1 /**
2 ******************************************************************************
3 * @file mfxstm32l152.c
4 * @author MCD Application Team
5 * @brief This file provides a set of functions needed to manage the MFXSTM32L152
6 * IO Expander devices.
7 ******************************************************************************
8 * @attention
9 *
10 * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
11 *
12 * Redistribution and use in source and binary forms, with or without modification,
13 * are permitted provided that the following conditions are met:
14 * 1. Redistributions of source code must retain the above copyright notice,
15 * this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright notice,
17 * this list of conditions and the following disclaimer in the documentation
18 * and/or other materials provided with the distribution.
19 * 3. Neither the name of STMicroelectronics nor the names of its contributors
20 * may be used to endorse or promote products derived from this software
21 * without specific prior written permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
30 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 *
34 ******************************************************************************
35 */
36
37 /* Includes ------------------------------------------------------------------*/
38 #include "mfxstm32l152.h"
39
40 /** @addtogroup BSP
41 * @{
42 */
43
44 /** @addtogroup Component
45 * @{
46 */
47
48 /** @defgroup MFXSTM32L152
49 * @{
50 */
51
52 /* Private typedef -----------------------------------------------------------*/
53
54 /** @defgroup MFXSTM32L152_Private_Types_Definitions
55 * @{
56 */
57
58 /* Private define ------------------------------------------------------------*/
59
60 /** @defgroup MFXSTM32L152_Private_Defines
61 * @{
62 */
63 #define MFXSTM32L152_MAX_INSTANCE 3
64
65 /* Private macro -------------------------------------------------------------*/
66
67 /** @defgroup MFXSTM32L152_Private_Macros
68 * @{
69 */
70
71 /* Private variables ---------------------------------------------------------*/
72
73 /** @defgroup MFXSTM32L152_Private_Variables
74 * @{
75 */
76
77 /* Touch screen driver structure initialization */
78 TS_DrvTypeDef mfxstm32l152_ts_drv =
79 {
80 mfxstm32l152_Init,
81 mfxstm32l152_ReadID,
82 mfxstm32l152_Reset,
83
84 mfxstm32l152_TS_Start,
85 mfxstm32l152_TS_DetectTouch,
86 mfxstm32l152_TS_GetXY,
87
88 mfxstm32l152_TS_EnableIT,
89 mfxstm32l152_TS_ClearIT,
90 mfxstm32l152_TS_ITStatus,
91 mfxstm32l152_TS_DisableIT,
92 };
93
94 /* IO driver structure initialization */
95 IO_DrvTypeDef mfxstm32l152_io_drv =
96 {
97 mfxstm32l152_Init,
98 mfxstm32l152_ReadID,
99 mfxstm32l152_Reset,
100
101 mfxstm32l152_IO_Start,
102 mfxstm32l152_IO_Config,
103 mfxstm32l152_IO_WritePin,
104 mfxstm32l152_IO_ReadPin,
105
106 mfxstm32l152_IO_EnableIT,
107 mfxstm32l152_IO_DisableIT,
108 mfxstm32l152_IO_ITStatus,
109 mfxstm32l152_IO_ClearIT,
110 };
111
112 /* IDD driver structure initialization */
113 IDD_DrvTypeDef mfxstm32l152_idd_drv =
114 {
115 mfxstm32l152_Init,
116 mfxstm32l152_DeInit,
117 mfxstm32l152_ReadID,
118 mfxstm32l152_Reset,
119 mfxstm32l152_LowPower,
120 mfxstm32l152_WakeUp,
121
122 mfxstm32l152_IDD_Start,
123 mfxstm32l152_IDD_Config,
124 mfxstm32l152_IDD_GetValue,
125
126 mfxstm32l152_IDD_EnableIT,
127 mfxstm32l152_IDD_ClearIT,
128 mfxstm32l152_IDD_GetITStatus,
129 mfxstm32l152_IDD_DisableIT,
130
131 mfxstm32l152_Error_EnableIT,
132 mfxstm32l152_Error_ClearIT,
133 mfxstm32l152_Error_GetITStatus,
134 mfxstm32l152_Error_DisableIT,
135 mfxstm32l152_Error_ReadSrc,
136 mfxstm32l152_Error_ReadMsg
137 };
138
139
140 /* mfxstm32l152 instances by address */
141 uint8_t mfxstm32l152[MFXSTM32L152_MAX_INSTANCE] = {0};
142 /**
143 * @}
144 */
145
146 /* Private function prototypes -----------------------------------------------*/
147
148 /** @defgroup MFXSTM32L152_Private_Function_Prototypes
149 * @{
150 */
151 static uint8_t mfxstm32l152_GetInstance(uint16_t DeviceAddr);
152 static uint8_t mfxstm32l152_ReleaseInstance(uint16_t DeviceAddr);
153 static void mfxstm32l152_reg24_setPinValue(uint16_t DeviceAddr, uint8_t RegisterAddr, uint32_t PinPosition, uint8_t PinValue );
154
155 /* Private functions ---------------------------------------------------------*/
156
157 /** @defgroup MFXSTM32L152_Private_Functions
158 * @{
159 */
160
161 /**
162 * @brief Initialize the mfxstm32l152 and configure the needed hardware resources
163 * @param DeviceAddr: Device address on communication Bus.
164 * @retval None
165 */
mfxstm32l152_Init(uint16_t DeviceAddr)166 void mfxstm32l152_Init(uint16_t DeviceAddr)
167 {
168 uint8_t instance;
169 uint8_t empty;
170
171 /* Check if device instance already exists */
172 instance = mfxstm32l152_GetInstance(DeviceAddr);
173
174 /* To prevent double initialization */
175 if(instance == 0xFF)
176 {
177 /* Look for empty instance */
178 empty = mfxstm32l152_GetInstance(0);
179
180 if(empty < MFXSTM32L152_MAX_INSTANCE)
181 {
182 /* Register the current device instance */
183 mfxstm32l152[empty] = DeviceAddr;
184
185 /* Initialize IO BUS layer */
186 MFX_IO_Init();
187 }
188 }
189
190 mfxstm32l152_SetIrqOutPinPolarity(DeviceAddr, MFXSTM32L152_OUT_PIN_POLARITY_HIGH);
191 mfxstm32l152_SetIrqOutPinType(DeviceAddr, MFXSTM32L152_OUT_PIN_TYPE_PUSHPULL);
192 }
193
194 /**
195 * @brief DeInitialize the mfxstm32l152 and unconfigure the needed hardware resources
196 * @param DeviceAddr: Device address on communication Bus.
197 * @retval None
198 */
mfxstm32l152_DeInit(uint16_t DeviceAddr)199 void mfxstm32l152_DeInit(uint16_t DeviceAddr)
200 {
201 uint8_t instance;
202
203 /* release existing instance */
204 instance = mfxstm32l152_ReleaseInstance(DeviceAddr);
205
206 /* De-Init only if instance was previously registered */
207 if(instance != 0xFF)
208 {
209 /* De-Initialize IO BUS layer */
210 MFX_IO_DeInit();
211 }
212 }
213
214 /**
215 * @brief Reset the mfxstm32l152 by Software.
216 * @param DeviceAddr: Device address on communication Bus.
217 * @retval None
218 */
mfxstm32l152_Reset(uint16_t DeviceAddr)219 void mfxstm32l152_Reset(uint16_t DeviceAddr)
220 {
221 /* Soft Reset */
222 MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_SYS_CTRL, MFXSTM32L152_SWRST);
223
224 /* Wait for a delay to ensure registers erasing */
225 rt_thread_delay(10);
226 }
227
228 /**
229 * @brief Put mfxstm32l152 Device in Low Power standby mode
230 * @param DeviceAddr: Device address on communication Bus.
231 * @retval None
232 */
mfxstm32l152_LowPower(uint16_t DeviceAddr)233 void mfxstm32l152_LowPower(uint16_t DeviceAddr)
234 {
235 /* Enter standby mode */
236 MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_SYS_CTRL, MFXSTM32L152_STANDBY);
237
238 /* enable wakeup pin */
239 MFX_IO_EnableWakeupPin();
240 }
241
242 /**
243 * @brief WakeUp mfxstm32l152 from standby mode
244 * @param DeviceAddr: Device address on communication Bus.
245 * @retval None
246 */
mfxstm32l152_WakeUp(uint16_t DeviceAddr)247 void mfxstm32l152_WakeUp(uint16_t DeviceAddr)
248 {
249 uint8_t instance;
250
251 /* Check if device instance already exists */
252 instance = mfxstm32l152_GetInstance(DeviceAddr);
253
254 /* if instance does not exist, first initialize pins*/
255 if(instance == 0xFF)
256 {
257 /* enable wakeup pin */
258 MFX_IO_EnableWakeupPin();
259 }
260
261 /* toggle wakeup pin */
262 MFX_IO_Wakeup();
263 }
264
265 /**
266 * @brief Read the MFXSTM32L152 IO Expander device ID.
267 * @param DeviceAddr: Device address on communication Bus.
268 * @retval The Device ID (two bytes).
269 */
mfxstm32l152_ReadID(uint16_t DeviceAddr)270 uint16_t mfxstm32l152_ReadID(uint16_t DeviceAddr)
271 {
272 uint8_t id;
273
274 /* Wait for a delay to ensure the state of registers */
275 rt_thread_mdelay(1);
276
277 /* Initialize IO BUS layer */
278 MFX_IO_Init();
279
280 id = MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_ID);
281
282 /* Return the device ID value */
283 return (id);
284 }
285
286 /**
287 * @brief Read the MFXSTM32L152 device firmware version.
288 * @param DeviceAddr: Device address on communication Bus.
289 * @retval The Device FW version (two bytes).
290 */
mfxstm32l152_ReadFwVersion(uint16_t DeviceAddr)291 uint16_t mfxstm32l152_ReadFwVersion(uint16_t DeviceAddr)
292 {
293 uint8_t data[2];
294
295 MFX_IO_ReadMultiple((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_FW_VERSION_MSB, data, sizeof(data)) ;
296
297 /* Recompose MFX firmware value */
298 return ((data[0] << 8) | data[1]);
299 }
300
301 /**
302 * @brief Enable the interrupt mode for the selected IT source
303 * @param DeviceAddr: Device address on communication Bus.
304 * @param Source: The interrupt source to be configured, could be:
305 * @arg MFXSTM32L152_IRQ_GPIO: IO interrupt
306 * @arg MFXSTM32L152_IRQ_IDD : IDD interrupt
307 * @arg MFXSTM32L152_IRQ_ERROR : Error interrupt
308 * @arg MFXSTM32L152_IRQ_TS_DET : Touch Screen Controller Touch Detected interrupt
309 * @arg MFXSTM32L152_IRQ_TS_NE : Touch Screen FIFO Not Empty
310 * @arg MFXSTM32L152_IRQ_TS_TH : Touch Screen FIFO threshold triggered
311 * @arg MFXSTM32L152_IRQ_TS_FULL : Touch Screen FIFO Full
312 * @arg MFXSTM32L152_IRQ_TS_OVF : Touch Screen FIFO Overflow
313 * @retval None
314 */
mfxstm32l152_EnableITSource(uint16_t DeviceAddr,uint8_t Source)315 void mfxstm32l152_EnableITSource(uint16_t DeviceAddr, uint8_t Source)
316 {
317 uint8_t tmp = 0;
318
319 /* Get the current value of the INT_EN register */
320 tmp = MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_SRC_EN);
321
322 /* Set the interrupts to be Enabled */
323 tmp |= Source;
324
325 /* Set the register */
326 MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_SRC_EN, tmp);
327 }
328
329 /**
330 * @brief Disable the interrupt mode for the selected IT source
331 * @param DeviceAddr: Device address on communication Bus.
332 * @param Source: The interrupt source to be configured, could be:
333 * @arg MFXSTM32L152_IRQ_GPIO: IO interrupt
334 * @arg MFXSTM32L152_IRQ_IDD : IDD interrupt
335 * @arg MFXSTM32L152_IRQ_ERROR : Error interrupt
336 * @arg MFXSTM32L152_IRQ_TS_DET : Touch Screen Controller Touch Detected interrupt
337 * @arg MFXSTM32L152_IRQ_TS_NE : Touch Screen FIFO Not Empty
338 * @arg MFXSTM32L152_IRQ_TS_TH : Touch Screen FIFO threshold triggered
339 * @arg MFXSTM32L152_IRQ_TS_FULL : Touch Screen FIFO Full
340 * @arg MFXSTM32L152_IRQ_TS_OVF : Touch Screen FIFO Overflow
341 * @retval None
342 */
mfxstm32l152_DisableITSource(uint16_t DeviceAddr,uint8_t Source)343 void mfxstm32l152_DisableITSource(uint16_t DeviceAddr, uint8_t Source)
344 {
345 uint8_t tmp = 0;
346
347 /* Get the current value of the INT_EN register */
348 tmp = MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_SRC_EN);
349
350 /* Set the interrupts to be Enabled */
351 tmp &= ~Source;
352
353 /* Set the register */
354 MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_SRC_EN, tmp);
355 }
356
357
358 /**
359 * @brief Returns the selected Global interrupt source pending bit value
360 * @param DeviceAddr: Device address on communication Bus.
361 * @param Source: the Global interrupt source to be checked, could be:
362 * @arg MFXSTM32L152_IRQ_GPIO: IO interrupt
363 * @arg MFXSTM32L152_IRQ_IDD : IDD interrupt
364 * @arg MFXSTM32L152_IRQ_ERROR : Error interrupt
365 * @arg MFXSTM32L152_IRQ_TS_DET : Touch Screen Controller Touch Detected interrupt
366 * @arg MFXSTM32L152_IRQ_TS_NE : Touch Screen FIFO Not Empty
367 * @arg MFXSTM32L152_IRQ_TS_TH : Touch Screen FIFO threshold triggered
368 * @arg MFXSTM32L152_IRQ_TS_FULL : Touch Screen FIFO Full
369 * @arg MFXSTM32L152_IRQ_TS_OVF : Touch Screen FIFO Overflow
370 * @retval The value of the checked Global interrupt source status.
371 */
mfxstm32l152_GlobalITStatus(uint16_t DeviceAddr,uint8_t Source)372 uint8_t mfxstm32l152_GlobalITStatus(uint16_t DeviceAddr, uint8_t Source)
373 {
374 /* Return the global IT source status (pending or not)*/
375 return((MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_PENDING) & Source));
376 }
377
378 /**
379 * @brief Clear the selected Global interrupt pending bit(s)
380 * @param DeviceAddr: Device address on communication Bus.
381 * @param Source: the Global interrupt source to be cleared, could be any combination
382 * of the below values. The acknowledge signal for MFXSTM32L152_GPIOs configured in input
383 * with interrupt is not on this register but in IRQ_GPI_ACK1, IRQ_GPI_ACK2 registers.
384 * @arg MFXSTM32L152_IRQ_IDD : IDD interrupt
385 * @arg MFXSTM32L152_IRQ_ERROR : Error interrupt
386 * @arg MFXSTM32L152_IRQ_TS_DET : Touch Screen Controller Touch Detected interrupt
387 * @arg MFXSTM32L152_IRQ_TS_NE : Touch Screen FIFO Not Empty
388 * @arg MFXSTM32L152_IRQ_TS_TH : Touch Screen FIFO threshold triggered
389 * @arg MFXSTM32L152_IRQ_TS_FULL : Touch Screen FIFO Full
390 * @arg MFXSTM32L152_IRQ_TS_OVF : Touch Screen FIFO Overflow
391 * /\/\ IMPORTANT NOTE /\/\ must not use MFXSTM32L152_IRQ_GPIO as argument, see IRQ_GPI_ACK1 and IRQ_GPI_ACK2 registers
392 * @retval None
393 */
mfxstm32l152_ClearGlobalIT(uint16_t DeviceAddr,uint8_t Source)394 void mfxstm32l152_ClearGlobalIT(uint16_t DeviceAddr, uint8_t Source)
395 {
396 /* Write 1 to the bits that have to be cleared */
397 MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_ACK, Source);
398 }
399
400 /**
401 * @brief Set the global interrupt Polarity of IRQ_OUT_PIN.
402 * @param DeviceAddr: Device address on communication Bus.
403 * @param Polarity: the IT mode polarity, could be one of the following values:
404 * @arg MFXSTM32L152_OUT_PIN_POLARITY_LOW: Interrupt output line is active Low edge
405 * @arg MFXSTM32L152_OUT_PIN_POLARITY_HIGH: Interrupt line output is active High edge
406 * @retval None
407 */
mfxstm32l152_SetIrqOutPinPolarity(uint16_t DeviceAddr,uint8_t Polarity)408 void mfxstm32l152_SetIrqOutPinPolarity(uint16_t DeviceAddr, uint8_t Polarity)
409 {
410 uint8_t tmp = 0;
411
412 /* Get the current register value */
413 tmp = MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_MFX_IRQ_OUT);
414
415 /* Mask the polarity bits */
416 tmp &= ~(uint8_t)0x02;
417
418 /* Modify the Interrupt Output line configuration */
419 tmp |= Polarity;
420
421 /* Set the new register value */
422 MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_MFX_IRQ_OUT, tmp);
423
424 /* Wait for 1 ms for MFX to change IRQ_out pin config, before activate it */
425 rt_thread_delay(1);
426
427 }
428
429 /**
430 * @brief Set the global interrupt Type of IRQ_OUT_PIN.
431 * @param DeviceAddr: Device address on communication Bus.
432 * @param Type: Interrupt line activity type, could be one of the following values:
433 * @arg MFXSTM32L152_OUT_PIN_TYPE_OPENDRAIN: Open Drain output Interrupt line
434 * @arg MFXSTM32L152_OUT_PIN_TYPE_PUSHPULL: Push Pull output Interrupt line
435 * @retval None
436 */
mfxstm32l152_SetIrqOutPinType(uint16_t DeviceAddr,uint8_t Type)437 void mfxstm32l152_SetIrqOutPinType(uint16_t DeviceAddr, uint8_t Type)
438 {
439 uint8_t tmp = 0;
440
441 /* Get the current register value */
442 tmp = MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_MFX_IRQ_OUT);
443
444 /* Mask the type bits */
445 tmp &= ~(uint8_t)0x01;
446
447 /* Modify the Interrupt Output line configuration */
448 tmp |= Type;
449
450 /* Set the new register value */
451 MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_MFX_IRQ_OUT, tmp);
452
453 /* Wait for 1 ms for MFX to change IRQ_out pin config, before activate it */
454 rt_thread_delay(1);
455
456 }
457
458
459 /* ------------------------------------------------------------------ */
460 /* ----------------------- GPIO ------------------------------------- */
461 /* ------------------------------------------------------------------ */
462
463
464 /**
465 * @brief Start the IO functionality used and enable the AF for selected IO pin(s).
466 * @param DeviceAddr: Device address on communication Bus.
467 * @param AF_en: 0 to disable, else enabled.
468 * @retval None
469 */
mfxstm32l152_IO_Start(uint16_t DeviceAddr,uint32_t IO_Pin)470 void mfxstm32l152_IO_Start(uint16_t DeviceAddr, uint32_t IO_Pin)
471 {
472 uint8_t mode;
473
474 /* Get the current register value */
475 mode = MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_SYS_CTRL);
476
477 /* Set the IO Functionalities to be Enabled */
478 mode |= MFXSTM32L152_GPIO_EN;
479
480 /* Enable ALTERNATE functions */
481 /* AGPIO[0..3] can be either IDD or GPIO */
482 /* AGPIO[4..7] can be either TS or GPIO */
483 /* if IDD or TS are enabled no matter the value this bit GPIO are not available for those pins */
484 /* however the MFX will waste some cycles to to handle these potential GPIO (pooling, etc) */
485 /* so if IDD and TS are both active it is better to let ALTERNATE off (0) */
486 /* if however IDD or TS are not connected then set it on gives more GPIOs availability */
487 /* remind that AGPIO are less efficient then normal GPIO (They use pooling rather then EXTI */
488 if (IO_Pin > 0xFFFF)
489 {
490 mode |= MFXSTM32L152_ALTERNATE_GPIO_EN;
491 }
492 else
493 {
494 mode &= ~MFXSTM32L152_ALTERNATE_GPIO_EN;
495 }
496
497 /* Write the new register value */
498 MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_SYS_CTRL, mode);
499
500 /* Wait for 1 ms for MFX to change IRQ_out pin config, before activate it */
501 rt_thread_delay(1);
502 }
503
504 /**
505 * @brief Configures the IO pin(s) according to IO mode structure value.
506 * @param DeviceAddr: Device address on communication Bus.
507 * @param IO_Pin: The output pin to be set or reset. This parameter can be one
508 * of the following values:
509 * @arg MFXSTM32L152_GPIO_PIN_x: where x can be from 0 to 23.
510 * @param IO_Mode: The IO pin mode to configure, could be one of the following values:
511 * @arg IO_MODE_INPUT
512 * @arg IO_MODE_OUTPUT
513 * @arg IO_MODE_IT_RISING_EDGE
514 * @arg IO_MODE_IT_FALLING_EDGE
515 * @arg IO_MODE_IT_LOW_LEVEL
516 * @arg IO_MODE_IT_HIGH_LEVEL
517 * @arg IO_MODE_INPUT_PU,
518 * @arg IO_MODE_INPUT_PD,
519 * @arg IO_MODE_OUTPUT_OD_PU,
520 * @arg IO_MODE_OUTPUT_OD_PD,
521 * @arg IO_MODE_OUTPUT_PP_PU,
522 * @arg IO_MODE_OUTPUT_PP_PD,
523 * @arg IO_MODE_IT_RISING_EDGE_PU
524 * @arg IO_MODE_IT_FALLING_EDGE_PU
525 * @arg IO_MODE_IT_LOW_LEVEL_PU
526 * @arg IO_MODE_IT_HIGH_LEVEL_PU
527 * @arg IO_MODE_IT_RISING_EDGE_PD
528 * @arg IO_MODE_IT_FALLING_EDGE_PD
529 * @arg IO_MODE_IT_LOW_LEVEL_PD
530 * @arg IO_MODE_IT_HIGH_LEVEL_PD
531 * @retval None
532 */
mfxstm32l152_IO_Config(uint16_t DeviceAddr,uint32_t IO_Pin,IO_ModeTypedef IO_Mode)533 uint8_t mfxstm32l152_IO_Config(uint16_t DeviceAddr, uint32_t IO_Pin, IO_ModeTypedef IO_Mode)
534 {
535 uint8_t error_code = 0;
536
537 /* Configure IO pin according to selected IO mode */
538 switch(IO_Mode)
539 {
540 case IO_MODE_OFF: /* Off or analog mode */
541 case IO_MODE_ANALOG: /* Off or analog mode */
542 mfxstm32l152_IO_DisablePinIT(DeviceAddr, IO_Pin); /* first disable IT */
543 mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN);
544 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITHOUT_PULL_RESISTOR);
545 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_DOWN);
546 break;
547
548 case IO_MODE_INPUT: /* Input mode */
549 mfxstm32l152_IO_DisablePinIT(DeviceAddr, IO_Pin); /* first disable IT */
550 mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN);
551 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITHOUT_PULL_RESISTOR);
552 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_UP);
553 break;
554
555 case IO_MODE_INPUT_PU: /* Input mode */
556 mfxstm32l152_IO_DisablePinIT(DeviceAddr, IO_Pin); /* first disable IT */
557 mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN);
558 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITH_PULL_RESISTOR);
559 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_UP);
560 break;
561
562 case IO_MODE_INPUT_PD: /* Input mode */
563 mfxstm32l152_IO_DisablePinIT(DeviceAddr, IO_Pin); /* first disable IT */
564 mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN);
565 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITH_PULL_RESISTOR);
566 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_DOWN);
567 break;
568
569 case IO_MODE_OUTPUT: /* Output mode */
570 case IO_MODE_OUTPUT_PP_PD: /* Output mode */
571 mfxstm32l152_IO_DisablePinIT(DeviceAddr, IO_Pin); /* first disable IT */
572 mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_OUT);
573 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPO_PUSH_PULL);
574 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_DOWN);
575 break;
576
577 case IO_MODE_OUTPUT_PP_PU: /* Output mode */
578 mfxstm32l152_IO_DisablePinIT(DeviceAddr, IO_Pin); /* first disable IT */
579 mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_OUT);
580 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPO_PUSH_PULL);
581 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_UP);
582 break;
583
584 case IO_MODE_OUTPUT_OD_PD: /* Output mode */
585 mfxstm32l152_IO_DisablePinIT(DeviceAddr, IO_Pin); /* first disable IT */
586 mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_OUT);
587 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPO_OPEN_DRAIN);
588 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_DOWN);
589 break;
590
591 case IO_MODE_OUTPUT_OD_PU: /* Output mode */
592 mfxstm32l152_IO_DisablePinIT(DeviceAddr, IO_Pin); /* first disable IT */
593 mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_OUT);
594 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPO_OPEN_DRAIN);
595 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_UP);
596 break;
597
598 case IO_MODE_IT_RISING_EDGE: /* Interrupt rising edge mode */
599 mfxstm32l152_IO_EnableIT(DeviceAddr);
600 mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN);
601 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITHOUT_PULL_RESISTOR);
602 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_UP);
603 mfxstm32l152_IO_SetIrqEvtMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_EVT_EDGE);
604 mfxstm32l152_IO_SetIrqTypeMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_TYPE_HLRE);
605 mfxstm32l152_IO_EnablePinIT(DeviceAddr, IO_Pin); /* last to do: enable IT */
606 break;
607
608 case IO_MODE_IT_RISING_EDGE_PU: /* Interrupt rising edge mode */
609 mfxstm32l152_IO_EnableIT(DeviceAddr);
610 mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN);
611 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITH_PULL_RESISTOR);
612 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_UP);
613 mfxstm32l152_IO_SetIrqEvtMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_EVT_EDGE);
614 mfxstm32l152_IO_SetIrqTypeMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_TYPE_HLRE);
615 mfxstm32l152_IO_EnablePinIT(DeviceAddr, IO_Pin); /* last to do: enable IT */
616 break;
617
618 case IO_MODE_IT_RISING_EDGE_PD: /* Interrupt rising edge mode */
619 mfxstm32l152_IO_EnableIT(DeviceAddr);
620 mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN);
621 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITH_PULL_RESISTOR);
622 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_DOWN);
623 mfxstm32l152_IO_SetIrqEvtMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_EVT_EDGE);
624 mfxstm32l152_IO_SetIrqTypeMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_TYPE_HLRE);
625 mfxstm32l152_IO_EnablePinIT(DeviceAddr, IO_Pin); /* last to do: enable IT */
626 break;
627
628 case IO_MODE_IT_FALLING_EDGE: /* Interrupt falling edge mode */
629 mfxstm32l152_IO_EnableIT(DeviceAddr);
630 mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN);
631 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITHOUT_PULL_RESISTOR);
632 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_UP);
633 mfxstm32l152_IO_SetIrqEvtMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_EVT_EDGE);
634 mfxstm32l152_IO_SetIrqTypeMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_TYPE_LLFE);
635 mfxstm32l152_IO_EnablePinIT(DeviceAddr, IO_Pin); /* last to do: enable IT */
636 break;
637
638 case IO_MODE_IT_FALLING_EDGE_PU: /* Interrupt falling edge mode */
639 mfxstm32l152_IO_EnableIT(DeviceAddr);
640 mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN);
641 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITH_PULL_RESISTOR);
642 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_UP);
643 mfxstm32l152_IO_SetIrqEvtMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_EVT_EDGE);
644 mfxstm32l152_IO_SetIrqTypeMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_TYPE_LLFE);
645 mfxstm32l152_IO_EnablePinIT(DeviceAddr, IO_Pin); /* last to do: enable IT */
646 break;
647
648 case IO_MODE_IT_FALLING_EDGE_PD: /* Interrupt falling edge mode */
649 mfxstm32l152_IO_EnableIT(DeviceAddr);
650 mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN);
651 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITH_PULL_RESISTOR);
652 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_DOWN);
653 mfxstm32l152_IO_SetIrqEvtMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_EVT_EDGE);
654 mfxstm32l152_IO_SetIrqTypeMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_TYPE_LLFE);
655 mfxstm32l152_IO_EnablePinIT(DeviceAddr, IO_Pin); /* last to do: enable IT */
656 break;
657
658 case IO_MODE_IT_LOW_LEVEL: /* Low level interrupt mode */
659 mfxstm32l152_IO_EnableIT(DeviceAddr);
660 mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN);
661 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITHOUT_PULL_RESISTOR);
662 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_UP);
663 mfxstm32l152_IO_SetIrqEvtMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_EVT_LEVEL);
664 mfxstm32l152_IO_SetIrqTypeMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_TYPE_LLFE);
665 mfxstm32l152_IO_EnablePinIT(DeviceAddr, IO_Pin); /* last to do: enable IT */
666 break;
667
668 case IO_MODE_IT_LOW_LEVEL_PU: /* Low level interrupt mode */
669 mfxstm32l152_IO_EnableIT(DeviceAddr);
670 mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN);
671 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITH_PULL_RESISTOR);
672 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_UP);
673 mfxstm32l152_IO_SetIrqEvtMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_EVT_LEVEL);
674 mfxstm32l152_IO_SetIrqTypeMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_TYPE_LLFE);
675 mfxstm32l152_IO_EnablePinIT(DeviceAddr, IO_Pin); /* last to do: enable IT */
676 break;
677
678 case IO_MODE_IT_LOW_LEVEL_PD: /* Low level interrupt mode */
679 mfxstm32l152_IO_EnableIT(DeviceAddr);
680 mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN);
681 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITH_PULL_RESISTOR);
682 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_DOWN);
683 mfxstm32l152_IO_SetIrqEvtMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_EVT_LEVEL);
684 mfxstm32l152_IO_SetIrqTypeMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_TYPE_LLFE);
685 mfxstm32l152_IO_EnablePinIT(DeviceAddr, IO_Pin); /* last to do: enable IT */
686 break;
687
688 case IO_MODE_IT_HIGH_LEVEL: /* High level interrupt mode */
689 mfxstm32l152_IO_EnableIT(DeviceAddr);
690 mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN);
691 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITHOUT_PULL_RESISTOR);
692 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_UP);
693 mfxstm32l152_IO_SetIrqEvtMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_EVT_LEVEL);
694 mfxstm32l152_IO_SetIrqTypeMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_TYPE_HLRE);
695 mfxstm32l152_IO_EnablePinIT(DeviceAddr, IO_Pin); /* last to do: enable IT */
696 break;
697
698 case IO_MODE_IT_HIGH_LEVEL_PU: /* High level interrupt mode */
699 mfxstm32l152_IO_EnableIT(DeviceAddr);
700 mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN);
701 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITH_PULL_RESISTOR);
702 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_UP);
703 mfxstm32l152_IO_SetIrqEvtMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_EVT_LEVEL);
704 mfxstm32l152_IO_SetIrqTypeMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_TYPE_HLRE);
705 mfxstm32l152_IO_EnablePinIT(DeviceAddr, IO_Pin); /* last to do: enable IT */
706 break;
707
708 case IO_MODE_IT_HIGH_LEVEL_PD: /* High level interrupt mode */
709 mfxstm32l152_IO_EnableIT(DeviceAddr);
710 mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN);
711 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITH_PULL_RESISTOR);
712 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_DOWN);
713 mfxstm32l152_IO_SetIrqEvtMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_EVT_LEVEL);
714 mfxstm32l152_IO_SetIrqTypeMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_TYPE_HLRE);
715 mfxstm32l152_IO_EnablePinIT(DeviceAddr, IO_Pin); /* last to do: enable IT */
716 break;
717
718 default:
719 error_code = (uint8_t) IO_Mode;
720 break;
721 }
722
723 return error_code;
724 }
725
726 /**
727 * @brief Initialize the selected IO pin direction.
728 * @param DeviceAddr: Device address on communication Bus.
729 * @param IO_Pin: The IO pin to be configured. This parameter could be any
730 * combination of the following values:
731 * @arg MFXSTM32L152_GPIO_PIN_x: Where x can be from 0 to 23.
732 * @param Direction: could be MFXSTM32L152_GPIO_DIR_IN or MFXSTM32L152_GPIO_DIR_OUT.
733 * @retval None
734 */
mfxstm32l152_IO_InitPin(uint16_t DeviceAddr,uint32_t IO_Pin,uint8_t Direction)735 void mfxstm32l152_IO_InitPin(uint16_t DeviceAddr, uint32_t IO_Pin, uint8_t Direction)
736 {
737 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_DIR1, IO_Pin, Direction);
738 }
739
740 /**
741 * @brief Set the global interrupt Type.
742 * @param DeviceAddr: Device address on communication Bus.
743 * @param IO_Pin: The IO pin to be configured. This parameter could be any
744 * combination of the following values:
745 * @arg MFXSTM32L152_GPIO_PIN_x: Where x can be from 0 to 23.
746 * @param Evt: Interrupt line activity type, could be one of the following values:
747 * @arg MFXSTM32L152_IRQ_GPI_EVT_LEVEL: Interrupt line is active in level model
748 * @arg MFXSTM32L152_IRQ_GPI_EVT_EDGE: Interrupt line is active in edge model
749 * @retval None
750 */
mfxstm32l152_IO_SetIrqEvtMode(uint16_t DeviceAddr,uint32_t IO_Pin,uint8_t Evt)751 void mfxstm32l152_IO_SetIrqEvtMode(uint16_t DeviceAddr, uint32_t IO_Pin, uint8_t Evt)
752 {
753 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_GPI_EVT1, IO_Pin, Evt);
754 rt_thread_delay(1);
755 }
756
757 /**
758 * @brief Configure the Edge for which a transition is detectable for the
759 * selected pin.
760 * @param DeviceAddr: Device address on communication Bus.
761 * @param IO_Pin: The IO pin to be configured. This parameter could be any
762 * combination of the following values:
763 * @arg MFXSTM32L152_GPIO_PIN_x: Where x can be from 0 to 23.
764 * @param Evt: Interrupt line activity type, could be one of the following values:
765 * @arg MFXSTM32L152_IRQ_GPI_TYPE_LLFE: Interrupt line is active in Low Level or Falling Edge
766 * @arg MFXSTM32L152_IRQ_GPI_TYPE_HLRE: Interrupt line is active in High Level or Rising Edge
767 * @retval None
768 */
mfxstm32l152_IO_SetIrqTypeMode(uint16_t DeviceAddr,uint32_t IO_Pin,uint8_t Type)769 void mfxstm32l152_IO_SetIrqTypeMode(uint16_t DeviceAddr, uint32_t IO_Pin, uint8_t Type)
770 {
771 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_GPI_TYPE1, IO_Pin, Type);
772 rt_thread_delay(1);
773 }
774
775 /**
776 * @brief When GPIO is in output mode, puts the corresponding GPO in High (1) or Low (0) level.
777 * @param DeviceAddr: Device address on communication Bus.
778 * @param IO_Pin: The output pin to be set or reset. This parameter can be one
779 * of the following values:
780 * @arg MFXSTM32L152_GPIO_PIN_x: where x can be from 0 to 23.
781 * @param PinState: The new IO pin state.
782 * @retval None
783 */
mfxstm32l152_IO_WritePin(uint16_t DeviceAddr,uint32_t IO_Pin,uint8_t PinState)784 void mfxstm32l152_IO_WritePin(uint16_t DeviceAddr, uint32_t IO_Pin, uint8_t PinState)
785 {
786 /* Apply the bit value to the selected pin */
787 if (PinState != 0)
788 {
789 /* Set the SET register */
790 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPO_SET1, IO_Pin, 1);
791 }
792 else
793 {
794 /* Set the CLEAR register */
795 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPO_CLR1, IO_Pin, 1);
796 }
797 }
798
799 /**
800 * @brief Return the state of the selected IO pin(s).
801 * @param DeviceAddr: Device address on communication Bus.
802 * @param IO_Pin: The output pin to be set or reset. This parameter can be one
803 * of the following values:
804 * @arg MFXSTM32L152_GPIO_PIN_x: where x can be from 0 to 23.
805 * @retval IO pin(s) state.
806 */
mfxstm32l152_IO_ReadPin(uint16_t DeviceAddr,uint32_t IO_Pin)807 uint32_t mfxstm32l152_IO_ReadPin(uint16_t DeviceAddr, uint32_t IO_Pin)
808 {
809 uint32_t tmp1 = 0;
810 uint32_t tmp2 = 0;
811 uint32_t tmp3 = 0;
812
813 if(IO_Pin & 0x000000FF)
814 {
815 tmp1 = (uint32_t) MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_STATE1);
816 }
817 if(IO_Pin & 0x0000FF00)
818 {
819 tmp2 = (uint32_t) MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_STATE2);
820 }
821 if(IO_Pin & 0x00FF0000)
822 {
823 tmp3 = (uint32_t) MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_STATE3);
824 }
825
826 tmp3 = tmp1 + (tmp2 << 8) + (tmp3 << 16);
827
828 return(tmp3 & IO_Pin);
829 }
830
831 /**
832 * @brief Enable the global IO interrupt source.
833 * @param DeviceAddr: Device address on communication Bus.
834 * @retval None
835 */
mfxstm32l152_IO_EnableIT(uint16_t DeviceAddr)836 void mfxstm32l152_IO_EnableIT(uint16_t DeviceAddr)
837 {
838 MFX_IO_ITConfig();
839
840 /* Enable global IO IT source */
841 mfxstm32l152_EnableITSource(DeviceAddr, MFXSTM32L152_IRQ_GPIO);
842 }
843
844 /**
845 * @brief Disable the global IO interrupt source.
846 * @param DeviceAddr: Device address on communication Bus.
847 * @retval None
848 */
mfxstm32l152_IO_DisableIT(uint16_t DeviceAddr)849 void mfxstm32l152_IO_DisableIT(uint16_t DeviceAddr)
850 {
851 /* Disable global IO IT source */
852 mfxstm32l152_DisableITSource(DeviceAddr, MFXSTM32L152_IRQ_GPIO);
853 }
854
855 /**
856 * @brief Enable interrupt mode for the selected IO pin(s).
857 * @param DeviceAddr: Device address on communication Bus.
858 * @param IO_Pin: The IO interrupt to be enabled. This parameter could be any
859 * combination of the following values:
860 * @arg MFXSTM32L152_GPIO_PIN_x: where x can be from 0 to 23.
861 * @retval None
862 */
mfxstm32l152_IO_EnablePinIT(uint16_t DeviceAddr,uint32_t IO_Pin)863 void mfxstm32l152_IO_EnablePinIT(uint16_t DeviceAddr, uint32_t IO_Pin)
864 {
865 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_GPI_SRC1, IO_Pin, 1);
866 }
867
868 /**
869 * @brief Disable interrupt mode for the selected IO pin(s).
870 * @param DeviceAddr: Device address on communication Bus.
871 * @param IO_Pin: The IO interrupt to be disabled. This parameter could be any
872 * combination of the following values:
873 * @arg MFXSTM32L152_GPIO_PIN_x: where x can be from 0 to 23.
874 * @retval None
875 */
mfxstm32l152_IO_DisablePinIT(uint16_t DeviceAddr,uint32_t IO_Pin)876 void mfxstm32l152_IO_DisablePinIT(uint16_t DeviceAddr, uint32_t IO_Pin)
877 {
878 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_GPI_SRC1, IO_Pin, 0);
879 }
880
881
882 /**
883 * @brief Check the status of the selected IO interrupt pending bit
884 * @param DeviceAddr: Device address on communication Bus.
885 * @param IO_Pin: The IO interrupt to be checked could be:
886 * @arg MFXSTM32L152_GPIO_PIN_x Where x can be from 0 to 23.
887 * @retval Status of the checked IO pin(s).
888 */
mfxstm32l152_IO_ITStatus(uint16_t DeviceAddr,uint32_t IO_Pin)889 uint32_t mfxstm32l152_IO_ITStatus(uint16_t DeviceAddr, uint32_t IO_Pin)
890 {
891 /* Get the Interrupt status */
892 uint8_t tmp1 = 0;
893 uint16_t tmp2 = 0;
894 uint32_t tmp3 = 0;
895
896 if(IO_Pin & 0xFF)
897 {
898 tmp1 = MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_GPI_PENDING1);
899 }
900 if(IO_Pin & 0xFFFF00)
901 {
902 tmp2 = (uint16_t) MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_GPI_PENDING2);
903 }
904 if(IO_Pin & 0xFFFF0000)
905 {
906 tmp3 = (uint32_t) MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_GPI_PENDING3);
907 }
908
909 tmp3 = tmp1 + (tmp2 << 8) + (tmp3 << 16);
910
911 return(tmp3 & IO_Pin);
912 }
913
914 /**
915 * @brief Clear the selected IO interrupt pending bit(s). It clear automatically also the general MFXSTM32L152_REG_ADR_IRQ_PENDING
916 * @param DeviceAddr: Device address on communication Bus.
917 * @param IO_Pin: the IO interrupt to be cleared, could be:
918 * @arg MFXSTM32L152_GPIO_PIN_x: Where x can be from 0 to 23.
919 * @retval None
920 */
mfxstm32l152_IO_ClearIT(uint16_t DeviceAddr,uint32_t IO_Pin)921 void mfxstm32l152_IO_ClearIT(uint16_t DeviceAddr, uint32_t IO_Pin)
922 {
923 /* Clear the IO IT pending bit(s) by acknowledging */
924 /* it cleans automatically also the Global IRQ_GPIO */
925 /* normally this function is called under interrupt */
926 uint8_t pin_0_7, pin_8_15, pin_16_23;
927
928 pin_0_7 = IO_Pin & 0x0000ff;
929 pin_8_15 = IO_Pin >> 8;
930 pin_8_15 = pin_8_15 & 0x00ff;
931 pin_16_23 = IO_Pin >> 16;
932
933 if (pin_0_7)
934 {
935 MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_GPI_ACK1, pin_0_7);
936 }
937 if (pin_8_15)
938 {
939 MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_GPI_ACK2, pin_8_15);
940 }
941 if (pin_16_23)
942 {
943 MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_GPI_ACK3, pin_16_23);
944 }
945 }
946
947
948 /**
949 * @brief Enable the AF for aGPIO.
950 * @param DeviceAddr: Device address on communication Bus.
951 * @retval None
952 */
mfxstm32l152_IO_EnableAF(uint16_t DeviceAddr)953 void mfxstm32l152_IO_EnableAF(uint16_t DeviceAddr)
954 {
955 uint8_t mode;
956
957 /* Get the current register value */
958 mode = MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_SYS_CTRL);
959
960 /* Enable ALTERNATE functions */
961 /* AGPIO[0..3] can be either IDD or GPIO */
962 /* AGPIO[4..7] can be either TS or GPIO */
963 /* if IDD or TS are enabled no matter the value this bit GPIO are not available for those pins */
964 /* however the MFX will waste some cycles to to handle these potential GPIO (pooling, etc) */
965 /* so if IDD and TS are both active it is better to let ALTERNATE disabled (0) */
966 /* if however IDD or TS are not connected then set it on gives more GPIOs availability */
967 /* remind that AGPIO are less efficient then normal GPIO (they use pooling rather then EXTI) */
968 mode |= MFXSTM32L152_ALTERNATE_GPIO_EN;
969
970 /* Write the new register value */
971 MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_SYS_CTRL, mode);
972 }
973
974 /**
975 * @brief Disable the AF for aGPIO.
976 * @param DeviceAddr: Device address on communication Bus.
977 * @retval None
978 */
mfxstm32l152_IO_DisableAF(uint16_t DeviceAddr)979 void mfxstm32l152_IO_DisableAF(uint16_t DeviceAddr)
980 {
981 uint8_t mode;
982
983 /* Get the current register value */
984 mode = MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_SYS_CTRL);
985
986 /* Enable ALTERNATE functions */
987 /* AGPIO[0..3] can be either IDD or GPIO */
988 /* AGPIO[4..7] can be either TS or GPIO */
989 /* if IDD or TS are enabled no matter the value this bit GPIO are not available for those pins */
990 /* however the MFX will waste some cycles to to handle these potential GPIO (pooling, etc) */
991 /* so if IDD and TS are both active it is better to let ALTERNATE disabled (0) */
992 /* if however IDD or TS are not connected then set it on gives more GPIOs availability */
993 /* remind that AGPIO are less efficient then normal GPIO (they use pooling rather then EXTI) */
994 mode &= ~MFXSTM32L152_ALTERNATE_GPIO_EN;
995
996 /* Write the new register value */
997 MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_SYS_CTRL, mode);
998
999 }
1000
1001
1002 /* ------------------------------------------------------------------ */
1003 /* --------------------- TOUCH SCREEN ------------------------------- */
1004 /* ------------------------------------------------------------------ */
1005
1006 /**
1007 * @brief Configures the touch Screen Controller (Single point detection)
1008 * @param DeviceAddr: Device address on communication Bus.
1009 * @retval None.
1010 */
mfxstm32l152_TS_Start(uint16_t DeviceAddr)1011 void mfxstm32l152_TS_Start(uint16_t DeviceAddr)
1012 {
1013 uint8_t mode;
1014
1015 /* Get the current register value */
1016 mode = MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_SYS_CTRL);
1017
1018 /* Set the Functionalities to be Enabled */
1019 mode |= MFXSTM32L152_TS_EN;
1020
1021 /* Set the new register value */
1022 MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_SYS_CTRL, mode);
1023
1024 /* Wait for 2 ms */
1025 rt_thread_delay(2);
1026
1027 /* Select 2 nF filter capacitor */
1028 /* Configuration:
1029 - Touch average control : 4 samples
1030 - Touch delay time : 500 uS
1031 - Panel driver setting time: 500 uS
1032 */
1033 MFX_IO_Write(DeviceAddr, MFXSTM32L152_TS_SETTLING, 0x32);
1034 MFX_IO_Write(DeviceAddr, MFXSTM32L152_TS_TOUCH_DET_DELAY, 0x5);
1035 MFX_IO_Write(DeviceAddr, MFXSTM32L152_TS_AVE, 0x04);
1036
1037 /* Configure the Touch FIFO threshold: single point reading */
1038 MFX_IO_Write(DeviceAddr, MFXSTM32L152_TS_FIFO_TH, 0x01);
1039
1040 /* Clear the FIFO memory content. */
1041 MFX_IO_Write(DeviceAddr, MFXSTM32L152_TS_FIFO_TH, MFXSTM32L152_TS_CLEAR_FIFO);
1042
1043 /* Touch screen control configuration :
1044 - No window tracking index
1045 */
1046 MFX_IO_Write(DeviceAddr, MFXSTM32L152_TS_TRACK, 0x00);
1047
1048
1049 /* Clear all the IT status pending bits if any */
1050 mfxstm32l152_IO_ClearIT(DeviceAddr, 0xFFFFFF);
1051
1052 /* Wait for 1 ms delay */
1053 rt_thread_delay(1);
1054 }
1055
1056 /**
1057 * @brief Return if there is touch detected or not.
1058 * @param DeviceAddr: Device address on communication Bus.
1059 * @retval Touch detected state.
1060 */
mfxstm32l152_TS_DetectTouch(uint16_t DeviceAddr)1061 uint8_t mfxstm32l152_TS_DetectTouch(uint16_t DeviceAddr)
1062 {
1063 uint8_t state;
1064 uint8_t ret = 0;
1065
1066 state = MFX_IO_Read(DeviceAddr, MFXSTM32L152_TS_FIFO_STA);
1067 state = ((state & (uint8_t)MFXSTM32L152_TS_CTRL_STATUS) == (uint8_t)MFXSTM32L152_TS_CTRL_STATUS);
1068
1069 if(state > 0)
1070 {
1071 if(MFX_IO_Read(DeviceAddr, MFXSTM32L152_TS_FIFO_LEVEL) > 0)
1072 {
1073 ret = 1;
1074 }
1075 }
1076
1077 return ret;
1078 }
1079
1080 /**
1081 * @brief Get the touch screen X and Y positions values
1082 * @param DeviceAddr: Device address on communication Bus.
1083 * @param X: Pointer to X position value
1084 * @param Y: Pointer to Y position value
1085 * @retval None.
1086 */
mfxstm32l152_TS_GetXY(uint16_t DeviceAddr,uint16_t * X,uint16_t * Y)1087 void mfxstm32l152_TS_GetXY(uint16_t DeviceAddr, uint16_t *X, uint16_t *Y)
1088 {
1089 uint8_t data_xy[3];
1090
1091 MFX_IO_ReadMultiple(DeviceAddr, MFXSTM32L152_TS_XY_DATA, data_xy, sizeof(data_xy)) ;
1092
1093 /* Calculate positions values */
1094 *X = (data_xy[1]<<4) + (data_xy[0]>>4);
1095 *Y = (data_xy[2]<<4) + (data_xy[0]&4);
1096
1097 /* Reset the FIFO memory content. */
1098 MFX_IO_Write(DeviceAddr, MFXSTM32L152_TS_FIFO_TH, MFXSTM32L152_TS_CLEAR_FIFO);
1099 }
1100
1101 /**
1102 * @brief Configure the selected source to generate a global interrupt or not
1103 * @param DeviceAddr: Device address on communication Bus.
1104 * @retval None
1105 */
mfxstm32l152_TS_EnableIT(uint16_t DeviceAddr)1106 void mfxstm32l152_TS_EnableIT(uint16_t DeviceAddr)
1107 {
1108 MFX_IO_ITConfig();
1109
1110 /* Enable global TS IT source */
1111 mfxstm32l152_EnableITSource(DeviceAddr, MFXSTM32L152_IRQ_TS_DET);
1112 }
1113
1114 /**
1115 * @brief Configure the selected source to generate a global interrupt or not
1116 * @param DeviceAddr: Device address on communication Bus.
1117 * @retval None
1118 */
mfxstm32l152_TS_DisableIT(uint16_t DeviceAddr)1119 void mfxstm32l152_TS_DisableIT(uint16_t DeviceAddr)
1120 {
1121 /* Disable global TS IT source */
1122 mfxstm32l152_DisableITSource(DeviceAddr, MFXSTM32L152_IRQ_TS_DET);
1123 }
1124
1125 /**
1126 * @brief Configure the selected source to generate a global interrupt or not
1127 * @param DeviceAddr: Device address on communication Bus.
1128 * @retval TS interrupts status
1129 */
mfxstm32l152_TS_ITStatus(uint16_t DeviceAddr)1130 uint8_t mfxstm32l152_TS_ITStatus(uint16_t DeviceAddr)
1131 {
1132 /* Return TS interrupts status */
1133 return(mfxstm32l152_GlobalITStatus(DeviceAddr, MFXSTM32L152_IRQ_TS));
1134 }
1135
1136 /**
1137 * @brief Configure the selected source to generate a global interrupt or not
1138 * @param DeviceAddr: Device address on communication Bus.
1139 * @retval None
1140 */
mfxstm32l152_TS_ClearIT(uint16_t DeviceAddr)1141 void mfxstm32l152_TS_ClearIT(uint16_t DeviceAddr)
1142 {
1143 /* Clear the global TS IT source */
1144 mfxstm32l152_ClearGlobalIT(DeviceAddr, MFXSTM32L152_IRQ_TS);
1145 }
1146
1147 /* ------------------------------------------------------------------ */
1148 /* --------------------- IDD MEASUREMENT ---------------------------- */
1149 /* ------------------------------------------------------------------ */
1150
1151 /**
1152 * @brief Launch IDD current measurement
1153 * @param DeviceAddr: Device address on communication Bus
1154 * @retval None.
1155 */
mfxstm32l152_IDD_Start(uint16_t DeviceAddr)1156 void mfxstm32l152_IDD_Start(uint16_t DeviceAddr)
1157 {
1158 uint8_t mode = 0;
1159
1160 /* Get the current register value */
1161 mode = MFX_IO_Read((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_CTRL);
1162
1163 /* Set the Functionalities to be enabled */
1164 mode |= MFXSTM32L152_IDD_CTRL_REQ;
1165
1166 /* Start measurement campaign */
1167 MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_CTRL, mode);
1168 }
1169
1170 /**
1171 * @brief Configures the IDD current measurement
1172 * @param DeviceAddr: Device address on communication Bus.
1173 * @param MfxIddConfig: Parameters depending on hardware config.
1174 * @retval None
1175 */
mfxstm32l152_IDD_Config(uint16_t DeviceAddr,IDD_ConfigTypeDef MfxIddConfig)1176 void mfxstm32l152_IDD_Config(uint16_t DeviceAddr, IDD_ConfigTypeDef MfxIddConfig)
1177 {
1178 uint8_t value = 0;
1179 uint8_t mode = 0;
1180
1181 /* Get the current register value */
1182 mode = MFX_IO_Read((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_SYS_CTRL);
1183
1184 if((mode & MFXSTM32L152_IDD_EN) != MFXSTM32L152_IDD_EN)
1185 {
1186 /* Set the Functionalities to be enabled */
1187 mode |= MFXSTM32L152_IDD_EN;
1188
1189 /* Set the new register value */
1190 MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_SYS_CTRL, mode);
1191 }
1192
1193 /* Control register setting: number of shunts */
1194 value = ((MfxIddConfig.ShuntNbUsed << 1) & MFXSTM32L152_IDD_CTRL_SHUNT_NB);
1195 value |= (MfxIddConfig.VrefMeasurement & MFXSTM32L152_IDD_CTRL_VREF_DIS);
1196 value |= (MfxIddConfig.Calibration & MFXSTM32L152_IDD_CTRL_CAL_DIS);
1197 MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_CTRL, value);
1198
1199 /* Idd pre delay configuration: unit and value*/
1200 value = (MfxIddConfig.PreDelayUnit & MFXSTM32L152_IDD_PREDELAY_UNIT) |
1201 (MfxIddConfig.PreDelayValue & MFXSTM32L152_IDD_PREDELAY_VALUE);
1202 MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_PRE_DELAY, value);
1203
1204 /* Shunt 0 register value: MSB then LSB */
1205 value = (uint8_t) (MfxIddConfig.Shunt0Value >> 8);
1206 MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SHUNT0_MSB, value);
1207 value = (uint8_t) (MfxIddConfig.Shunt0Value);
1208 MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SHUNT0_LSB, value);
1209
1210 /* Shunt 1 register value: MSB then LSB */
1211 value = (uint8_t) (MfxIddConfig.Shunt1Value >> 8);
1212 MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SHUNT1_MSB, value);
1213 value = (uint8_t) (MfxIddConfig.Shunt1Value);
1214 MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SHUNT1_LSB, value);
1215
1216 /* Shunt 2 register value: MSB then LSB */
1217 value = (uint8_t) (MfxIddConfig.Shunt2Value >> 8);
1218 MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SHUNT2_MSB, value);
1219 value = (uint8_t) (MfxIddConfig.Shunt2Value);
1220 MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SHUNT2_LSB, value);
1221
1222 /* Shunt 3 register value: MSB then LSB */
1223 value = (uint8_t) (MfxIddConfig.Shunt3Value >> 8);
1224 MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SHUNT3_MSB, value);
1225 value = (uint8_t) (MfxIddConfig.Shunt3Value);
1226 MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SHUNT3_LSB, value);
1227
1228 /* Shunt 4 register value: MSB then LSB */
1229 value = (uint8_t) (MfxIddConfig.Shunt4Value >> 8);
1230 MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SHUNT4_MSB, value);
1231 value = (uint8_t) (MfxIddConfig.Shunt4Value);
1232 MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SHUNT4_LSB, value);
1233
1234 /* Shunt 0 stabilization delay */
1235 value = MfxIddConfig.Shunt0StabDelay;
1236 MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SH0_STABILIZATION, value);
1237
1238 /* Shunt 1 stabilization delay */
1239 value = MfxIddConfig.Shunt1StabDelay;
1240 MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SH1_STABILIZATION, value);
1241
1242 /* Shunt 2 stabilization delay */
1243 value = MfxIddConfig.Shunt2StabDelay;
1244 MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SH2_STABILIZATION, value);
1245
1246 /* Shunt 3 stabilization delay */
1247 value = MfxIddConfig.Shunt3StabDelay;
1248 MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SH3_STABILIZATION, value);
1249
1250 /* Shunt 4 stabilization delay */
1251 value = MfxIddConfig.Shunt4StabDelay;
1252 MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SH4_STABILIZATION, value);
1253
1254 /* Idd ampli gain value: MSB then LSB */
1255 value = (uint8_t) (MfxIddConfig.AmpliGain >> 8);
1256 MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_GAIN_MSB, value);
1257 value = (uint8_t) (MfxIddConfig.AmpliGain);
1258 MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_GAIN_LSB, value);
1259
1260 /* Idd VDD min value: MSB then LSB */
1261 value = (uint8_t) (MfxIddConfig.VddMin >> 8);
1262 MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_VDD_MIN_MSB, value);
1263 value = (uint8_t) (MfxIddConfig.VddMin);
1264 MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_VDD_MIN_LSB, value);
1265
1266 /* Idd number of measurements */
1267 value = MfxIddConfig.MeasureNb;
1268 MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_NBR_OF_MEAS, value);
1269
1270 /* Idd delta delay configuration: unit and value */
1271 value = (MfxIddConfig.DeltaDelayUnit & MFXSTM32L152_IDD_DELTADELAY_UNIT) |
1272 (MfxIddConfig.DeltaDelayValue & MFXSTM32L152_IDD_DELTADELAY_VALUE);
1273 MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_MEAS_DELTA_DELAY, value);
1274
1275 /* Idd number of shut on board */
1276 value = MfxIddConfig.ShuntNbOnBoard;
1277 MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SHUNTS_ON_BOARD, value);
1278 }
1279
1280 /**
1281 * @brief This function allows to modify number of shunt used for a measurement
1282 * @param DeviceAddr: Device address on communication Bus
1283 * @retval None.
1284 */
mfxstm32l152_IDD_ConfigShuntNbLimit(uint16_t DeviceAddr,uint8_t ShuntNbLimit)1285 void mfxstm32l152_IDD_ConfigShuntNbLimit(uint16_t DeviceAddr, uint8_t ShuntNbLimit)
1286 {
1287 uint8_t mode = 0;
1288
1289 /* Get the current register value */
1290 mode = MFX_IO_Read((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_CTRL);
1291
1292 /* Clear number of shunt limit */
1293 mode &= ~(MFXSTM32L152_IDD_CTRL_SHUNT_NB);
1294
1295 /* Clear number of shunt limit */
1296 mode |= ((ShuntNbLimit << 1) & MFXSTM32L152_IDD_CTRL_SHUNT_NB);
1297
1298 /* Write noewx desired limit */
1299 MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_CTRL, mode);
1300 }
1301
1302 /**
1303 * @brief Get Idd current value
1304 * @param DeviceAddr: Device address on communication Bus
1305 * @param ReadValue: Pointer on value to be read
1306 * @retval Idd value in 10 nA.
1307 */
mfxstm32l152_IDD_GetValue(uint16_t DeviceAddr,uint32_t * ReadValue)1308 void mfxstm32l152_IDD_GetValue(uint16_t DeviceAddr, uint32_t *ReadValue)
1309 {
1310 uint8_t data[3];
1311
1312 MFX_IO_ReadMultiple((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_VALUE_MSB, data, sizeof(data)) ;
1313
1314 /* Recompose Idd current value */
1315 *ReadValue = (data[0] << 16) | (data[1] << 8) | data[2];
1316
1317 }
1318
1319 /**
1320 * @brief Get Last shunt used for measurement
1321 * @param DeviceAddr: Device address on communication Bus
1322 * @retval Last shunt used
1323 */
mfxstm32l152_IDD_GetShuntUsed(uint16_t DeviceAddr)1324 uint8_t mfxstm32l152_IDD_GetShuntUsed(uint16_t DeviceAddr)
1325 {
1326 return(MFX_IO_Read((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SHUNT_USED));
1327 }
1328
1329 /**
1330 * @brief Configure mfx to enable Idd interrupt
1331 * @param DeviceAddr: Device address on communication Bus.
1332 * @retval None
1333 */
mfxstm32l152_IDD_EnableIT(uint16_t DeviceAddr)1334 void mfxstm32l152_IDD_EnableIT(uint16_t DeviceAddr)
1335 {
1336 MFX_IO_ITConfig();
1337
1338 /* Enable global IDD interrupt source */
1339 mfxstm32l152_EnableITSource(DeviceAddr, MFXSTM32L152_IRQ_IDD);
1340 }
1341
1342 /**
1343 * @brief Clear Idd global interrupt
1344 * @param DeviceAddr: Device address on communication Bus.
1345 * @retval None
1346 */
mfxstm32l152_IDD_ClearIT(uint16_t DeviceAddr)1347 void mfxstm32l152_IDD_ClearIT(uint16_t DeviceAddr)
1348 {
1349 /* Clear the global IDD interrupt source */
1350 mfxstm32l152_ClearGlobalIT(DeviceAddr, MFXSTM32L152_IRQ_IDD);
1351 }
1352
1353 /**
1354 * @brief get Idd interrupt status
1355 * @param DeviceAddr: Device address on communication Bus.
1356 * @retval IDD interrupts status
1357 */
mfxstm32l152_IDD_GetITStatus(uint16_t DeviceAddr)1358 uint8_t mfxstm32l152_IDD_GetITStatus(uint16_t DeviceAddr)
1359 {
1360 /* Return IDD interrupt status */
1361 return(mfxstm32l152_GlobalITStatus(DeviceAddr, MFXSTM32L152_IRQ_IDD));
1362 }
1363
1364 /**
1365 * @brief disable Idd interrupt
1366 * @param DeviceAddr: Device address on communication Bus.
1367 * @retval None.
1368 */
mfxstm32l152_IDD_DisableIT(uint16_t DeviceAddr)1369 void mfxstm32l152_IDD_DisableIT(uint16_t DeviceAddr)
1370 {
1371 /* Disable global IDD interrupt source */
1372 mfxstm32l152_DisableITSource(DeviceAddr, MFXSTM32L152_IRQ_IDD);
1373 }
1374
1375
1376 /* ------------------------------------------------------------------ */
1377 /* --------------------- ERROR MANAGEMENT --------------------------- */
1378 /* ------------------------------------------------------------------ */
1379
1380 /**
1381 * @brief Read Error Source.
1382 * @param DeviceAddr: Device address on communication Bus.
1383 * @retval Error message code with error source
1384 */
mfxstm32l152_Error_ReadSrc(uint16_t DeviceAddr)1385 uint8_t mfxstm32l152_Error_ReadSrc(uint16_t DeviceAddr)
1386 {
1387 /* Get the current source register value */
1388 return(MFX_IO_Read((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_ERROR_SRC));
1389 }
1390
1391 /**
1392 * @brief Read Error Message
1393 * @param DeviceAddr: Device address on communication Bus.
1394 * @retval Error message code with error source
1395 */
mfxstm32l152_Error_ReadMsg(uint16_t DeviceAddr)1396 uint8_t mfxstm32l152_Error_ReadMsg(uint16_t DeviceAddr)
1397 {
1398 /* Get the current message register value */
1399 return(MFX_IO_Read((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_ERROR_MSG));
1400 }
1401
1402 /**
1403 * @brief Enable Error global interrupt
1404 * @param DeviceAddr: Device address on communication Bus.
1405 * @retval None
1406 */
1407
mfxstm32l152_Error_EnableIT(uint16_t DeviceAddr)1408 void mfxstm32l152_Error_EnableIT(uint16_t DeviceAddr)
1409 {
1410 MFX_IO_ITConfig();
1411
1412 /* Enable global Error interrupt source */
1413 mfxstm32l152_EnableITSource(DeviceAddr, MFXSTM32L152_IRQ_ERROR);
1414 }
1415
1416 /**
1417 * @brief Clear Error global interrupt
1418 * @param DeviceAddr: Device address on communication Bus.
1419 * @retval None
1420 */
mfxstm32l152_Error_ClearIT(uint16_t DeviceAddr)1421 void mfxstm32l152_Error_ClearIT(uint16_t DeviceAddr)
1422 {
1423 /* Clear the global Error interrupt source */
1424 mfxstm32l152_ClearGlobalIT(DeviceAddr, MFXSTM32L152_IRQ_ERROR);
1425 }
1426
1427 /**
1428 * @brief get Error interrupt status
1429 * @param DeviceAddr: Device address on communication Bus.
1430 * @retval Error interrupts status
1431 */
mfxstm32l152_Error_GetITStatus(uint16_t DeviceAddr)1432 uint8_t mfxstm32l152_Error_GetITStatus(uint16_t DeviceAddr)
1433 {
1434 /* Return Error interrupt status */
1435 return(mfxstm32l152_GlobalITStatus(DeviceAddr, MFXSTM32L152_IRQ_ERROR));
1436 }
1437
1438 /**
1439 * @brief disable Error interrupt
1440 * @param DeviceAddr: Device address on communication Bus.
1441 * @retval None.
1442 */
mfxstm32l152_Error_DisableIT(uint16_t DeviceAddr)1443 void mfxstm32l152_Error_DisableIT(uint16_t DeviceAddr)
1444 {
1445 /* Disable global Error interrupt source */
1446 mfxstm32l152_DisableITSource(DeviceAddr, MFXSTM32L152_IRQ_ERROR);
1447 }
1448
1449 /**
1450 * @brief FOR DEBUG ONLY
1451 */
mfxstm32l152_ReadReg(uint16_t DeviceAddr,uint8_t RegAddr)1452 uint8_t mfxstm32l152_ReadReg(uint16_t DeviceAddr, uint8_t RegAddr)
1453 {
1454 /* Get the current register value */
1455 return(MFX_IO_Read((uint8_t) DeviceAddr, RegAddr));
1456 }
1457
mfxstm32l152_WriteReg(uint16_t DeviceAddr,uint8_t RegAddr,uint8_t Value)1458 void mfxstm32l152_WriteReg(uint16_t DeviceAddr, uint8_t RegAddr, uint8_t Value)
1459 {
1460 /* set the current register value */
1461 MFX_IO_Write((uint8_t) DeviceAddr, RegAddr, Value);
1462 }
1463
1464 /* ------------------------------------------------------------------ */
1465 /* ----------------------- Private functions ------------------------ */
1466 /* ------------------------------------------------------------------ */
1467 /**
1468 * @brief Check if the device instance of the selected address is already registered
1469 * and return its index
1470 * @param DeviceAddr: Device address on communication Bus.
1471 * @retval Index of the device instance if registered, 0xFF if not.
1472 */
mfxstm32l152_GetInstance(uint16_t DeviceAddr)1473 static uint8_t mfxstm32l152_GetInstance(uint16_t DeviceAddr)
1474 {
1475 uint8_t idx = 0;
1476
1477 /* Check all the registered instances */
1478 for(idx = 0; idx < MFXSTM32L152_MAX_INSTANCE ; idx ++)
1479 {
1480 if(mfxstm32l152[idx] == DeviceAddr)
1481 {
1482 return idx;
1483 }
1484 }
1485
1486 return 0xFF;
1487 }
1488
1489 /**
1490 * @brief Release registered device instance
1491 * @param DeviceAddr: Device address on communication Bus.
1492 * @retval Index of released device instance, 0xFF if not.
1493 */
mfxstm32l152_ReleaseInstance(uint16_t DeviceAddr)1494 static uint8_t mfxstm32l152_ReleaseInstance(uint16_t DeviceAddr)
1495 {
1496 uint8_t idx = 0;
1497
1498 /* Check for all the registered instances */
1499 for(idx = 0; idx < MFXSTM32L152_MAX_INSTANCE ; idx ++)
1500 {
1501 if(mfxstm32l152[idx] == DeviceAddr)
1502 {
1503 mfxstm32l152[idx] = 0;
1504 return idx;
1505 }
1506 }
1507 return 0xFF;
1508 }
1509
1510 /**
1511 * @brief Internal routine
1512 * @param DeviceAddr: Device address on communication Bus.
1513 * @param RegisterAddr: Register Address
1514 * @param PinPosition: Pin [0:23]
1515 * @param PinValue: 0/1
1516 * @retval None
1517 */
mfxstm32l152_reg24_setPinValue(uint16_t DeviceAddr,uint8_t RegisterAddr,uint32_t PinPosition,uint8_t PinValue)1518 void mfxstm32l152_reg24_setPinValue(uint16_t DeviceAddr, uint8_t RegisterAddr, uint32_t PinPosition, uint8_t PinValue )
1519 {
1520 uint8_t tmp = 0;
1521 uint8_t pin_0_7, pin_8_15, pin_16_23;
1522
1523 pin_0_7 = PinPosition & 0x0000ff;
1524 pin_8_15 = PinPosition >> 8;
1525 pin_8_15 = pin_8_15 & 0x00ff;
1526 pin_16_23 = PinPosition >> 16;
1527
1528 if (pin_0_7)
1529 {
1530 /* Get the current register value */
1531 tmp = MFX_IO_Read(DeviceAddr, RegisterAddr);
1532
1533 /* Set the selected pin direction */
1534 if (PinValue != 0)
1535 {
1536 tmp |= (uint8_t)pin_0_7;
1537 }
1538 else
1539 {
1540 tmp &= ~(uint8_t)pin_0_7;
1541 }
1542
1543 /* Set the new register value */
1544 MFX_IO_Write(DeviceAddr, RegisterAddr, tmp);
1545 }
1546
1547 if (pin_8_15)
1548 {
1549 /* Get the current register value */
1550 tmp = MFX_IO_Read(DeviceAddr, RegisterAddr+1);
1551
1552 /* Set the selected pin direction */
1553 if (PinValue != 0)
1554 {
1555 tmp |= (uint8_t)pin_8_15;
1556 }
1557 else
1558 {
1559 tmp &= ~(uint8_t)pin_8_15;
1560 }
1561
1562 /* Set the new register value */
1563 MFX_IO_Write(DeviceAddr, RegisterAddr+1, tmp);
1564 }
1565
1566 if (pin_16_23)
1567 {
1568 /* Get the current register value */
1569 tmp = MFX_IO_Read(DeviceAddr, RegisterAddr+2);
1570
1571 /* Set the selected pin direction */
1572 if (PinValue != 0)
1573 {
1574 tmp |= (uint8_t)pin_16_23;
1575 }
1576 else
1577 {
1578 tmp &= ~(uint8_t)pin_16_23;
1579 }
1580
1581 /* Set the new register value */
1582 MFX_IO_Write(DeviceAddr, RegisterAddr+2, tmp);
1583 }
1584 }
1585
1586
1587 /**
1588 * @}
1589 */
1590
1591 /**
1592 * @}
1593 */
1594
1595 /**
1596 * @}
1597 */
1598
1599 /**
1600 * @}
1601 */
1602 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1603