1 /* 2 * Copyright (c) 2006-2023, RT-Thread Development Team 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 * 2023-07-08 Zheng-Bicheng first version 9 */ 10 11 #include "board.h" 12 SystemClock_Config(void)13void SystemClock_Config(void) 14 { 15 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 16 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 17 18 /** Configure the main internal regulator output voltage 19 */ 20 if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK) 21 { 22 Error_Handler(); 23 } 24 25 /** Initializes the CPU, AHB and APB buses clocks 26 */ 27 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI; 28 RCC_OscInitStruct.MSIState = RCC_MSI_ON; 29 RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT; 30 RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_4; 31 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 32 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI; 33 RCC_OscInitStruct.PLL.PLLMBOOST = RCC_PLLMBOOST_DIV1; 34 RCC_OscInitStruct.PLL.PLLM = 1; 35 RCC_OscInitStruct.PLL.PLLN = 80; 36 RCC_OscInitStruct.PLL.PLLP = 2; 37 RCC_OscInitStruct.PLL.PLLQ = 2; 38 RCC_OscInitStruct.PLL.PLLR = 2; 39 RCC_OscInitStruct.PLL.PLLRGE = RCC_PLLVCIRANGE_0; 40 RCC_OscInitStruct.PLL.PLLFRACN = 0; 41 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 42 { 43 Error_Handler(); 44 } 45 46 /** Initializes the CPU, AHB and APB buses clocks 47 */ 48 RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 49 |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2 50 |RCC_CLOCKTYPE_PCLK3; 51 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; 52 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 53 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; 54 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; 55 RCC_ClkInitStruct.APB3CLKDivider = RCC_HCLK_DIV1; 56 57 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) 58 { 59 Error_Handler(); 60 } 61 } 62