1 /*
2 * Copyright (c) 2006-2022, Synwit Technology Co.,Ltd.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Change Logs:
7 * Date Author Notes
8 * 2020-5-26 lik first version
9 */
10
11 #include "drv_adc.h"
12
13 #ifdef RT_USING_ADC
14 #ifdef BSP_USING_ADC
15
16 //#define DRV_DEBUG
17 #define LOG_TAG "drv.adc"
18 #include <drv_log.h>
19
20 #if !defined(BSP_USING_ADC0) && !defined(BSP_USING_ADC1)
21 #error "Please define at least one BSP_USING_ADCx"
22 /* this driver can be disabled at menuconfig ? RT-Thread Components ? Device Drivers */
23 #endif
24
25 #ifdef BSP_USING_ADC0
26 #ifndef ADC0_CFG
27 #define ADC0_CFG \
28 { \
29 .name = "adc0", \
30 .ADCx = ADC0, \
31 .adc_initstruct.clk_src = ADC_CLKSRC_VCO_DIV64, \
32 .adc_initstruct.clk_div = 25, \
33 .adc_initstruct.pga_ref = PGA_REF_INTERNAL, \
34 .adc_initstruct.channels = 0, \
35 .adc_initstruct.samplAvg = ADC_AVG_SAMPLE1, \
36 .adc_initstruct.trig_src = ADC_TRIGSRC_SW, \
37 .adc_initstruct.Continue = 0, \
38 .adc_initstruct.EOC_IEn = 0, \
39 .adc_initstruct.OVF_IEn = 0, \
40 .adc_initstruct.HFULL_IEn = 0, \
41 .adc_initstruct.FULL_IEn = 0, \
42 }
43 #endif /* ADC0_CFG */
44 #endif /* BSP_USING_ADC0 */
45
46 #ifdef BSP_USING_ADC1
47 #ifndef ADC1_CFG
48 #define ADC1_CFG \
49 { \
50 .name = "adc1", \
51 .ADCx = ADC1, \
52 .adc_initstruct.clk_src = ADC_CLKSRC_VCO_DIV64, \
53 .adc_initstruct.clk_div = 25, \
54 .adc_initstruct.pga_ref = PGA_REF_INTERNAL, \
55 .adc_initstruct.channels = 0, \
56 .adc_initstruct.samplAvg = ADC_AVG_SAMPLE1, \
57 .adc_initstruct.trig_src = ADC_TRIGSRC_SW, \
58 .adc_initstruct.Continue = 0, \
59 .adc_initstruct.EOC_IEn = 0, \
60 .adc_initstruct.OVF_IEn = 0, \
61 .adc_initstruct.HFULL_IEn = 0, \
62 .adc_initstruct.FULL_IEn = 0, \
63 }
64 #endif /* ADC1_CFG */
65 #endif /* BSP_USING_ADC1 */
66
67 struct swm_adc_cfg
68 {
69 const char *name;
70 ADC_TypeDef *ADCx;
71 ADC_InitStructure adc_initstruct;
72 };
73
74 struct swm_adc_device
75 {
76 struct swm_adc_cfg *adc_cfg;
77 struct rt_adc_device adc_device;
78 };
79
80 static struct swm_adc_cfg swm_adc_cfg[] =
81 {
82 #ifdef BSP_USING_ADC0
83 ADC0_CFG,
84 #endif
85 #ifdef BSP_USING_ADC1
86 ADC1_CFG,
87 #endif
88
89 };
90
91 static struct swm_adc_device adc_obj[sizeof(swm_adc_cfg) / sizeof(swm_adc_cfg[0])];
92
swm_adc_get_channel(rt_uint32_t channel)93 static rt_uint32_t swm_adc_get_channel(rt_uint32_t channel)
94 {
95 rt_uint32_t swm_channel = 0;
96
97 switch (channel)
98 {
99 case 0:
100 swm_channel = ADC_CH0;
101 break;
102 case 1:
103 swm_channel = ADC_CH1;
104 break;
105 case 2:
106 swm_channel = ADC_CH2;
107 break;
108 case 3:
109 swm_channel = ADC_CH3;
110 break;
111 case 4:
112 swm_channel = ADC_CH4;
113 break;
114 case 5:
115 swm_channel = ADC_CH5;
116 break;
117 case 6:
118 swm_channel = ADC_CH6;
119 break;
120 case 7:
121 swm_channel = ADC_CH7;
122 break;
123 }
124
125 return swm_channel;
126 }
127
swm_adc_enabled(struct rt_adc_device * adc_device,rt_uint32_t channel,rt_bool_t enabled)128 static rt_err_t swm_adc_enabled(struct rt_adc_device *adc_device, rt_uint32_t channel, rt_bool_t enabled)
129 {
130 uint32_t adc_chn;
131 struct swm_adc_cfg *adc_cfg;
132 RT_ASSERT(adc_device != RT_NULL);
133 adc_cfg = adc_device->parent.user_data;
134
135 if (channel < 8)
136 {
137 /* set swm ADC channel */
138 adc_chn = swm_adc_get_channel(channel);
139 }
140 else
141 {
142 LOG_E("ADC channel must be between 0 and 7.");
143 return -RT_ERROR;
144 }
145
146 if (enabled)
147 {
148 adc_cfg->ADCx->CTRL |= (adc_chn << ADC_CTRL_CH0_Pos);
149 }
150 else
151 {
152 adc_cfg->ADCx->CTRL &= ~(adc_chn << ADC_CTRL_CH0_Pos);
153 }
154
155 return RT_EOK;
156 }
157
swm_adc_convert(struct rt_adc_device * adc_device,rt_uint32_t channel,rt_uint32_t * value)158 static rt_err_t swm_adc_convert(struct rt_adc_device *adc_device, rt_uint32_t channel, rt_uint32_t *value)
159 {
160 uint32_t adc_chn;
161 struct swm_adc_cfg *adc_cfg;
162 RT_ASSERT(adc_device != RT_NULL);
163 RT_ASSERT(value != RT_NULL);
164 adc_cfg = adc_device->parent.user_data;
165
166 if (channel < 8)
167 {
168 /* set swm ADC channel */
169 adc_chn = swm_adc_get_channel(channel);
170 }
171 else
172 {
173 LOG_E("ADC channel must be between 0 and 7.");
174 return -RT_ERROR;
175 }
176
177 /* start ADC */
178 ADC_Start(adc_cfg->ADCx);
179 /* Wait for the ADC to convert */
180 while ((adc_cfg->ADCx->CH[channel].STAT & 0x01) == 0)
181 ;
182
183 /* get ADC value */
184 *value = (rt_uint32_t)ADC_Read(adc_cfg->ADCx, adc_chn);
185
186 return RT_EOK;
187 }
188
189 static const struct rt_adc_ops swm_adc_ops =
190 {
191 .enabled = swm_adc_enabled,
192 .convert = swm_adc_convert,
193 };
194
swm_adc_init(void)195 static int swm_adc_init(void)
196 {
197 int i = 0;
198 int result = RT_EOK;
199
200 for (i = 0; i < sizeof(swm_adc_cfg) / sizeof(swm_adc_cfg[0]); i++)
201 {
202 /* ADC init */
203 adc_obj[i].adc_cfg = &swm_adc_cfg[i];
204
205 if (adc_obj[i].adc_cfg->ADCx == ADC0)
206 {
207 #ifdef BSP_USING_ADC0_CHN0
208 adc_obj[i].adc_cfg->adc_initstruct.channels |= ADC_CH0;
209 #endif
210 #ifdef BSP_USING_ADC0_CHN1
211 adc_obj[i].adc_cfg->adc_initstruct.channels |= ADC_CH1;
212 #endif
213 #ifdef BSP_USING_ADC0_CHN2
214 adc_obj[i].adc_cfg->adc_initstruct.channels |= ADC_CH2;
215 #endif
216 #ifdef BSP_USING_ADC0_CHN3
217 adc_obj[i].adc_cfg->adc_initstruct.channels |= ADC_CH3;
218 #endif
219 #ifdef BSP_USING_ADC0_CHN4
220 adc_obj[i].adc_cfg->adc_initstruct.channels |= ADC_CH4;
221 PORT_Init(PORTA, PIN12, PORTA_PIN12_ADC0_IN4, 0); //PA.12 => ADC0.CH4
222 #endif
223 #ifdef BSP_USING_ADC0_CHN5
224 adc_obj[i].adc_cfg->adc_initstruct.channels |= ADC_CH5;
225 PORT_Init(PORTA, PIN11, PORTA_PIN11_ADC0_IN5, 0); //PA.11 => ADC0.CH5
226 #endif
227 #ifdef BSP_USING_ADC0_CHN6
228 adc_obj[i].adc_cfg->adc_initstruct.channels |= ADC_CH6;
229 PORT_Init(PORTA, PIN10, PORTA_PIN10_ADC0_IN6, 0); //PA.10 => ADC0.CH6
230 #endif
231 #ifdef BSP_USING_ADC0_CHN7
232 adc_obj[i].adc_cfg->adc_initstruct.channels |= ADC_CH7;
233 PORT_Init(PORTA, PIN9, PORTA_PIN9_ADC0_IN7, 0); //PA.9 => ADC0.CH7
234 #endif
235 }
236 else if (adc_obj[i].adc_cfg->ADCx == ADC1)
237 {
238 #ifdef BSP_USING_ADC1_CHN0
239 adc_obj[i].adc_cfg->adc_initstruct.channels |= ADC_CH0;
240 PORT_Init(PORTC, PIN7, PORTC_PIN7_ADC1_IN0, 0); //PC.7 => ADC1.CH0
241 #endif
242 #ifdef BSP_USING_ADC1_CHN1
243 adc_obj[i].adc_cfg->adc_initstruct.channels |= ADC_CH1;
244 PORT_Init(PORTC, PIN6, PORTC_PIN6_ADC1_IN1, 0); //PC.6 => ADC1.CH1
245 #endif
246 #ifdef BSP_USING_ADC1_CHN2
247 adc_obj[i].adc_cfg->adc_initstruct.channels |= ADC_CH2;
248 PORT_Init(PORTC, PIN5, PORTC_PIN5_ADC1_IN2, 0); //PC.5 => ADC1.CH2
249 #endif
250 #ifdef BSP_USING_ADC1_CHN3
251 adc_obj[i].adc_cfg->adc_initstruct.channels |= ADC_CH3;
252 PORT_Init(PORTC, PIN4, PORTC_PIN4_ADC1_IN3, 0); //PC.4 => ADC1.CH3
253 #endif
254 #ifdef BSP_USING_ADC1_CHN4
255 adc_obj[i].adc_cfg->adc_initstruct.channels |= ADC_CH4;
256 PORT_Init(PORTN, PIN0, PORTN_PIN0_ADC1_IN4, 0); //PN.0 => ADC1.CH4
257 #endif
258 #ifdef BSP_USING_ADC1_CHN5
259 adc_obj[i].adc_cfg->adc_initstruct.channels |= ADC_CH5;
260 PORT_Init(PORTN, PIN1, PORTN_PIN1_ADC1_IN5, 0); //PN.1 => ADC1.CH5
261 #endif
262 #ifdef BSP_USING_ADC1_CHN6
263 adc_obj[i].adc_cfg->adc_initstruct.channels |= ADC_CH6;
264 PORT_Init(PORTN, PIN2, PORTN_PIN2_ADC1_IN6, 0); //PN.2 => ADC1.CH6
265 #endif
266 #ifdef BSP_USING_ADC1_CHN7
267 adc_obj[i].adc_cfg->adc_initstruct.channels |= ADC_CH7;
268 #endif
269 }
270
271 ADC_Init(adc_obj[i].adc_cfg->ADCx, &(adc_obj[i].adc_cfg->adc_initstruct));
272 ADC_Open(adc_obj[i].adc_cfg->ADCx);
273 /* register ADC device */
274 result = rt_hw_adc_register(&adc_obj[i].adc_device, adc_obj[i].adc_cfg->name, &swm_adc_ops, adc_obj[i].adc_cfg);
275 if(result != RT_EOK)
276 {
277 LOG_E("%s register fail.", adc_obj[i].adc_cfg->name);
278 }
279 else
280 {
281 LOG_D("%s register success.", adc_obj[i].adc_cfg->name);
282 }
283 }
284
285 return result;
286 }
287 INIT_BOARD_EXPORT(swm_adc_init);
288 #endif /* BSP_USING_ADC */
289 #endif /* RT_USING_ADC */
290