1 /*
2  * Copyright (c) 2006-2022, Synwit Technology Co.,Ltd.
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  *
6  * Change Logs:
7  * Date           Author       Notes
8  * 2018-05-31     ZYH          first version
9  * 2018-12-10     Zohar_Lee    fix bug
10  * 2020-07-10     lik          rewrite
11  */
12 
13 #include "drv_gpio.h"
14 
15 #ifdef RT_USING_PIN
16 #ifdef BSP_USING_GPIO
17 
18 //#define DRV_DEBUG
19 #define LOG_TAG "drv.gpio"
20 #include <drv_log.h>
21 
22 #define __SWM_PIN(index, gpio, pin_index)                    \
23     {                                                        \
24         index, GPIO##gpio, PIN##pin_index, GPIO##gpio##_IRQn \
25     }
26 #define GPIO0 ((GPIO_TypeDef *)(0))
27 #define GPIO0_IRQn (GPIOA0_IRQn)
28 
29 struct swm_pin_device
30 {
31     uint32_t index;
32     GPIO_TypeDef *gpio;
33     uint32_t pin;
34     IRQn_Type irq;
35 };
36 
37 static const struct swm_pin_device pin_obj[] =
38     {
39         __SWM_PIN(0, A, 0),
40         __SWM_PIN(1, A, 1),
41         __SWM_PIN(2, A, 2),
42         __SWM_PIN(3, A, 3),
43         __SWM_PIN(4, A, 4),
44         __SWM_PIN(5, A, 5),
45         __SWM_PIN(6, A, 6),
46         __SWM_PIN(7, A, 7),
47         __SWM_PIN(8, A, 8),
48         __SWM_PIN(9, A, 9),
49         __SWM_PIN(10, A, 10),
50         __SWM_PIN(11, A, 11),
51         __SWM_PIN(12, A, 12),
52 
53         __SWM_PIN(13, B, 0),
54         __SWM_PIN(14, B, 1),
55         __SWM_PIN(15, B, 2),
56         __SWM_PIN(16, B, 3),
57         __SWM_PIN(17, B, 4),
58         __SWM_PIN(18, B, 5),
59         __SWM_PIN(19, B, 6),
60         __SWM_PIN(20, B, 7),
61         __SWM_PIN(21, B, 8),
62         __SWM_PIN(22, B, 9),
63         __SWM_PIN(23, B, 10),
64         __SWM_PIN(24, B, 11),
65         __SWM_PIN(25, B, 12),
66 
67         __SWM_PIN(26, C, 0),
68         __SWM_PIN(27, C, 1),
69         __SWM_PIN(28, C, 2),
70         __SWM_PIN(29, C, 3),
71         __SWM_PIN(30, C, 4),
72         __SWM_PIN(31, C, 5),
73         __SWM_PIN(32, C, 6),
74         __SWM_PIN(33, C, 7),
75 
76         __SWM_PIN(34, M, 0),
77         __SWM_PIN(35, M, 1),
78         __SWM_PIN(36, M, 2),
79         __SWM_PIN(37, M, 3),
80         __SWM_PIN(38, M, 4),
81         __SWM_PIN(39, M, 5),
82         __SWM_PIN(40, M, 6),
83         __SWM_PIN(41, M, 7),
84         __SWM_PIN(42, M, 8),
85         __SWM_PIN(43, M, 9),
86         __SWM_PIN(44, M, 10),
87         __SWM_PIN(45, M, 11),
88         __SWM_PIN(46, M, 12),
89         __SWM_PIN(47, M, 13),
90         __SWM_PIN(48, M, 14),
91         __SWM_PIN(49, M, 15),
92         __SWM_PIN(50, M, 16),
93         __SWM_PIN(51, M, 17),
94         __SWM_PIN(52, M, 18),
95         __SWM_PIN(53, M, 19),
96         __SWM_PIN(54, M, 20),
97         __SWM_PIN(55, M, 21),
98 
99         __SWM_PIN(56, N, 0),
100         __SWM_PIN(57, N, 1),
101         __SWM_PIN(58, N, 2),
102         __SWM_PIN(59, N, 3),
103         __SWM_PIN(60, N, 4),
104         __SWM_PIN(61, N, 5),
105         __SWM_PIN(62, N, 6),
106         __SWM_PIN(63, N, 7),
107         __SWM_PIN(64, N, 8),
108         __SWM_PIN(65, N, 9),
109         __SWM_PIN(66, N, 10),
110         __SWM_PIN(67, N, 11),
111         __SWM_PIN(68, N, 12),
112         __SWM_PIN(69, N, 13),
113         __SWM_PIN(70, N, 14),
114         __SWM_PIN(71, N, 15),
115         __SWM_PIN(72, N, 16),
116         __SWM_PIN(73, N, 17),
117         __SWM_PIN(74, N, 18),
118         __SWM_PIN(75, N, 19),
119 
120         __SWM_PIN(76, P, 0),
121         __SWM_PIN(77, P, 1),
122         __SWM_PIN(78, P, 2),
123         __SWM_PIN(79, P, 3),
124         __SWM_PIN(80, P, 4),
125         __SWM_PIN(81, P, 5),
126         __SWM_PIN(82, P, 6),
127         __SWM_PIN(83, P, 7),
128         __SWM_PIN(84, P, 8),
129         __SWM_PIN(85, P, 9),
130         __SWM_PIN(86, P, 10),
131         __SWM_PIN(87, P, 11),
132         __SWM_PIN(88, P, 12),
133         __SWM_PIN(89, P, 13),
134         __SWM_PIN(90, P, 14),
135         __SWM_PIN(91, P, 15),
136         __SWM_PIN(92, P, 16),
137         __SWM_PIN(93, P, 17),
138         __SWM_PIN(94, P, 18),
139         __SWM_PIN(95, P, 19),
140         __SWM_PIN(96, P, 20),
141         __SWM_PIN(97, P, 21),
142         __SWM_PIN(98, P, 22),
143         __SWM_PIN(99, P, 23)};
144 
145 static struct rt_pin_irq_hdr pin_irq_hdr_tab[] =
146     {
147         {0, 0, RT_NULL, RT_NULL},
148         {1, 0, RT_NULL, RT_NULL},
149         {2, 0, RT_NULL, RT_NULL},
150         {3, 0, RT_NULL, RT_NULL},
151         {4, 0, RT_NULL, RT_NULL},
152         {5, 0, RT_NULL, RT_NULL},
153         {6, 0, RT_NULL, RT_NULL},
154         {7, 0, RT_NULL, RT_NULL},
155         {8, 0, RT_NULL, RT_NULL},
156         {9, 0, RT_NULL, RT_NULL},
157         {10, 0, RT_NULL, RT_NULL},
158         {11, 0, RT_NULL, RT_NULL},
159         {12, 0, RT_NULL, RT_NULL},
160         {13, 0, RT_NULL, RT_NULL},
161         {14, 0, RT_NULL, RT_NULL},
162         {15, 0, RT_NULL, RT_NULL},
163         {16, 0, RT_NULL, RT_NULL},
164         {17, 0, RT_NULL, RT_NULL},
165         {18, 0, RT_NULL, RT_NULL},
166         {19, 0, RT_NULL, RT_NULL},
167         {20, 0, RT_NULL, RT_NULL},
168         {21, 0, RT_NULL, RT_NULL},
169         {22, 0, RT_NULL, RT_NULL},
170         {23, 0, RT_NULL, RT_NULL},
171         {24, 0, RT_NULL, RT_NULL},
172         {25, 0, RT_NULL, RT_NULL},
173         {26, 0, RT_NULL, RT_NULL},
174         {27, 0, RT_NULL, RT_NULL},
175         {28, 0, RT_NULL, RT_NULL},
176         {29, 0, RT_NULL, RT_NULL},
177         {30, 0, RT_NULL, RT_NULL},
178         {31, 0, RT_NULL, RT_NULL},
179         {32, 0, RT_NULL, RT_NULL},
180         {33, 0, RT_NULL, RT_NULL},
181         {34, 0, RT_NULL, RT_NULL},
182         {35, 0, RT_NULL, RT_NULL},
183         {36, 0, RT_NULL, RT_NULL},
184         {37, 0, RT_NULL, RT_NULL},
185         {38, 0, RT_NULL, RT_NULL},
186         {39, 0, RT_NULL, RT_NULL},
187         {40, 0, RT_NULL, RT_NULL},
188         {41, 0, RT_NULL, RT_NULL},
189         {42, 0, RT_NULL, RT_NULL},
190         {43, 0, RT_NULL, RT_NULL},
191         {44, 0, RT_NULL, RT_NULL},
192         {45, 0, RT_NULL, RT_NULL},
193         {46, 0, RT_NULL, RT_NULL},
194         {47, 0, RT_NULL, RT_NULL},
195         {48, 0, RT_NULL, RT_NULL},
196         {49, 0, RT_NULL, RT_NULL},
197         {50, 0, RT_NULL, RT_NULL},
198         {51, 0, RT_NULL, RT_NULL},
199         {52, 0, RT_NULL, RT_NULL},
200         {53, 0, RT_NULL, RT_NULL},
201         {54, 0, RT_NULL, RT_NULL},
202         {55, 0, RT_NULL, RT_NULL},
203         {56, 0, RT_NULL, RT_NULL},
204         {57, 0, RT_NULL, RT_NULL},
205         {58, 0, RT_NULL, RT_NULL},
206         {59, 0, RT_NULL, RT_NULL},
207         {60, 0, RT_NULL, RT_NULL},
208         {61, 0, RT_NULL, RT_NULL},
209         {62, 0, RT_NULL, RT_NULL},
210         {63, 0, RT_NULL, RT_NULL},
211         {64, 0, RT_NULL, RT_NULL},
212         {65, 0, RT_NULL, RT_NULL},
213         {66, 0, RT_NULL, RT_NULL},
214         {67, 0, RT_NULL, RT_NULL},
215         {68, 0, RT_NULL, RT_NULL},
216         {69, 0, RT_NULL, RT_NULL},
217         {70, 0, RT_NULL, RT_NULL},
218         {71, 0, RT_NULL, RT_NULL},
219         {72, 0, RT_NULL, RT_NULL},
220         {73, 0, RT_NULL, RT_NULL},
221         {74, 0, RT_NULL, RT_NULL},
222         {75, 0, RT_NULL, RT_NULL},
223         {76, 0, RT_NULL, RT_NULL},
224         {77, 0, RT_NULL, RT_NULL},
225         {78, 0, RT_NULL, RT_NULL},
226         {79, 0, RT_NULL, RT_NULL},
227         {80, 0, RT_NULL, RT_NULL},
228         {81, 0, RT_NULL, RT_NULL},
229         {82, 0, RT_NULL, RT_NULL},
230         {83, 0, RT_NULL, RT_NULL},
231         {84, 0, RT_NULL, RT_NULL},
232         {85, 0, RT_NULL, RT_NULL},
233         {86, 0, RT_NULL, RT_NULL},
234         {87, 0, RT_NULL, RT_NULL},
235         {88, 0, RT_NULL, RT_NULL},
236         {89, 0, RT_NULL, RT_NULL},
237         {90, 0, RT_NULL, RT_NULL},
238         {91, 0, RT_NULL, RT_NULL},
239         {92, 0, RT_NULL, RT_NULL},
240         {93, 0, RT_NULL, RT_NULL},
241         {94, 0, RT_NULL, RT_NULL},
242         {95, 0, RT_NULL, RT_NULL},
243         {96, 0, RT_NULL, RT_NULL},
244         {97, 0, RT_NULL, RT_NULL},
245         {98, 0, RT_NULL, RT_NULL},
246         {99, 0, RT_NULL, RT_NULL}};
247 
248 #define ITEM_NUM(items) sizeof(items) / sizeof(items[0])
249 
_pin2struct(uint8_t pin)250 static const struct swm_pin_device *_pin2struct(uint8_t pin)
251 {
252     const struct swm_pin_device *gpio_obj;
253 
254     if (pin < ITEM_NUM(pin_obj))
255     {
256         gpio_obj = &pin_obj[pin];
257     }
258     else
259     {
260         gpio_obj = RT_NULL;
261     }
262 
263     return gpio_obj;
264 }
265 
swm_pin_mode(rt_device_t dev,rt_base_t pin,rt_uint8_t mode)266 static void swm_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode)
267 {
268     const struct swm_pin_device *gpio_obj;
269     int dir = 0;
270     int pull_up = 0;
271     int pull_down = 0;
272 
273     gpio_obj = _pin2struct(pin);
274     if (gpio_obj == RT_NULL)
275     {
276         return;
277     }
278     /* Configure GPIO_InitStructure */
279     switch (mode)
280     {
281     case PIN_MODE_OUTPUT:
282         /* output setting */
283         dir = 1;
284         break;
285     case PIN_MODE_INPUT:
286         /* input setting: not pull. */
287         dir = 0;
288         break;
289     case PIN_MODE_INPUT_PULLUP:
290         /* input setting: pull up. */
291         dir = 0;
292         pull_up = 1;
293         break;
294     case PIN_MODE_INPUT_PULLDOWN:
295         /* input setting: pull down. */
296         dir = 0;
297         pull_down = 1;
298         break;
299     case PIN_MODE_OUTPUT_OD:
300         /* output setting: od. */
301         dir = 1;
302         pull_up = 1;
303         break;
304     }
305 
306     GPIO_Init(gpio_obj->gpio, gpio_obj->pin, dir, pull_up, pull_down);
307 }
308 
swm_pin_write(rt_device_t dev,rt_base_t pin,rt_uint8_t value)309 static void swm_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value)
310 {
311     const struct swm_pin_device *gpio_obj;
312 
313     gpio_obj = _pin2struct(pin);
314     if (gpio_obj == RT_NULL)
315     {
316         return;
317     }
318     if (value)
319     {
320         GPIO_AtomicSetBit(gpio_obj->gpio, gpio_obj->pin);
321     }
322     else
323     {
324         GPIO_AtomicClrBit(gpio_obj->gpio, gpio_obj->pin);
325     }
326 }
327 
swm_pin_read(rt_device_t dev,rt_base_t pin)328 static rt_ssize_t swm_pin_read(rt_device_t dev, rt_base_t pin)
329 {
330     const struct swm_pin_device *gpio_obj;
331 
332     gpio_obj = _pin2struct(pin);
333     if (gpio_obj == RT_NULL)
334     {
335         return -RT_EINVAL;
336     }
337     return (rt_ssize_t)GPIO_GetBit(gpio_obj->gpio, gpio_obj->pin);
338 }
339 
swm_pin_attach_irq(struct rt_device * device,rt_base_t pin,rt_uint8_t mode,void (* hdr)(void * args),void * args)340 static rt_err_t swm_pin_attach_irq(struct rt_device *device,
341                                    rt_base_t pin,
342                                    rt_uint8_t mode,
343                                    void (*hdr)(void *args),
344                                    void *args)
345 {
346     rt_base_t level;
347 
348     level = rt_hw_interrupt_disable();
349     if (pin_irq_hdr_tab[pin].pin == pin &&
350         pin_irq_hdr_tab[pin].mode == mode &&
351         pin_irq_hdr_tab[pin].hdr == hdr &&
352         pin_irq_hdr_tab[pin].args == args)
353     {
354         rt_hw_interrupt_enable(level);
355         return RT_EOK;
356     }
357     pin_irq_hdr_tab[pin].pin = pin;
358     pin_irq_hdr_tab[pin].mode = mode;
359     pin_irq_hdr_tab[pin].hdr = hdr;
360     pin_irq_hdr_tab[pin].args = args;
361     rt_hw_interrupt_enable(level);
362     return RT_EOK;
363 }
364 
swm_pin_detach_irq(struct rt_device * device,rt_base_t pin)365 static rt_err_t swm_pin_detach_irq(struct rt_device *device, rt_base_t pin)
366 {
367     rt_base_t level;
368 
369     level = rt_hw_interrupt_disable();
370     pin_irq_hdr_tab[pin].mode = 0;
371     pin_irq_hdr_tab[pin].hdr = RT_NULL;
372     pin_irq_hdr_tab[pin].args = RT_NULL;
373     rt_hw_interrupt_enable(level);
374     return RT_EOK;
375 }
376 
swm_pin_irq_enable(struct rt_device * device,rt_base_t pin,rt_uint8_t enabled)377 static rt_err_t swm_pin_irq_enable(struct rt_device *device,
378                                    rt_base_t pin,
379                                    rt_uint8_t enabled)
380 {
381     const struct swm_pin_device *gpio_obj;
382     rt_base_t level = 0;
383 
384     gpio_obj = _pin2struct(pin);
385     if (gpio_obj == RT_NULL)
386     {
387         return -RT_ENOSYS;
388     }
389 
390     if (enabled == PIN_IRQ_ENABLE)
391     {
392         switch (pin_irq_hdr_tab[pin].mode)
393         {
394         case PIN_IRQ_MODE_RISING:
395             GPIO_Init(gpio_obj->gpio, gpio_obj->pin, 0, 0, 1);
396             EXTI_Init(gpio_obj->gpio, gpio_obj->pin, EXTI_RISE_EDGE);
397             break;
398         case PIN_IRQ_MODE_FALLING:
399             GPIO_Init(gpio_obj->gpio, gpio_obj->pin, 0, 1, 0);
400             EXTI_Init(gpio_obj->gpio, gpio_obj->pin, EXTI_FALL_EDGE);
401             break;
402         case PIN_IRQ_MODE_RISING_FALLING:
403             GPIO_Init(gpio_obj->gpio, gpio_obj->pin, 0, 1, 1);
404             EXTI_Init(gpio_obj->gpio, gpio_obj->pin, EXTI_BOTH_EDGE);
405             break;
406         case PIN_IRQ_MODE_HIGH_LEVEL:
407             GPIO_Init(gpio_obj->gpio, gpio_obj->pin, 0, 0, 1);
408             EXTI_Init(gpio_obj->gpio, gpio_obj->pin, EXTI_HIGH_LEVEL);
409             break;
410         case PIN_IRQ_MODE_LOW_LEVEL:
411             GPIO_Init(gpio_obj->gpio, gpio_obj->pin, 0, 1, 0);
412             EXTI_Init(gpio_obj->gpio, gpio_obj->pin, EXTI_LOW_LEVEL);
413             break;
414         default:
415             return -RT_EINVAL;
416         }
417 
418         level = rt_hw_interrupt_disable();
419         NVIC_EnableIRQ(gpio_obj->irq);
420         EXTI_Open(gpio_obj->gpio, gpio_obj->pin);
421         rt_hw_interrupt_enable(level);
422     }
423     else if (enabled == PIN_IRQ_DISABLE)
424     {
425         level = rt_hw_interrupt_disable();
426         // NVIC_DisableIRQ(gpio_obj->irq);
427         EXTI_Close(gpio_obj->gpio, gpio_obj->pin);
428         rt_hw_interrupt_enable(level);
429     }
430     else
431     {
432         return -RT_ENOSYS;
433     }
434     return RT_EOK;
435 }
436 
swm_pin_get(const char * name)437 static rt_base_t swm_pin_get(const char *name)
438 {
439     rt_base_t pin = 0;
440     int pin_num = 0;
441     int i, name_len;
442 
443     name_len = rt_strlen(name);
444 
445     if ((name_len < 4) || (name_len >= 6))
446     {
447         goto out;
448     }
449     if ((name[0] != 'P') || (name[2] != '.'))
450     {
451         goto out;
452     }
453 
454     switch(name[1])
455     {
456         case 'A':
457             pin = 0;
458         break;
459         case 'B':
460             pin = 13;
461         break;
462         case 'C':
463             pin = 26;
464         break;
465         case 'M':
466             pin = 34;
467         break;
468         case 'N':
469             pin = 56;
470         break;
471         case 'P':
472             pin = 76;
473         break;
474         default:
475             goto out;
476     }
477 
478     for (i = 3; i < name_len; i++)
479     {
480         pin_num *= 10;
481         pin_num += name[i] - '0';
482     }
483     if(pin_num < 24)
484     {
485         pin += pin_num;
486     }
487     else
488     {
489         goto out;
490     }
491 
492     return pin;
493 out:
494     rt_kprintf("PA0~PA12, PB0~PB12, PC0~PC7, PM0~PM21, PN0~PN19, PP0~PP23\n");
495     return -RT_EINVAL;
496 }
497 
498 const static struct rt_pin_ops swm_pin_ops =
499 {
500     .pin_mode = swm_pin_mode,
501     .pin_write = swm_pin_write,
502     .pin_read = swm_pin_read,
503     .pin_attach_irq = swm_pin_attach_irq,
504     .pin_detach_irq = swm_pin_detach_irq,
505     .pin_irq_enable = swm_pin_irq_enable,
506     .pin_get = swm_pin_get
507 };
508 
swm_pin_isr(GPIO_TypeDef * GPIOx)509 static void swm_pin_isr(GPIO_TypeDef *GPIOx)
510 {
511     static int gpio[24];
512     int index = 0;
513     static int init = 0;
514     const struct swm_pin_device *gpio_obj;
515 
516     if (init == 0)
517     {
518         init = 1;
519         for (gpio_obj = &pin_obj[0];
520              gpio_obj->index < ITEM_NUM(pin_obj);
521              gpio_obj++)
522         {
523             if (gpio_obj->gpio == GPIOx)
524             {
525                 gpio[index] = gpio_obj->index;
526                 index++;
527                 RT_ASSERT(index <= 24)
528             }
529         }
530     }
531     for (index = 0; index < 24; index++)
532     {
533         gpio_obj = _pin2struct(gpio[index]);
534         if (EXTI_State(gpio_obj->gpio, gpio_obj->pin))
535         {
536             EXTI_Clear(gpio_obj->gpio, gpio_obj->pin);
537             if (pin_irq_hdr_tab[gpio_obj->index].hdr)
538             {
539                 pin_irq_hdr_tab[gpio_obj->index].hdr(pin_irq_hdr_tab[gpio_obj->index].args);
540             }
541         }
542     }
543 }
544 
GPIOA_Handler(void)545 void GPIOA_Handler(void)
546 {
547     rt_interrupt_enter();
548     swm_pin_isr(GPIOA);
549     rt_interrupt_leave();
550 }
551 
GPIOB_Handler(void)552 void GPIOB_Handler(void)
553 {
554     rt_interrupt_enter();
555     swm_pin_isr(GPIOB);
556     rt_interrupt_leave();
557 }
558 
GPIOC_Handler(void)559 void GPIOC_Handler(void)
560 {
561     rt_interrupt_enter();
562     swm_pin_isr(GPIOC);
563     rt_interrupt_leave();
564 }
565 
GPIOM_Handler(void)566 void GPIOM_Handler(void)
567 {
568     rt_interrupt_enter();
569     swm_pin_isr(GPIOM);
570     rt_interrupt_leave();
571 }
572 
GPION_Handler(void)573 void GPION_Handler(void)
574 {
575     rt_interrupt_enter();
576     swm_pin_isr(GPION);
577     rt_interrupt_leave();
578 }
579 
GPIOP_Handler(void)580 void GPIOP_Handler(void)
581 {
582     rt_interrupt_enter();
583     swm_pin_isr(GPIOP);
584     rt_interrupt_leave();
585 }
586 
swm_pin_init(void)587 int swm_pin_init(void)
588 {
589     return rt_device_pin_register("pin", &swm_pin_ops, RT_NULL);
590 }
591 
592 #endif /* BSP_USING_GPIO */
593 #endif /* RT_USING_PIN */
594