1 /*
2 * Copyright (c) 2006-2022, Synwit Technology Co.,Ltd.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Change Logs:
7 * Date Author Notes
8 * 2018-12-10 Zohar_Lee first version
9 * 2020-07-10 lik format file
10 */
11
12 #include "drv_pwm.h"
13
14 #ifdef RT_USING_PWM
15 #ifdef BSP_USING_PWM
16
17 //#define DRV_DEBUG
18 #define LOG_TAG "drv.pwm"
19 #include <drv_log.h>
20
21 #if !defined(BSP_USING_PWM0) && !defined(BSP_USING_PWM1) && !defined(BSP_USING_PWM2) && !defined(BSP_USING_PWM3) && !defined(BSP_USING_PWM4) && !defined(BSP_USING_PWM5)
22 #error "Please define at least one BSP_USING_PWMx"
23 /* this driver can be disabled at menuconfig ? RT-Thread Components ? Device Drivers */
24 #endif
25
26 #define MIN_PERIOD 2
27 #define MIN_PULSE 1
28
29 #ifdef BSP_USING_PWM0
30 #ifndef PWM0_CFG
31 #define PWM0_CFG \
32 { \
33 .name = "pwm0", \
34 .PWMx = PWM0, \
35 .pwm_initstruct.clk_div = PWM_CLKDIV_8, \
36 .pwm_initstruct.mode = PWM_MODE_INDEP, \
37 .pwm_initstruct.cycleA = 10000, \
38 .pwm_initstruct.hdutyA = 5000, \
39 .pwm_initstruct.initLevelA = 1, \
40 .pwm_initstruct.cycleB = 10000, \
41 .pwm_initstruct.hdutyB = 5000, \
42 .pwm_initstruct.initLevelB = 1, \
43 .pwm_initstruct.HEndAIEn = 0, \
44 .pwm_initstruct.NCycleAIEn = 0, \
45 .pwm_initstruct.HEndBIEn = 0, \
46 .pwm_initstruct.NCycleBIEn = 0, \
47 }
48 #endif /* PWM0_CFG */
49 #endif /* BSP_USING_PWM0 */
50
51 #ifdef BSP_USING_PWM1
52 #ifndef PWM1_CFG
53 #define PWM1_CFG \
54 { \
55 .name = "pwm1", \
56 .PWMx = PWM1, \
57 .pwm_initstruct.clk_div = PWM_CLKDIV_8, \
58 .pwm_initstruct.mode = PWM_MODE_INDEP, \
59 .pwm_initstruct.cycleA = 10000, \
60 .pwm_initstruct.hdutyA = 5000, \
61 .pwm_initstruct.initLevelA = 1, \
62 .pwm_initstruct.cycleB = 10000, \
63 .pwm_initstruct.hdutyB = 5000, \
64 .pwm_initstruct.initLevelB = 1, \
65 .pwm_initstruct.HEndAIEn = 0, \
66 .pwm_initstruct.NCycleAIEn = 0, \
67 .pwm_initstruct.HEndBIEn = 0, \
68 .pwm_initstruct.NCycleBIEn = 0, \
69 }
70 #endif /* PWM1_CFG */
71 #endif /* BSP_USING_PWM1 */
72
73 #ifdef BSP_USING_PWM2
74 #ifndef PWM2_CFG
75 #define PWM2_CFG \
76 { \
77 .name = "pwm2", \
78 .PWMx = PWM2, \
79 .pwm_initstruct.clk_div = PWM_CLKDIV_8, \
80 .pwm_initstruct.mode = PWM_MODE_INDEP, \
81 .pwm_initstruct.cycleA = 10000, \
82 .pwm_initstruct.hdutyA = 5000, \
83 .pwm_initstruct.initLevelA = 1, \
84 .pwm_initstruct.cycleB = 10000, \
85 .pwm_initstruct.hdutyB = 5000, \
86 .pwm_initstruct.initLevelB = 1, \
87 .pwm_initstruct.HEndAIEn = 0, \
88 .pwm_initstruct.NCycleAIEn = 0, \
89 .pwm_initstruct.HEndBIEn = 0, \
90 .pwm_initstruct.NCycleBIEn = 0, \
91 }
92 #endif /* PWM2_CFG */
93 #endif /* BSP_USING_PWM2 */
94
95 #ifdef BSP_USING_PWM3
96 #ifndef PWM3_CFG
97 #define PWM3_CFG \
98 { \
99 .name = "pwm3", \
100 .PWMx = PWM3, \
101 .pwm_initstruct.clk_div = PWM_CLKDIV_8, \
102 .pwm_initstruct.mode = PWM_MODE_INDEP, \
103 .pwm_initstruct.cycleA = 10000, \
104 .pwm_initstruct.hdutyA = 5000, \
105 .pwm_initstruct.initLevelA = 1, \
106 .pwm_initstruct.cycleB = 10000, \
107 .pwm_initstruct.hdutyB = 5000, \
108 .pwm_initstruct.initLevelB = 1, \
109 .pwm_initstruct.HEndAIEn = 0, \
110 .pwm_initstruct.NCycleAIEn = 0, \
111 .pwm_initstruct.HEndBIEn = 0, \
112 .pwm_initstruct.NCycleBIEn = 0, \
113 }
114 #endif /* PWM3_CFG */
115 #endif /* BSP_USING_PWM3 */
116
117 #ifdef BSP_USING_PWM4
118 #ifndef PWM4_CFG
119 #define PWM4_CFG \
120 { \
121 .name = "pwm4", \
122 .PWMx = PWM4, \
123 .pwm_initstruct.clk_div = PWM_CLKDIV_8, \
124 .pwm_initstruct.mode = PWM_MODE_INDEP, \
125 .pwm_initstruct.cycleA = 10000, \
126 .pwm_initstruct.hdutyA = 5000, \
127 .pwm_initstruct.initLevelA = 1, \
128 .pwm_initstruct.cycleB = 10000, \
129 .pwm_initstruct.hdutyB = 5000, \
130 .pwm_initstruct.initLevelB = 1, \
131 .pwm_initstruct.HEndAIEn = 0, \
132 .pwm_initstruct.NCycleAIEn = 0, \
133 .pwm_initstruct.HEndBIEn = 0, \
134 .pwm_initstruct.NCycleBIEn = 0, \
135 }
136 #endif /* PWM4_CFG */
137 #endif /* BSP_USING_PWM4 */
138
139 #ifdef BSP_USING_PWM5
140 #ifndef PWM5_CFG
141 #define PWM5_CFG \
142 { \
143 .name = "pwm5", \
144 .PWMx = PWM5, \
145 .pwm_initstruct.clk_div = PWM_CLKDIV_8, \
146 .pwm_initstruct.mode = PWM_MODE_INDEP, \
147 .pwm_initstruct.cycleA = 10000, \
148 .pwm_initstruct.hdutyA = 5000, \
149 .pwm_initstruct.initLevelA = 1, \
150 .pwm_initstruct.cycleB = 10000, \
151 .pwm_initstruct.hdutyB = 5000, \
152 .pwm_initstruct.initLevelB = 1, \
153 .pwm_initstruct.HEndAIEn = 0, \
154 .pwm_initstruct.NCycleAIEn = 0, \
155 .pwm_initstruct.HEndBIEn = 0, \
156 .pwm_initstruct.NCycleBIEn = 0, \
157 }
158 #endif /* PWM5_CFG */
159 #endif /* BSP_USING_PWM5 */
160
161 struct swm_pwm_cfg
162 {
163 const char *name;
164 PWM_TypeDef *PWMx;
165 PWM_InitStructure pwm_initstruct;
166 };
167
168 struct swm_pwm_device
169 {
170 struct swm_pwm_cfg *pwm_cfg;
171 struct rt_device_pwm pwm_device;
172 };
173
174 static struct swm_pwm_cfg swm_pwm_cfg[] =
175 {
176 #ifdef BSP_USING_PWM0
177 PWM0_CFG,
178 #endif
179 #ifdef BSP_USING_PWM1
180 PWM1_CFG,
181 #endif
182 #ifdef BSP_USING_PWM2
183 PWM2_CFG,
184 #endif
185 #ifdef BSP_USING_PWM3
186 PWM3_CFG,
187 #endif
188 #ifdef BSP_USING_PWM4
189 PWM4_CFG,
190 #endif
191 #ifdef BSP_USING_PWM5
192 PWM5_CFG,
193 #endif
194 };
195
196 static struct swm_pwm_device pwm_obj[sizeof(swm_pwm_cfg) / sizeof(swm_pwm_cfg[0])] = {0};
197
swm_pwm_enable(struct rt_device_pwm * pwm_device,struct rt_pwm_configuration * configuration,rt_bool_t enable)198 static rt_err_t swm_pwm_enable(struct rt_device_pwm *pwm_device, struct rt_pwm_configuration *configuration, rt_bool_t enable)
199 {
200 struct swm_pwm_cfg *pwm_cfg = RT_NULL;
201 RT_ASSERT(pwm_device != RT_NULL);
202 pwm_cfg = pwm_device->parent.user_data;
203
204 if (!enable)
205 {
206 if (PWM_CH_A == configuration->channel)
207 {
208 PWM_Stop(pwm_cfg->PWMx, 1, 0);
209 }
210 if (PWM_CH_B == configuration->channel)
211 {
212 PWM_Stop(pwm_cfg->PWMx, 0, 1);
213 }
214 }
215 else
216 {
217 if (PWM_CH_A == configuration->channel)
218 {
219 PWM_Start(pwm_cfg->PWMx, 1, 0);
220 }
221 if (PWM_CH_B == configuration->channel)
222 {
223 PWM_Start(pwm_cfg->PWMx, 0, 1);
224 }
225 }
226
227 return RT_EOK;
228 }
229
swm_pwm_get(struct rt_device_pwm * pwm_device,struct rt_pwm_configuration * configuration)230 static rt_err_t swm_pwm_get(struct rt_device_pwm *pwm_device, struct rt_pwm_configuration *configuration)
231 {
232 rt_uint64_t tim_clock;
233 tim_clock = SystemCoreClock / 8;
234
235 struct swm_pwm_cfg *pwm_cfg = RT_NULL;
236 RT_ASSERT(pwm_device != RT_NULL);
237 pwm_cfg = pwm_device->parent.user_data;
238
239 /* Convert nanosecond to frequency and duty cycle. 1s = 1 * 1000 * 1000 * 1000 ns */
240 tim_clock /= 1000000UL;
241 configuration->period = PWM_GetCycle(pwm_cfg->PWMx, configuration->channel) * 1000UL / tim_clock;
242 configuration->pulse = PWM_GetHDuty(pwm_cfg->PWMx, configuration->channel) * 1000UL / tim_clock;
243
244 return RT_EOK;
245 }
246
swm_pwm_set(struct rt_device_pwm * pwm_device,struct rt_pwm_configuration * configuration)247 static rt_err_t swm_pwm_set(struct rt_device_pwm *pwm_device, struct rt_pwm_configuration *configuration)
248 {
249 rt_uint32_t period, pulse;
250 rt_uint64_t tim_clock;
251 tim_clock = SystemCoreClock / 8;
252
253 struct swm_pwm_cfg *pwm_cfg = RT_NULL;
254 RT_ASSERT(pwm_device != RT_NULL);
255 pwm_cfg = pwm_device->parent.user_data;
256
257 /* Convert nanosecond to frequency and duty cycle. 1s = 1 * 1000 * 1000 * 1000 ns */
258 /* when SystemCoreClock = 120MHz, configuration->period max 4.369ms */
259 /* when SystemCoreClock = 20MHz, configuration->period max 26.214ms */
260 tim_clock /= 1000000UL;
261 period = (unsigned long long)configuration->period * tim_clock / 1000ULL;
262 pulse = (unsigned long long)configuration->pulse * tim_clock / 1000ULL;
263 if (period < MIN_PERIOD)
264 {
265 period = MIN_PERIOD;
266 }
267 if (pulse < MIN_PULSE)
268 {
269 pulse = MIN_PULSE;
270 }
271 PWM_SetCycle(pwm_cfg->PWMx, configuration->channel, period);
272 PWM_SetHDuty(pwm_cfg->PWMx, configuration->channel, pulse);
273
274 return RT_EOK;
275 }
276
swm_pwm_control(struct rt_device_pwm * pwm_device,int cmd,void * arg)277 static rt_err_t swm_pwm_control(struct rt_device_pwm *pwm_device, int cmd, void *arg)
278 {
279 RT_ASSERT(pwm_device != RT_NULL);
280
281 struct rt_pwm_configuration *configuration = (struct rt_pwm_configuration *)arg;
282
283 switch (cmd)
284 {
285 case PWM_CMD_ENABLE:
286 return swm_pwm_enable(pwm_device, configuration, RT_TRUE);
287 case PWM_CMD_DISABLE:
288 return swm_pwm_enable(pwm_device, configuration, RT_FALSE);
289 case PWM_CMD_SET:
290 return swm_pwm_set(pwm_device, configuration);
291 case PWM_CMD_GET:
292 return swm_pwm_get(pwm_device, configuration);
293 default:
294 return -RT_EINVAL;
295 }
296 }
297
298 static struct rt_pwm_ops pwm_ops =
299 {
300 swm_pwm_control};
301
swm_pwm_init(void)302 int swm_pwm_init(void)
303 {
304 int i = 0;
305 int result = RT_EOK;
306
307 for (i = 0; i < sizeof(swm_pwm_cfg) / sizeof(swm_pwm_cfg[0]); i++)
308 {
309 pwm_obj[i].pwm_cfg = &swm_pwm_cfg[i];
310
311 if (pwm_obj[i].pwm_cfg->PWMx == PWM0)
312 {
313 #ifdef BSP_USING_PWM0A
314 PORT_Init(PORTC, PIN2, FUNMUX0_PWM0A_OUT, 0);
315 #endif
316 #ifdef BSP_USING_PWM0B
317 PORT_Init(PORTC, PIN4, FUNMUX0_PWM0B_OUT, 0);
318 #endif
319 }
320 else if (pwm_obj[i].pwm_cfg->PWMx == PWM1)
321 {
322 #ifdef BSP_USING_PWM1A
323 PORT_Init(PORTC, PIN3, FUNMUX1_PWM1A_OUT, 0);
324 #endif
325 #ifdef BSP_USING_PWM1B
326 PORT_Init(PORTC, PIN5, FUNMUX1_PWM1B_OUT, 0);
327 #endif
328 }
329 else if (pwm_obj[i].pwm_cfg->PWMx == PWM2)
330 {
331 #ifdef BSP_USING_PWM2A
332 PORT_Init(PORTN, PIN4, FUNMUX0_PWM2A_OUT, 0);
333 #endif
334 #ifdef BSP_USING_PWM2B
335 PORT_Init(PORTN, PIN6, FUNMUX0_PWM2B_OUT, 0);
336 #endif
337 }
338 else if (pwm_obj[i].pwm_cfg->PWMx == PWM3)
339 {
340 #ifdef BSP_USING_PWM3A
341 PORT_Init(PORTN, PIN3, FUNMUX1_PWM3A_OUT, 0);
342 #endif
343 #ifdef BSP_USING_PWM3B
344 PORT_Init(PORTN, PIN5, FUNMUX1_PWM3B_OUT, 0);
345 #endif
346 }
347 else if (pwm_obj[i].pwm_cfg->PWMx == PWM4)
348 {
349 #ifdef BSP_USING_PWM4A
350 PORT_Init(PORTN, PIN8, FUNMUX0_PWM4A_OUT, 0);
351 #endif
352 #ifdef BSP_USING_PWM4B
353 PORT_Init(PORTN, PIN10, FUNMUX0_PWM4B_OUT, 0);
354 #endif
355 }
356 else if (pwm_obj[i].pwm_cfg->PWMx == PWM5)
357 {
358 #ifdef BSP_USING_PWM5A
359 PORT_Init(PORTN, PIN7, FUNMUX1_PWM5A_OUT, 0);
360 #endif
361 #ifdef BSP_USING_PWM5B
362 PORT_Init(PORTN, PIN9, FUNMUX1_PWM5B_OUT, 0);
363 #endif
364 }
365
366 PWM_Init(pwm_obj[i].pwm_cfg->PWMx, &(pwm_obj[i].pwm_cfg->pwm_initstruct));
367 result = rt_device_pwm_register(&pwm_obj[i].pwm_device, pwm_obj[i].pwm_cfg->name, &pwm_ops, pwm_obj[i].pwm_cfg);
368 if(result != RT_EOK)
369 {
370 LOG_E("%s register fail.", pwm_obj[i].pwm_cfg->name);
371 }
372 else
373 {
374 LOG_D("%s register success.", pwm_obj[i].pwm_cfg->name);
375 }
376 }
377 return result;
378 }
379 INIT_DEVICE_EXPORT(swm_pwm_init);
380
381 #endif /* BSP_USING_PWM */
382 #endif /* RT_USING_PWM */
383