1 #ifndef __SWM341_SDRAM_H__ 2 #define __SWM341_SDRAM_H__ 3 4 typedef struct { 5 uint8_t Size; // SDRAM 容量，SDRAM_SIZE_2MB、SDRAM_SIZE_8MB、SDRAM_SIZE_16MB、SDRAM_SIZE_32MB 6 uint8_t ClkDiv; // SDRAM 时钟分频，SDRAM_CLKDIV_1、SDRAM_CLKDIV_2 7 uint8_t CASLatency; // 列地址到有效数据输出间隔，SDRAM_CASLATENCY_2、SDRAM_CASLATENCY_3 8 uint8_t RefreshTime; // 刷新时间，单位 ms，在这个时间内 SDRAM 必须完成一次整片刷新，通常为 64ms 9 10 uint8_t TimeTRP; // Row precharge delay，Precharge命令到另一个命令间延时 11 uint8_t TimeTRCD; // Row to column delay，行地址到列地址间延时，也即Activate命令到读写命令间延时 12 uint8_t TimeTRC; // Row cycle time, Activate to Activate on same bank 13 // 若 SDRAM 颗粒除了 tRC，还有 tRFC 或 tRRC 参数，则按照二者中较大的计算 TimeTRC 14 } SDRAM_InitStructure; 15 16 // rowaddr bankaddr coladdr 17 #define SDRAM_SIZE_2MB 3 // HADDR[20:10] HADDR[9] HADDR[8:1] 18 #define SDRAM_SIZE_8MB 0 // HADDR[22:11] HADDR[10:9] HADDR[8:1] 19 #define SDRAM_SIZE_16MB 1 // HADDR[23:12] HADDR[11:10] HADDR[9:1] 20 #define SDRAM_SIZE_32MB 2 // HADDR[24:12] HADDR[11:10] HADDR[9:1] 21 22 #define SDRAM_CLKDIV_1 0 // 支持的 CPU 频率范围：80MHz--125MHz 23 #define SDRAM_CLKDIV_2 1 // 支持的 CPU 频率范围：20MHz--160Mhz 24 25 #define SDRAM_CASLATENCY_2 0 26 #define SDRAM_CASLATENCY_3 1 27 28 29 #define SDRAM_TRP_1 0 30 #define SDRAM_TRP_2 1 31 #define SDRAM_TRP_3 2 32 #define SDRAM_TRP_4 3 33 34 #define SDRAM_TRCD_1 0 35 #define SDRAM_TRCD_2 1 36 #define SDRAM_TRCD_3 2 37 #define SDRAM_TRCD_4 3 38 39 #define SDRAM_TRC_4 3 40 #define SDRAM_TRC_5 4 41 #define SDRAM_TRC_6 5 42 #define SDRAM_TRC_7 6 43 #define SDRAM_TRC_8 7 44 #define SDRAM_TRC_9 8 45 #define SDRAM_TRC_10 9 46 #define SDRAM_TRC_11 10 47 #define SDRAM_TRC_12 11 48 #define SDRAM_TRC_13 12 49 #define SDRAM_TRC_14 13 50 #define SDRAM_TRC_15 14 51 #define SDRAM_TRC_16 15 52 53 54 void SDRAM_Init(SDRAM_InitStructure * initStruct); 55 56 void SDRAM_Enable(void); 57 void SDRAM_Disable(void); 58 59 #endif //__SWM341_SDRAM_H__ 60