1 /*
2 * Copyright (c) 2006-2022, Synwit Technology Co.,Ltd.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Change Logs:
7 * Date Author Notes
8 * 2021-07-01 lik first version
9 */
10
11 #include "drv_adc.h"
12
13 #ifdef RT_USING_ADC
14 #ifdef BSP_USING_ADC
15
16 //#define DRV_DEBUG
17 #define LOG_TAG "drv.adc"
18 #include <drv_log.h>
19
20 #if !defined(BSP_USING_ADC0) && !defined(BSP_USING_ADC1)
21 #error "Please define at least one BSP_USING_ADCx"
22 /* this driver can be disabled at menuconfig ? RT-Thread Components ? Device Drivers */
23 #endif
24
25 #ifdef BSP_USING_ADC0
26 #ifndef ADC0_CFG
27 #define ADC0_CFG \
28 { \
29 .name = "adc0", \
30 .ADCx = ADC0, \
31 .ADC_initstruct.clk_src = ADC_CLKSRC_HRC_DIV8, \
32 .ADC_initstruct.samplAvg = ADC_AVG_SAMPLE1, \
33 .ADC_initstruct.EOC_IEn = 0, \
34 .ADC_initstruct.HalfIEn = 0, \
35 .ADC_SEQ_initstruct.trig_src = ADC_TRIGGER_SW, \
36 .ADC_SEQ_initstruct.conv_cnt = 1, \
37 .ADC_SEQ_initstruct.samp_tim = ADC_SAMPLE_1CLOCK, \
38 }
39 #endif /* ADC0_CFG */
40 #endif /* BSP_USING_ADC0 */
41
42 #ifdef BSP_USING_ADC1
43 #ifndef ADC1_CFG
44 #define ADC1_CFG \
45 { \
46 .name = "adc1", \
47 .ADCx = ADC1, \
48 .ADC_initstruct.clk_src = ADC_CLKSRC_HRC_DIV8, \
49 .ADC_initstruct.samplAvg = ADC_AVG_SAMPLE1, \
50 .ADC_initstruct.EOC_IEn = 0, \
51 .ADC_initstruct.HalfIEn = 0, \
52 .ADC_SEQ_initstruct.trig_src = ADC_TRIGGER_SW, \
53 .ADC_SEQ_initstruct.conv_cnt = 1, \
54 .ADC_SEQ_initstruct.samp_tim = ADC_SAMPLE_1CLOCK, \
55 }
56 #endif /* ADC1_CFG */
57 #endif /* BSP_USING_ADC1 */
58
59 struct swm_adc_cfg
60 {
61 const char *name;
62 ADC_TypeDef *ADCx;
63 ADC_InitStructure ADC_initstruct;
64 ADC_SEQ_InitStructure ADC_SEQ_initstruct;
65 };
66
67 struct swm_adc_device
68 {
69 struct swm_adc_cfg *adc_cfg;
70 struct rt_adc_device adc_device;
71 };
72
73 static struct swm_adc_cfg swm_adc_cfg[] =
74 {
75 #ifdef BSP_USING_ADC0
76 ADC0_CFG,
77 #endif
78 #ifdef BSP_USING_ADC1
79 ADC1_CFG,
80 #endif
81 };
82
83 static struct swm_adc_device adc_obj[sizeof(swm_adc_cfg) / sizeof(swm_adc_cfg[0])];
84
swm_adc_get_channel(rt_uint32_t channel)85 static rt_uint32_t swm_adc_get_channel(rt_uint32_t channel)
86 {
87 rt_uint32_t swm_channel = 0;
88
89 switch (channel)
90 {
91 case 0:
92 swm_channel = ADC_CH0;
93 break;
94 case 1:
95 swm_channel = ADC_CH1;
96 break;
97 case 2:
98 swm_channel = ADC_CH2;
99 break;
100 case 3:
101 swm_channel = ADC_CH3;
102 break;
103 case 4:
104 swm_channel = ADC_CH4;
105 break;
106 case 5:
107 swm_channel = ADC_CH5;
108 break;
109 case 6:
110 swm_channel = ADC_CH6;
111 break;
112 case 7:
113 swm_channel = ADC_CH7;
114 break;
115 case 8:
116 swm_channel = ADC_CH8;
117 break;
118 case 9:
119 swm_channel = ADC_CH9;
120 break;
121 case 10:
122 swm_channel = ADC_CH10;
123 break;
124 case 11:
125 swm_channel = ADC_CH11;
126 break;
127 }
128
129 return swm_channel;
130 }
131
swm_adc_enabled(struct rt_adc_device * adc_device,rt_uint32_t channel,rt_bool_t enabled)132 static rt_err_t swm_adc_enabled(struct rt_adc_device *adc_device, rt_uint32_t channel, rt_bool_t enabled)
133 {
134 uint32_t adc_chn;
135 struct swm_adc_cfg *adc_cfg;
136 RT_ASSERT(adc_device != RT_NULL);
137 adc_cfg = adc_device->parent.user_data;
138
139 if (channel < 12)
140 {
141 /* set swm ADC channel */
142 adc_chn = swm_adc_get_channel(channel);
143 }
144 else
145 {
146 LOG_E("ADC channel must be between 0 and 11.");
147 return -RT_ERROR;
148 }
149
150 if (enabled)
151 {
152 adc_cfg->ADCx->SEQCHN0 |= adc_chn;
153 }
154 else
155 {
156 adc_cfg->ADCx->SEQCHN0 &= ~adc_chn;
157 }
158
159 return RT_EOK;
160 }
161
swm_adc_convert(struct rt_adc_device * adc_device,rt_uint32_t channel,rt_uint32_t * value)162 static rt_err_t swm_adc_convert(struct rt_adc_device *adc_device, rt_uint32_t channel, rt_uint32_t *value)
163 {
164 uint32_t chn, val, adc_chn;
165 struct swm_adc_cfg *adc_cfg;
166 RT_ASSERT(adc_device != RT_NULL);
167 RT_ASSERT(value != RT_NULL);
168 adc_cfg = adc_device->parent.user_data;
169
170 if (channel < 12)
171 {
172 /* set swm ADC channel */
173 adc_chn = swm_adc_get_channel(channel);
174 }
175 else
176 {
177 LOG_E("ADC channel must be between 0 and 11.");
178 return -RT_ERROR;
179 }
180
181 *value = 0xFFFFFFFF;
182
183 /* start ADC */
184 ADC_Start(adc_cfg->ADCx, ADC_SEQ0);
185
186 /* Wait for the ADC to convert */
187 while (adc_cfg->ADCx->GO & ADC_GO_BUSY_Msk)
188 __NOP();
189 while ((adc_cfg->ADCx->SEQ[0].SR & ADC_SR_EMPTY_Msk) == 0)
190 {
191 val = ADC_Read(adc_cfg->ADCx, ADC_SEQ0, &chn);
192 if (chn == adc_chn)
193 {
194 *value = val;
195 }
196 }
197
198 if (*value == 0xFFFFFFFF)
199 {
200 LOG_E("ADC channel can not find.");
201 return -RT_ERROR;
202 }
203
204 return RT_EOK;
205 }
206
207 static const struct rt_adc_ops swm_adc_ops =
208 {
209 .enabled = swm_adc_enabled,
210 .convert = swm_adc_convert,
211 };
212
swm_adc_init(void)213 int swm_adc_init(void)
214 {
215 int i = 0;
216 int result = RT_EOK;
217
218 for (i = 0; i < sizeof(swm_adc_cfg) / sizeof(swm_adc_cfg[0]); i++)
219 {
220 /* ADC init */
221 adc_obj[i].adc_cfg = &swm_adc_cfg[i];
222
223 if (adc_obj[i].adc_cfg->ADCx == ADC0)
224 {
225 #ifdef BSP_USING_ADC0_CHN0
226 adc_obj[i].adc_cfg->ADC_SEQ_initstruct.channels |= ADC_CH0;
227 PORT_Init(PORTC, PIN6, PORTC_PIN6_ADC0_CH0, 0); //PC.6 => ADC.CH0
228 #endif
229 #ifdef BSP_USING_ADC0_CHN1
230 adc_obj[i].adc_cfg->ADC_SEQ_initstruct.channels |= ADC_CH1;
231 PORT_Init(PORTC, PIN5, PORTC_PIN5_ADC0_CH1, 0); //PC.5 => ADC.CH1
232 #endif
233 #ifdef BSP_USING_ADC0_CHN2
234 adc_obj[i].adc_cfg->ADC_SEQ_initstruct.channels |= ADC_CH2;
235 PORT_Init(PORTC, PIN4, PORTC_PIN4_ADC0_CH2, 0); //PC.4 => ADC.CH2
236 #endif
237 #ifdef BSP_USING_ADC0_CHN3
238 adc_obj[i].adc_cfg->ADC_SEQ_initstruct.channels |= ADC_CH3;
239 PORT_Init(PORTC, PIN3, PORTC_PIN3_ADC0_CH3, 0); //PC.3 => ADC.CH3
240 #endif
241 #ifdef BSP_USING_ADC0_CHN4
242 adc_obj[i].adc_cfg->ADC_SEQ_initstruct.channels |= ADC_CH4;
243 PORT_Init(PORTC, PIN2, PORTC_PIN2_ADC0_CH4, 0); //PC.2 => ADC.CH4
244 #endif
245 #ifdef BSP_USING_ADC0_CHN5
246 adc_obj[i].adc_cfg->ADC_SEQ_initstruct.channels |= ADC_CH5;
247 PORT_Init(PORTC, PIN1, PORTC_PIN1_ADC0_CH5, 0); //PC.1 => ADC.CH5
248 #endif
249 #ifdef BSP_USING_ADC0_CHN6
250 adc_obj[i].adc_cfg->ADC_SEQ_initstruct.channels |= ADC_CH6;
251 PORT_Init(PORTC, PIN0, PORTC_PIN0_ADC0_CH6, 0); //PC.0 => ADC.CH6
252 #endif
253 #ifdef BSP_USING_ADC0_CHN7
254 adc_obj[i].adc_cfg->ADC_SEQ_initstruct.channels |= ADC_CH7;
255 PORT_Init(PORTA, PIN15, PORTA_PIN15_ADC0_CH7, 0); //PA.15 => ADC.CH7
256 #endif
257 #ifdef BSP_USING_ADC0_CHN8
258 adc_obj[i].adc_cfg->ADC_SEQ_initstruct.channels |= ADC_CH8;
259 PORT_Init(PORTA, PIN14, PORTA_PIN14_ADC0_CH8, 0); //PA.14 => ADC.CH8
260 #endif
261 #ifdef BSP_USING_ADC0_CHN9
262 adc_obj[i].adc_cfg->ADC_SEQ_initstruct.channels |= ADC_CH9;
263 PORT_Init(PORTA, PIN13, PORTA_PIN13_ADC0_CH9, 0); //PA.13 => ADC.CH9
264 #endif
265 #ifdef BSP_USING_ADC0_CHN10
266 adc_obj[i].adc_cfg->ADC_SEQ_initstruct.channels |= ADC_CH10;
267 PORT_Init(PORTA, PIN12, PORTA_PIN12_ADC0_CH10, 0); //PA.12 => ADC.CH10
268 #endif
269 #ifdef BSP_USING_ADC0_CHN11
270 adc_obj[i].adc_cfg->ADC_SEQ_initstruct.channels |= ADC_CH11;
271 PORT_Init(PORTA, PIN10, PORTA_PIN10_ADC0_CH11, 0); //PA.10 => ADC.CH11
272 #endif
273 }
274 else if (adc_obj[i].adc_cfg->ADCx == ADC1)
275 {
276 #ifdef BSP_USING_ADC1_CHN0
277 adc_obj[i].adc_cfg->ADC_SEQ_initstruct.channels |= ADC_CH0;
278 PORT_Init(PORTD, PIN1, PORTD_PIN1_ADC1_CH0, 0); //PD.1 => ADC1.CH0
279 #endif
280 #ifdef BSP_USING_ADC1_CHN1
281 adc_obj[i].adc_cfg->ADC_SEQ_initstruct.channels |= ADC_CH1;
282 PORT_Init(PORTD, PIN0, PORTD_PIN0_ADC1_CH1, 0); //PD.0 => ADC1.CH1
283 #endif
284 #ifdef BSP_USING_ADC1_CHN2
285 adc_obj[i].adc_cfg->ADC_SEQ_initstruct.channels |= ADC_CH2;
286 PORT_Init(PORTC, PIN13, PORTC_PIN13_ADC1_CH2, 0); //PC.13 => ADC1.CH2
287 #endif
288 #ifdef BSP_USING_ADC1_CHN3
289 adc_obj[i].adc_cfg->ADC_SEQ_initstruct.channels |= ADC_CH3;
290 PORT_Init(PORTC, PIN12, PORTC_PIN12_ADC1_CH3, 0); //PC.12 => ADC1.CH3
291 #endif
292 #ifdef BSP_USING_ADC1_CHN4
293 adc_obj[i].adc_cfg->ADC_SEQ_initstruct.channels |= ADC_CH4;
294 PORT_Init(PORTC, PIN11, PORTC_PIN11_ADC1_CH4, 0); //PC.11 => ADC1.CH4
295 #endif
296 #ifdef BSP_USING_ADC1_CHN5
297 adc_obj[i].adc_cfg->ADC_SEQ_initstruct.channels |= ADC_CH5;
298 PORT_Init(PORTC, PIN10, PORTC_PIN10_ADC1_CH5, 0); //PC.10 => ADC1.CH5
299 #endif
300 #ifdef BSP_USING_ADC1_CHN6
301 adc_obj[i].adc_cfg->ADC_SEQ_initstruct.channels |= ADC_CH6;
302 PORT_Init(PORTC, PIN9, PORTC_PIN9_ADC1_CH6, 0); //PC.9 => ADC1.CH6
303 #endif
304 }
305
306 ADC_Init(adc_obj[i].adc_cfg->ADCx, &(adc_obj[i].adc_cfg->ADC_initstruct));
307 ADC_SEQ_Init(adc_obj[i].adc_cfg->ADCx, ADC_SEQ0, &(adc_obj[i].adc_cfg->ADC_SEQ_initstruct));
308 ADC_Open(adc_obj[i].adc_cfg->ADCx);
309 ADC_Calibrate(adc_obj[i].adc_cfg->ADCx);
310
311 result = rt_hw_adc_register(&adc_obj[i].adc_device, adc_obj[i].adc_cfg->name, &swm_adc_ops, adc_obj[i].adc_cfg);
312 if(result != RT_EOK)
313 {
314 LOG_E("%s register fail.", adc_obj[i].adc_cfg->name);
315 }
316 else
317 {
318 LOG_D("%s register success.", adc_obj[i].adc_cfg->name);
319 }
320 }
321
322 return result;
323 }
324 INIT_BOARD_EXPORT(swm_adc_init);
325 #endif /* BSP_USING_ADC */
326 #endif /* RT_USING_ADC */
327