1 /*
2 * Copyright (C) 2017-2019 Alibaba Group Holding Limited
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Change Logs:
7 * Date Author Notes
8 * 2020-08-20 zx.chen CSI Device System Source File
9 */
10
11 #include <csi_config.h>
12 #include <soc.h>
13 #include <csi_core.h>
14 #include <drv_irq.h>
15
16 #ifndef CONFIG_SYSTICK_HZ
17 #define CONFIG_SYSTICK_HZ 100
18 #endif
19
20 int g_system_clock = IHS_VALUE;
21 extern int32_t g_top_irqstack;
22 extern void irq_vectors_init(void);
23 extern void mm_heap_initialize(void);
24
25 int SystemCoreClock = IHS_VALUE; /* System Core Clock Frequency */
26 extern int __Vectors;
27
SystemCoreClockUpdate(void)28 void SystemCoreClockUpdate(void)
29 {
30 SystemCoreClock = IHS_VALUE;
31 }
32
33
_system_init_for_kernel(void)34 static void _system_init_for_kernel(void)
35 {
36 irq_vectors_init();
37
38 csi_coret_config(drv_get_sys_freq() / CONFIG_SYSTICK_HZ, CORET_IRQn); //10ms
39 drv_irq_enable(CORET_IRQn);
40 }
41
42 /**
43 * @brief initialize system map
44 * @param None
45 * @return None
46 */
systemmap_config(void)47 void systemmap_config(void)
48 {
49 csi_sysmap_config_region(0, 0x20000000, SYSMAP_SYSMAPCFG_B_Msk | SYSMAP_SYSMAPCFG_C_Msk);
50 csi_sysmap_config_region(1, 0x40000000, SYSMAP_SYSMAPCFG_B_Msk | SYSMAP_SYSMAPCFG_C_Msk);
51 csi_sysmap_config_region(2, 0x50000000, SYSMAP_SYSMAPCFG_SO_Msk);
52 csi_sysmap_config_region(3, 0x50700000, SYSMAP_SYSMAPCFG_B_Msk | SYSMAP_SYSMAPCFG_C_Msk);
53 csi_sysmap_config_region(4, 0x60000000, SYSMAP_SYSMAPCFG_SO_Msk);
54 csi_sysmap_config_region(5, 0x80000000, SYSMAP_SYSMAPCFG_B_Msk | SYSMAP_SYSMAPCFG_C_Msk);
55 csi_sysmap_config_region(6, 0x90000000, SYSMAP_SYSMAPCFG_B_Msk | SYSMAP_SYSMAPCFG_C_Msk);
56 csi_sysmap_config_region(7, 0xf0000000, SYSMAP_SYSMAPCFG_SO_Msk);
57 }
58
59 /**
60 * @brief initialize the system
61 * Initialize the psr and vbr.
62 * @param None
63 * @return None
64 */
SystemInit(void)65 void SystemInit(void)
66 {
67 int i;
68 #if ((CONFIG_CPU_E902 != 1) && (CONFIG_CPU_E902M != 1))
69 systemmap_config();
70 #endif
71
72 /* enable mstatus FS */
73 #if (__riscv_flen)
74 uint32_t mstatus = __get_MSTATUS();
75 mstatus |= (1 << 13);
76 __set_MSTATUS(mstatus);
77 #endif
78
79 /* enable mxstatus THEADISAEE */
80 uint32_t mxstatus = __get_MXSTATUS();
81 mxstatus |= (1 << 22);
82 /* enable mxstatus MM */
83 #if ((CONFIG_CPU_E906==1) || (CONFIG_CPU_E906F==1) || (CONFIG_CPU_E906FD==1))
84 mxstatus |= (1 << 15);
85 #endif
86 __set_MXSTATUS(mxstatus);
87
88
89 /* get interrupt level from info */
90 CLIC->CLICCFG = (((CLIC->CLICINFO & CLIC_INFO_CLICINTCTLBITS_Msk) >> CLIC_INFO_CLICINTCTLBITS_Pos) << CLIC_CLICCFG_NLBIT_Pos);
91
92 for (i = 0; i < 64; i++)
93 {
94 CLIC->CLICINT[i].IP = 0;
95 CLIC->CLICINT[i].ATTR = 1; /* use vector interrupt */
96 }
97
98 /* tspend use positive interrupt */
99 CLIC->CLICINT[Machine_Software_IRQn].ATTR = 0x3;
100
101 #if ((CONFIG_CPU_E902 != 1) && (CONFIG_CPU_E902M != 1))
102 csi_dcache_enable();
103 #endif
104 csi_icache_enable();
105 drv_irq_enable(Machine_Software_IRQn);
106
107 _system_init_for_kernel();
108 }
109