1 //#############################################################################
2 //
3 // FILE:   F2837xD_Can_defines.h
4 //
5 // TITLE:  Common defines used in CAN Test Cases
6 //
7 //#############################################################################
8 // $TI Release: F2837xD Support Library v3.05.00.00 $
9 // $Release Date: Tue Jun 26 03:15:23 CDT 2018 $
10 // $Copyright:
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41 //#############################################################################
42 
43 #ifndef F2837xD_CAN_DEFINES_H
44 #define F2837xD_CAN_DEFINES_H
45 
46 #ifdef __cplusplus
47 extern "C" {
48 #endif
49 
50 //
51 // Defines
52 //
53 
54 //
55 // Reset Values
56 //
57 #define CAN_RESET_VALUE_ZERO			0x00000000
58 #define CAN_CTL_RESET_VALUE		    	0x00001401
59 #define CAN_ES_RESET_VALUE				0x00000007
60 #define CAN_BTR_RESET_VALUE		    	0x00002301
61 #define CAN_REL_RESET_VALUE		    	0xA3170504
62 #define CAN_RAM_INIT_RESET_VALUE		0x00000005
63 #define CAN_IF_CMD_RESET_VALUE			0x00000001
64 #define CAN_IF_MASK_RESET_VALUE	    	0xFFFFFFFF
65 
66 //
67 // Register value when Peripheral Clock is Disabled
68 //
69 #define CAN_MODULE_CLK_DISABLE_VALUE	0x00000000
70 
71 //
72 // Bit field definition of CAN_CTL register.
73 //
74 #define CAN_CTL_INIT		0x00000001  // Initialization
75 #define CAN_CTL_IE0         0x00000002  // Interrupt Enable 0
76 #define CAN_CTL_SIE         0x00000004  // Status Interrupt Enable
77 #define CAN_CTL_EIE         0x00000008  // Error Interrupt Enable
78 #define CAN_CTL_DAR         0x00000020  // Disable Automatic-Retransmission
79 #define CAN_CTL_CCE         0x00000040  // Configuration Change Enable
80 #define CAN_CTL_TEST        0x00000080  // Test Mode Enable
81 #define CAN_CTL_IDS		    0x00000100	// Interruption Debug Support Enable
82 #define CAN_CTL_ABO		    0x00000200	// Auto-Bus On Enable
83 #define CAN_CTL_PMD_S		10
84 #define CAN_CTL_PMD_M		0x00003C00	// Parity/SECDED Enable
85 #define CAN_CTL_SWR		    0x00008000	// Software Reset Enable
86 #define CAN_CTL_INITDBG	    0x00010000	// Debug Mode Status
87 #define CAN_CTL_IE1		    0x00020000	// Interrupt Enable 1
88 #define CAN_CTL_PDR		    0x01000000	// Power Down Mode Request
89 #define CAN_CTL_WUBA		0x02000000	// Wake Up on Bus Activity
90 
91 //
92 // Bit field definition of CAN_IF1_CMD register.
93 //
94 #define CAN_IF1_CMD_MESSNUM_S		0
95 #define CAN_IF1_CMD_MESSNUM_M		0x000000FF	// Message Number
96 #define CAN_IF1_CMD_BUSY			0x00008000	// Busy Flag
97 #define CAN_IF1_CMD_DATAB			0x00010000	// Access Data B
98 #define CAN_IF1_CMD_DATAA			0x00020000	// Access Data A
99 #define CAN_IF1_CMD_TXRQSTNDAT		0x00040000	// Transmission Request Bit
100 #define CAN_IF1_CMD_CLRINTPND		0x00080000	// Clear Interrupt Pending Bit
101 #define CAN_IF1_CMD_CONTROL		    0x00100000	// Access Control Bits
102 #define CAN_IF1_CMD_ARB			    0x00200000	// Access Arbitration Bits
103 #define CAN_IF1_CMD_MASK			0x00400000	// Access Mask Bits
104 #define CAN_IF1_CMD_WR_RD			0x00800000	// Write and Read
105 
106 //
107 // Bit field definition of CAN_IF2_CMD register.
108 //
109 #define CAN_IF2_CMD_MESSNUM_S		0
110 #define CAN_IF2_CMD_MESSNUM_M		0x000000FF	// Message Number
111 #define CAN_IF2_CMD_BUSY			0x00008000	// Busy Flag
112 #define CAN_IF2_CMD_DATAB			0x00010000	// Access Data B
113 #define CAN_IF2_CMD_DATAA			0x00020000	// Access Data A
114 #define CAN_IF2_CMD_TXRQSTNDAT		0x00040000	// Transmission Request Bit
115 #define CAN_IF2_CMD_CLRINTPND		0x00080000	// Clear Interrupt Pending Bit
116 #define CAN_IF2_CMD_CONTROL		    0x00100000	// Access Control Bits
117 #define CAN_IF2_CMD_ARB			    0x00200000	// Access Arbitration Bits
118 #define CAN_IF2_CMD_MASK			0x00400000	// Access Mask Bits
119 #define CAN_IF2_CMD_WR_RD			0x00800000	// Write and Read
120 
121 #ifdef __cplusplus
122 }
123 #endif /* extern "C" */
124 
125 #endif   // - end of F2837xD_CAN_DEFINES_H
126 
127 //
128 // End of file
129 //
130