1 //########################################################################### 2 // 3 // FILE: F2837xD_EPwm_defines.h 4 // 5 // TITLE: #defines used in EPwm examples 6 // 7 //########################################################################### 8 // $TI Release: F2837xD Support Library v3.05.00.00 $ 9 // $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ 10 // $Copyright: 11 // Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ 12 // 13 // Redistribution and use in source and binary forms, with or without 14 // modification, are permitted provided that the following conditions 15 // are met: 16 // 17 // Redistributions of source code must retain the above copyright 18 // notice, this list of conditions and the following disclaimer. 19 // 20 // Redistributions in binary form must reproduce the above copyright 21 // notice, this list of conditions and the following disclaimer in the 22 // documentation and/or other materials provided with the 23 // distribution. 24 // 25 // Neither the name of Texas Instruments Incorporated nor the names of 26 // its contributors may be used to endorse or promote products derived 27 // from this software without specific prior written permission. 28 // 29 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 // $ 41 //########################################################################### 42 43 #ifndef F2837xD_EPWM_DEFINES_H 44 #define F2837xD_EPWM_DEFINES_H 45 46 #ifdef __cplusplus 47 extern "C" { 48 #endif 49 50 // 51 // Defines 52 // 53 54 // 55 // TBCTL (Time-Base Control) 56 // 57 58 // 59 // CTRMODE bits 60 // 61 #define TB_COUNT_UP 0x0 62 #define TB_COUNT_DOWN 0x1 63 #define TB_COUNT_UPDOWN 0x2 64 #define TB_FREEZE 0x3 65 66 // 67 // PHSEN bit 68 // 69 #define TB_DISABLE 0x0 70 #define TB_ENABLE 0x1 71 72 // 73 // PRDLD bit 74 // 75 #define TB_SHADOW 0x0 76 #define TB_IMMEDIATE 0x1 77 78 // 79 // SYNCOSEL bits 80 // 81 #define TB_SYNC_IN 0x0 82 #define TB_CTR_ZERO 0x1 83 #define TB_CTR_CMPB 0x2 84 #define TB_SYNC_DISABLE 0x3 85 86 // 87 // HSPCLKDIV and CLKDIV bits 88 // 89 #define TB_DIV1 0x0 90 #define TB_DIV2 0x1 91 #define TB_DIV4 0x2 92 93 // 94 // PHSDIR bit 95 // 96 #define TB_DOWN 0x0 97 #define TB_UP 0x1 98 99 // 100 // CMPCTL (Compare Control) 101 // 102 103 // 104 // LOADAMODE and LOADBMODE bits 105 // 106 #define CC_CTR_ZERO 0x0 107 #define CC_CTR_PRD 0x1 108 #define CC_CTR_ZERO_PRD 0x2 109 #define CC_LD_DISABLE 0x3 110 111 // 112 // SHDWAMODE and SHDWBMODE bits 113 // 114 #define CC_SHADOW 0x0 115 #define CC_IMMEDIATE 0x1 116 117 // 118 // AQCTLA and AQCTLB (Action Qualifier Control) 119 // 120 121 // 122 // ZRO, PRD, CAU, CAD, CBU, CBD bits 123 // 124 #define AQ_NO_ACTION 0x0 125 #define AQ_CLEAR 0x1 126 #define AQ_SET 0x2 127 #define AQ_TOGGLE 0x3 128 129 // 130 // DBCTL (Dead-Band Control) 131 // 132 133 // 134 // OUT MODE bits 135 // 136 #define DB_DISABLE 0x0 137 #define DBB_ENABLE 0x1 138 #define DBA_ENABLE 0x2 139 #define DB_FULL_ENABLE 0x3 140 141 // 142 // POLSEL bits 143 // 144 #define DB_ACTV_HI 0x0 145 #define DB_ACTV_LOC 0x1 146 #define DB_ACTV_HIC 0x2 147 #define DB_ACTV_LO 0x3 148 149 // 150 // IN MODE 151 // 152 #define DBA_ALL 0x0 153 #define DBB_RED_DBA_FED 0x1 154 #define DBA_RED_DBB_FED 0x2 155 #define DBB_ALL 0x3 156 157 // 158 // CHPCTL (chopper control) 159 // 160 161 // 162 // CHPEN bit 163 // 164 #define CHP_DISABLE 0x0 165 #define CHP_ENABLE 0x1 166 167 // 168 // CHPFREQ bits 169 // 170 #define CHP_DIV1 0x0 171 #define CHP_DIV2 0x1 172 #define CHP_DIV3 0x2 173 #define CHP_DIV4 0x3 174 #define CHP_DIV5 0x4 175 #define CHP_DIV6 0x5 176 #define CHP_DIV7 0x6 177 #define CHP_DIV8 0x7 178 179 // 180 // CHPDUTY bits 181 // 182 #define CHP1_8TH 0x0 183 #define CHP2_8TH 0x1 184 #define CHP3_8TH 0x2 185 #define CHP4_8TH 0x3 186 #define CHP5_8TH 0x4 187 #define CHP6_8TH 0x5 188 #define CHP7_8TH 0x6 189 190 // 191 // TZSEL (Trip Zone Select) 192 // 193 194 // 195 // CBCn and OSHTn bits 196 // 197 #define TZ_DISABLE 0x0 198 #define TZ_ENABLE 0x1 199 200 // 201 // TZCTL (Trip Zone Control) 202 // 203 204 // 205 // TZA and TZB bits 206 // 207 #define TZ_HIZ 0x0 208 #define TZ_FORCE_HI 0x1 209 #define TZ_FORCE_LO 0x2 210 #define TZ_NO_CHANGE 0x3 211 212 // 213 // TZDCSEL (Trip Zone Digital Compare) 214 // 215 216 // 217 // DCAEVT1, DCAEVT2, DCBEVT1, DCBEVT2 bits 218 // 219 #define TZ_EVT_DISABLE 0x0 220 #define TZ_DCAH_LOW 0x1 221 #define TZ_DCAH_HI 0x2 222 #define TZ_DCAL_LOW 0x3 223 #define TZ_DCAL_HI 0x4 224 #define TZ_DCAL_HI_DCAH_LOW 0x5 225 226 #define TZ_DCBH_LOW 0x1 227 #define TZ_DCBH_HI 0x2 228 #define TZ_DCBL_LOW 0x3 229 #define TZ_DCBL_HI 0x4 230 #define TZ_DCBL_HI_DCBH_LOW 0x5 231 232 // 233 // ETSEL (Event Trigger Select) 234 // 235 #define ET_DCAEVT1SOC 0x0 236 #define ET_CTR_ZERO 0x1 237 #define ET_CTR_PRD 0x2 238 #define ET_CTR_PRDZERO 0x3 239 #define ET_CTRU_CMPA 0x4 240 #define ET_CTRD_CMPA 0x5 241 #define ET_CTRU_CMPB 0x6 242 #define ET_CTRD_CMPB 0x7 243 244 // 245 // ETPS (Event Trigger Pre-scale) 246 // 247 248 // 249 // INTPRD, SOCAPRD, SOCBPRD bits 250 // 251 #define ET_DISABLE 0x0 252 #define ET_1ST 0x1 253 #define ET_2ND 0x2 254 #define ET_3RD 0x3 255 256 // 257 // HRPWM (High Resolution PWM) 258 // 259 260 // 261 // HRCNFG 262 // 263 #define HR_DISABLE 0x0 264 #define HR_REP 0x1 265 #define HR_FEP 0x2 266 #define HR_BEP 0x3 267 268 #define HR_CMP 0x0 269 #define HR_PHS 0x1 270 271 #define HR_CTR_ZERO 0x0 272 #define HR_CTR_PRD 0x1 273 #define HR_CTR_ZERO_PRD 0x2 274 275 #define HR_NORM_B 0x0 276 #define HR_INVERT_B 0x1 277 278 // 279 // DC (Digital Compare) 280 // 281 282 // 283 // DCTRIPSEL 284 // 285 #define DC_TZ1 0x0 286 #define DC_TZ2 0x1 287 #define DC_TZ3 0x2 288 #define DC_TRIPIN1 0x0 289 #define DC_TRIPIN2 0x1 290 #define DC_TRIPIN3 0x2 291 #define DC_TRIPIN4 0x3 292 #define DC_TRIPIN5 0x4 293 #define DC_TRIPIN6 0x5 294 #define DC_TRIPIN7 0x6 295 #define DC_TRIPIN8 0x7 296 #define DC_TRIPIN9 0x8 297 #define DC_TRIPIN10 0x9 298 #define DC_TRIPIN11 0xA 299 #define DC_TRIPIN12 0xB 300 // Reserved 0xC 301 #define DC_TRIPIN14 0xD 302 #define DC_TRIPIN15 0xE 303 #define DC_COMBINATION 0xF 304 305 // 306 // DCFCTL 307 // 308 #define DC_SRC_DCAEVT1 0x0 309 #define DC_SRC_DCAEVT2 0x1 310 #define DC_SRC_DCBEVT1 0x2 311 #define DC_SRC_DCBEVT2 0x3 312 313 #define DC_PULSESEL_PRD 0x0 314 #define DC_PULSESEL_ZERO 0x1 315 #define DC_PULSESEL_ZERO_PRD 0x2 316 317 #define DC_BLANK_DISABLE 0x0 318 #define DC_BLANK_ENABLE 0x1 319 320 #define DC_BLANK_NOTINV 0x0 321 #define DC_BLANK_INV 0x1 322 323 // 324 //DCACTL/DCBCTL 325 // 326 #define DC_EVT1 0x0 327 #define DC_EVT2 0x0 328 #define DC_EVT_FLT 0x1 329 #define DC_EVT_SYNC 0x0 330 #define DC_EVT_ASYNC 0x1 331 #define DC_SOC_DISABLE 0x0 332 #define DC_SOC_ENABLE 0x1 333 334 #ifdef __cplusplus 335 } 336 #endif /* extern "C" */ 337 338 #endif // - end of F2837xD_EPWM_DEFINES_H 339 340 // 341 // End of file 342 // 343