1 //########################################################################### 2 // 3 // FILE: F2837xD_Emif_defines.h 4 // 5 // TITLE: #defines used in EMIF examples 6 // 7 //########################################################################### 8 // $TI Release: F2837xD Support Library v3.05.00.00 $ 9 // $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ 10 // $Copyright: 11 // Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ 12 // 13 // Redistribution and use in source and binary forms, with or without 14 // modification, are permitted provided that the following conditions 15 // are met: 16 // 17 // Redistributions of source code must retain the above copyright 18 // notice, this list of conditions and the following disclaimer. 19 // 20 // Redistributions in binary form must reproduce the above copyright 21 // notice, this list of conditions and the following disclaimer in the 22 // documentation and/or other materials provided with the 23 // distribution. 24 // 25 // Neither the name of Texas Instruments Incorporated nor the names of 26 // its contributors may be used to endorse or promote products derived 27 // from this software without specific prior written permission. 28 // 29 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 // $ 41 //########################################################################### 42 43 #ifndef F2837xD_EMIF_DEFINES_H 44 #define F2837xD_EMIF_DEFINES_H 45 46 #ifdef __cplusplus 47 extern "C" { 48 #endif 49 50 // 51 // Defines 52 // 53 54 // 55 //cpu1 to cpu2 message for handshaking 56 // 57 #define CPU1_CPU2_MSG 0x3fd00 58 59 // 60 //cpu2_to_cpu1 message ram for handshaking 61 // 62 #define CPU2_CPU1_MSG 0x3fb00 63 64 #define MSEL_EMIF1_CPU1 0x93A5CE71 65 #define MSEL_EMIF1_CPU2 0x93A5CE72 66 #define MSEL_DEF_3 0x93A5CE73 67 #define MSEL_DEF_0 0x93A5CE70 68 #define MSEL_DEF_1 0x93A5CE71 69 #define MSEL_DEF_2 0x93A5CE72 70 71 // 72 //soft reset bit register 73 // 74 #define EMIF_SOFT_PRES_REG 0x5D084 75 76 // 77 //Device capability/EMIF customization register 78 // 79 #define EMIF_DEV_DC_REG 0x5D014 80 81 // 82 // Values for ASYNC_CSx_CR Registers 83 // 84 #define EMIF_ASYNC_ASIZE_8 0x0 85 #define EMIF_ASYNC_ASIZE_16 0x1 86 #define EMIF_ASYNC_ASIZE_32 0x2 87 88 #define EMIF_ASYNC_TA_1 0x0 89 #define EMIF_ASYNC_TA_2 0x4 90 #define EMIF_ASYNC_TA_3 0x8 91 #define EMIF_ASYNC_TA_4 0xC 92 93 #define EMIF_ASYNC_RHOLD_1 0x00 94 #define EMIF_ASYNC_RHOLD_2 0x10 95 #define EMIF_ASYNC_RHOLD_3 0x20 96 #define EMIF_ASYNC_RHOLD_4 0x30 97 #define EMIF_ASYNC_RHOLD_5 0x40 98 #define EMIF_ASYNC_RHOLD_6 0x50 99 #define EMIF_ASYNC_RHOLD_7 0x60 100 #define EMIF_ASYNC_RHOLD_8 0x70 101 102 #define EMIF_ASYNC_RSTROBE_1 0x0000 103 #define EMIF_ASYNC_RSTROBE_2 0x0080 104 #define EMIF_ASYNC_RSTROBE_3 0x0100 105 #define EMIF_ASYNC_RSTROBE_4 0x0180 106 #define EMIF_ASYNC_RSTROBE_5 0x0200 107 #define EMIF_ASYNC_RSTROBE_6 0x0280 108 #define EMIF_ASYNC_RSTROBE_7 0x0300 109 #define EMIF_ASYNC_RSTROBE_8 0x0380 110 #define EMIF_ASYNC_RSTROBE_9 0x0400 111 #define EMIF_ASYNC_RSTROBE_10 0x0480 112 #define EMIF_ASYNC_RSTROBE_11 0x0500 113 #define EMIF_ASYNC_RSTROBE_12 0x0580 114 #define EMIF_ASYNC_RSTROBE_13 0x0600 115 #define EMIF_ASYNC_RSTROBE_14 0x0680 116 #define EMIF_ASYNC_RSTROBE_15 0x0700 117 #define EMIF_ASYNC_RSTROBE_16 0x0780 118 #define EMIF_ASYNC_RSTROBE_17 0x0800 119 #define EMIF_ASYNC_RSTROBE_18 0x0880 120 #define EMIF_ASYNC_RSTROBE_19 0x0900 121 #define EMIF_ASYNC_RSTROBE_20 0x0980 122 #define EMIF_ASYNC_RSTROBE_21 0x0A00 123 #define EMIF_ASYNC_RSTROBE_22 0x0A80 124 #define EMIF_ASYNC_RSTROBE_23 0x0B00 125 #define EMIF_ASYNC_RSTROBE_24 0x0B80 126 #define EMIF_ASYNC_RSTROBE_25 0x0C00 127 #define EMIF_ASYNC_RSTROBE_26 0x0C80 128 #define EMIF_ASYNC_RSTROBE_27 0x0D00 129 #define EMIF_ASYNC_RSTROBE_28 0x0D80 130 #define EMIF_ASYNC_RSTROBE_29 0x0E00 131 #define EMIF_ASYNC_RSTROBE_30 0x0E80 132 #define EMIF_ASYNC_RSTROBE_31 0x0F00 133 #define EMIF_ASYNC_RSTROBE_32 0x0F80 134 #define EMIF_ASYNC_RSTROBE_33 0x1000 135 #define EMIF_ASYNC_RSTROBE_34 0x1080 136 #define EMIF_ASYNC_RSTROBE_35 0x1100 137 #define EMIF_ASYNC_RSTROBE_36 0x1180 138 #define EMIF_ASYNC_RSTROBE_37 0x1200 139 #define EMIF_ASYNC_RSTROBE_38 0x1280 140 #define EMIF_ASYNC_RSTROBE_39 0x1300 141 #define EMIF_ASYNC_RSTROBE_40 0x1380 142 #define EMIF_ASYNC_RSTROBE_41 0x1400 143 #define EMIF_ASYNC_RSTROBE_42 0x1480 144 #define EMIF_ASYNC_RSTROBE_43 0x1500 145 #define EMIF_ASYNC_RSTROBE_44 0x1580 146 #define EMIF_ASYNC_RSTROBE_45 0x1600 147 #define EMIF_ASYNC_RSTROBE_46 0x1680 148 #define EMIF_ASYNC_RSTROBE_47 0x1700 149 #define EMIF_ASYNC_RSTROBE_48 0x1780 150 #define EMIF_ASYNC_RSTROBE_49 0x1800 151 #define EMIF_ASYNC_RSTROBE_50 0x1880 152 #define EMIF_ASYNC_RSTROBE_51 0x1900 153 #define EMIF_ASYNC_RSTROBE_52 0x1980 154 #define EMIF_ASYNC_RSTROBE_53 0x1A00 155 #define EMIF_ASYNC_RSTROBE_54 0x1A80 156 #define EMIF_ASYNC_RSTROBE_55 0x1B00 157 #define EMIF_ASYNC_RSTROBE_56 0x1B80 158 #define EMIF_ASYNC_RSTROBE_57 0x1C00 159 #define EMIF_ASYNC_RSTROBE_58 0x1C80 160 #define EMIF_ASYNC_RSTROBE_59 0x1D00 161 #define EMIF_ASYNC_RSTROBE_60 0x1D80 162 #define EMIF_ASYNC_RSTROBE_61 0x1E00 163 #define EMIF_ASYNC_RSTROBE_62 0x1E80 164 #define EMIF_ASYNC_RSTROBE_63 0x1F00 165 #define EMIF_ASYNC_RSTROBE_64 0x1F80 166 167 #define EMIF_ASYNC_RSETUP_1 0x0000 168 #define EMIF_ASYNC_RSETUP_2 0x2000 169 #define EMIF_ASYNC_RSETUP_3 0x4000 170 #define EMIF_ASYNC_RSETUP_4 0x6000 171 #define EMIF_ASYNC_RSETUP_5 0x8000 172 #define EMIF_ASYNC_RSETUP_6 0xA000 173 #define EMIF_ASYNC_RSETUP_7 0xC000 174 #define EMIF_ASYNC_RSETUP_8 0xE000 175 #define EMIF_ASYNC_RSETUP_9 0x10000 176 #define EMIF_ASYNC_RSETUP_10 0x12000 177 #define EMIF_ASYNC_RSETUP_11 0x14000 178 #define EMIF_ASYNC_RSETUP_12 0x16000 179 #define EMIF_ASYNC_RSETUP_13 0x18000 180 #define EMIF_ASYNC_RSETUP_14 0x1A000 181 #define EMIF_ASYNC_RSETUP_15 0x1C000 182 #define EMIF_ASYNC_RSETUP_16 0x1E000 183 184 #define EMIF_ASYNC_WHOLD_1 0x00000 185 #define EMIF_ASYNC_WHOLD_2 0x20000 186 #define EMIF_ASYNC_WHOLD_3 0x40000 187 #define EMIF_ASYNC_WHOLD_4 0x60000 188 #define EMIF_ASYNC_WHOLD_5 0x80000 189 #define EMIF_ASYNC_WHOLD_6 0xA0000 190 #define EMIF_ASYNC_WHOLD_7 0xC0000 191 #define EMIF_ASYNC_WHOLD_8 0xE0000 192 193 #define EMIF_ASYNC_WSTROBE_1 0x0000000 194 #define EMIF_ASYNC_WSTROBE_2 0x0100000 195 #define EMIF_ASYNC_WSTROBE_3 0x0200000 196 #define EMIF_ASYNC_WSTROBE_4 0x0300000 197 #define EMIF_ASYNC_WSTROBE_5 0x0400000 198 #define EMIF_ASYNC_WSTROBE_6 0x0500000 199 #define EMIF_ASYNC_WSTROBE_7 0x0600000 200 #define EMIF_ASYNC_WSTROBE_8 0x0700000 201 #define EMIF_ASYNC_WSTROBE_9 0x0800000 202 #define EMIF_ASYNC_WSTROBE_10 0x0900000 203 #define EMIF_ASYNC_WSTROBE_11 0x0A00000 204 #define EMIF_ASYNC_WSTROBE_12 0x0B00000 205 #define EMIF_ASYNC_WSTROBE_13 0x0C00000 206 #define EMIF_ASYNC_WSTROBE_14 0x0D00000 207 #define EMIF_ASYNC_WSTROBE_15 0x0E00000 208 #define EMIF_ASYNC_WSTROBE_16 0x0F00000 209 #define EMIF_ASYNC_WSTROBE_17 0x1000000 210 #define EMIF_ASYNC_WSTROBE_18 0x1100000 211 #define EMIF_ASYNC_WSTROBE_19 0x1200000 212 #define EMIF_ASYNC_WSTROBE_20 0x1300000 213 #define EMIF_ASYNC_WSTROBE_21 0x1400000 214 #define EMIF_ASYNC_WSTROBE_22 0x1500000 215 #define EMIF_ASYNC_WSTROBE_23 0x1600000 216 #define EMIF_ASYNC_WSTROBE_24 0x1700000 217 #define EMIF_ASYNC_WSTROBE_25 0x1800000 218 #define EMIF_ASYNC_WSTROBE_26 0x1900000 219 #define EMIF_ASYNC_WSTROBE_27 0x1A00000 220 #define EMIF_ASYNC_WSTROBE_28 0x1B00000 221 #define EMIF_ASYNC_WSTROBE_29 0x1C00000 222 #define EMIF_ASYNC_WSTROBE_30 0x1D00000 223 #define EMIF_ASYNC_WSTROBE_31 0x1E00000 224 #define EMIF_ASYNC_WSTROBE_32 0x1F00000 225 #define EMIF_ASYNC_WSTROBE_33 0x2000000 226 #define EMIF_ASYNC_WSTROBE_34 0x2100000 227 #define EMIF_ASYNC_WSTROBE_35 0x2200000 228 #define EMIF_ASYNC_WSTROBE_36 0x2300000 229 #define EMIF_ASYNC_WSTROBE_37 0x2400000 230 #define EMIF_ASYNC_WSTROBE_38 0x2500000 231 #define EMIF_ASYNC_WSTROBE_39 0x2600000 232 #define EMIF_ASYNC_WSTROBE_40 0x2700000 233 #define EMIF_ASYNC_WSTROBE_41 0x2800000 234 #define EMIF_ASYNC_WSTROBE_42 0x2900000 235 #define EMIF_ASYNC_WSTROBE_43 0x2A00000 236 #define EMIF_ASYNC_WSTROBE_44 0x2B00000 237 #define EMIF_ASYNC_WSTROBE_45 0x2C00000 238 #define EMIF_ASYNC_WSTROBE_46 0x2D00000 239 #define EMIF_ASYNC_WSTROBE_47 0x2E00000 240 #define EMIF_ASYNC_WSTROBE_48 0x2F00000 241 #define EMIF_ASYNC_WSTROBE_49 0x3000000 242 #define EMIF_ASYNC_WSTROBE_50 0x3100000 243 #define EMIF_ASYNC_WSTROBE_51 0x3200000 244 #define EMIF_ASYNC_WSTROBE_52 0x3300000 245 #define EMIF_ASYNC_WSTROBE_53 0x3400000 246 #define EMIF_ASYNC_WSTROBE_54 0x3500000 247 #define EMIF_ASYNC_WSTROBE_55 0x3600000 248 #define EMIF_ASYNC_WSTROBE_56 0x3700000 249 #define EMIF_ASYNC_WSTROBE_57 0x3800000 250 #define EMIF_ASYNC_WSTROBE_58 0x3900000 251 #define EMIF_ASYNC_WSTROBE_59 0x3A00000 252 #define EMIF_ASYNC_WSTROBE_60 0x3B00000 253 #define EMIF_ASYNC_WSTROBE_61 0x3C00000 254 #define EMIF_ASYNC_WSTROBE_62 0x3D00000 255 #define EMIF_ASYNC_WSTROBE_63 0x3E00000 256 #define EMIF_ASYNC_WSTROBE_64 0x3F00000 257 258 #define EMIF_ASYNC_WSETUP_1 0x00000000 259 #define EMIF_ASYNC_WSETUP_2 0x04000000 260 #define EMIF_ASYNC_WSETUP_3 0x08000000 261 #define EMIF_ASYNC_WSETUP_4 0x0C000000 262 #define EMIF_ASYNC_WSETUP_5 0x10000000 263 #define EMIF_ASYNC_WSETUP_6 0x14000000 264 #define EMIF_ASYNC_WSETUP_7 0x18000000 265 #define EMIF_ASYNC_WSETUP_8 0x1C000000 266 #define EMIF_ASYNC_WSETUP_9 0x20000000 267 #define EMIF_ASYNC_WSETUP_10 0x24000000 268 #define EMIF_ASYNC_WSETUP_11 0x28000000 269 #define EMIF_ASYNC_WSETUP_12 0x2C000000 270 #define EMIF_ASYNC_WSETUP_13 0x30000000 271 #define EMIF_ASYNC_WSETUP_14 0x34000000 272 #define EMIF_ASYNC_WSETUP_15 0x38000000 273 #define EMIF_ASYNC_WSETUP_16 0x3C000000 274 275 #define EMIF_ASYNC_EW_DISABLE 0x00000000 276 #define EMIF_ASYNC_EW_ENABLE 0x40000000 277 278 #define EMIF_ASYNC_SS_DISABLE 0x00000000 279 #define EMIF_ASYNC_SS_ENABLE 0x80000000 280 281 // 282 // Values for ASYNC_WCCR Register 283 // 284 #define EMIF_ASYNC_WCCR_WP_LOW 0x00000000 285 #define EMIF_ASYNC_WCCR_WP_HIGH 0x01000000 286 287 // 288 // Read mask for the registers which has reserved bits. 289 // 290 #define ASYNC_WCCR_RDMASK 0xF0FF00FF 291 #define SDRAM_CR_RDMASK 0xE3FF7F7F 292 #define SDRAM_RCR_RDMASK 0x00071FFF 293 #define SDRAM_TR_RDMASK 0xFF77FF70 294 #define SDR_EXT_TMNG_RDMASK 0x1F 295 #define INT_RAW_RDMASK 0x3F 296 #define INT_MASK_RDMASK 0x3F 297 #define IO_CTRL_RDMASK_RDMASK 0xFFFF 298 #define IO_STAT_RDMASK_RDMASK 0xF 299 #define NAND_FLASH_CTRL_RDMASK 0x3F3F 300 #define NAND_FLASH_STAT_RDMASK 0x30F0F 301 #define IODFT_TLECR_REG_RDMASK 0xFFFF 302 #define IODFT_TLGCR_REG_RDMASK 0x71FF 303 #define IODFT_TLAMR_REG_RDMASK 0x0FFFFFFF 304 #define IODFT_TLDCMR_REG_RDMASK 0x3fff3f07 305 #define MODEL_REL_NUM_REG_RDMASK 0xFF 306 #define NAND_FLASH_4BIT_ECCLR_RDMASK 0x3F 307 #define NAND_FLASH_4BIT_ECCx_RDMASK 0x03ff03ff 308 #define NAND_FLASH_ERR_ADDRx_RDMASK 0x03ff03ff 309 #define NAND_FLASH_ERR_VALx_RDMASK 0x03ff03ff 310 311 #ifdef __cplusplus 312 } 313 #endif /* extern "C" */ 314 315 #endif // - end of F2837xD_EMIF_DEFINES_H 316 317 // 318 // End of file 319 // 320