1 //###########################################################################
2 //
3 // FILE: F2837xD_Spi.c
4 //
5 // TITLE: F2837xD SPI Initialization & Support Functions.
6 //
7 //###########################################################################
8 // $TI Release: F2837xD Support Library v3.05.00.00 $
9 // $Release Date: Tue Jun 26 03:15:23 CDT 2018 $
10 // $Copyright:
11 // Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/
12 //
13 // Redistribution and use in source and binary forms, with or without
14 // modification, are permitted provided that the following conditions
15 // are met:
16 //
17 // Redistributions of source code must retain the above copyright
18 // notice, this list of conditions and the following disclaimer.
19 //
20 // Redistributions in binary form must reproduce the above copyright
21 // notice, this list of conditions and the following disclaimer in the
22 // documentation and/or other materials provided with the
23 // distribution.
24 //
25 // Neither the name of Texas Instruments Incorporated nor the names of
26 // its contributors may be used to endorse or promote products derived
27 // from this software without specific prior written permission.
28 //
29 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 // $
41 //###########################################################################
42
43 //
44 // Included Files
45 //
46 #include "F2837xD_device.h"
47 #include "F2837xD_Examples.h"
48
49 //
50 // Calculate BRR: 7-bit baud rate register value
51 // SPI CLK freq = 500 kHz
52 // LSPCLK freq = CPU freq / 4 (by default)
53 // BRR = (LSPCLK freq / SPI CLK freq) - 1
54 //
55 #if CPU_FRQ_200MHZ
56 #define SPI_BRR ((200E6 / 4) / 500E3) - 1
57 #endif
58
59 #if CPU_FRQ_150MHZ
60 #define SPI_BRR ((150E6 / 4) / 500E3) - 1
61 #endif
62
63 #if CPU_FRQ_120MHZ
64 #define SPI_BRR ((120E6 / 4) / 500E3) - 1
65 #endif
66
67 //
68 // InitSPI - This function initializes the SPI to a known state
69 //
InitSpi(void)70 void InitSpi(void)
71 {
72 // Initialize SPI-A
73
74 // Set reset low before configuration changes
75 // Clock polarity (0 == rising, 1 == falling)
76 // 16-bit character
77 // Enable loop-back
78 SpiaRegs.SPICCR.bit.SPISWRESET = 0;
79 SpiaRegs.SPICCR.bit.CLKPOLARITY = 0;
80 SpiaRegs.SPICCR.bit.SPICHAR = (16-1);
81 SpiaRegs.SPICCR.bit.SPILBK = 1;
82
83 // Enable master (0 == slave, 1 == master)
84 // Enable transmission (Talk)
85 // Clock phase (0 == normal, 1 == delayed)
86 // SPI interrupts are disabled
87 SpiaRegs.SPICTL.bit.MASTER_SLAVE = 1;
88 SpiaRegs.SPICTL.bit.TALK = 1;
89 SpiaRegs.SPICTL.bit.CLK_PHASE = 0;
90 SpiaRegs.SPICTL.bit.SPIINTENA = 0;
91
92 // Set the baud rate
93 SpiaRegs.SPIBRR.bit.SPI_BIT_RATE = SPI_BRR;
94
95 // Set FREE bit
96 // Halting on a breakpoint will not halt the SPI
97 SpiaRegs.SPIPRI.bit.FREE = 1;
98
99 // Release the SPI from reset
100 SpiaRegs.SPICCR.bit.SPISWRESET = 1;
101 }
102
103 //
104 // InitSpiGpio - This function initializes GPIO pins to function as SPI pins.
105 // Each GPIO pin can be configured as a GPIO pin or up to 3
106 // different peripheral functional pins. By default all pins come
107 // up as GPIO inputs after reset.
108 //
109 // Caution:
110 // For each SPI peripheral
111 // Only one GPIO pin should be enabled for SPISOMO operation.
112 // Only one GPIO pin should be enabled for SPISOMI operation.
113 // Only one GPIO pin should be enabled for SPICLK operation.
114 // Only one GPIO pin should be enabled for SPISTE operation.
115 // Comment out other unwanted lines.
116 //
InitSpiGpio()117 void InitSpiGpio()
118 {
119 InitSpiaGpio();
120 }
121
122 //
123 // InitSpiaGpio - Initialize SPIA GPIOs
124 //
InitSpiaGpio()125 void InitSpiaGpio()
126 {
127 EALLOW;
128
129 //
130 // Enable internal pull-up for the selected pins
131 //
132 // Pull-ups can be enabled or disabled by the user.
133 // This will enable the pullups for the specified pins.
134 // Comment out other unwanted lines.
135 //
136 GpioCtrlRegs.GPAPUD.bit.GPIO16 = 0; // Enable pull-up on GPIO16 (SPISIMOA)
137 // GpioCtrlRegs.GPAPUD.bit.GPIO5 = 0; // Enable pull-up on GPIO5 (SPISIMOA)
138 GpioCtrlRegs.GPAPUD.bit.GPIO17 = 0; // Enable pull-up on GPIO17 (SPISOMIA)
139 // GpioCtrlRegs.GPAPUD.bit.GPIO3 = 0; // Enable pull-up on GPIO3 (SPISOMIA)
140 GpioCtrlRegs.GPAPUD.bit.GPIO18 = 0; // Enable pull-up on GPIO18 (SPICLKA)
141 GpioCtrlRegs.GPAPUD.bit.GPIO19 = 0; // Enable pull-up on GPIO19 (SPISTEA)
142
143 //
144 // Set qualification for selected pins to asynch only
145 //
146 // This will select asynch (no qualification) for the selected pins.
147 // Comment out other unwanted lines.
148 //
149 GpioCtrlRegs.GPAQSEL2.bit.GPIO16 = 3; // Asynch input GPIO16 (SPISIMOA)
150 // GpioCtrlRegs.GPAQSEL1.bit.GPIO5 = 3; // Asynch input GPIO5 (SPISIMOA)
151 GpioCtrlRegs.GPAQSEL2.bit.GPIO17 = 3; // Asynch input GPIO17 (SPISOMIA)
152 // GpioCtrlRegs.GPAQSEL1.bit.GPIO3 = 3; // Asynch input GPIO3 (SPISOMIA)
153 GpioCtrlRegs.GPAQSEL2.bit.GPIO18 = 3; // Asynch input GPIO18 (SPICLKA)
154 GpioCtrlRegs.GPAQSEL2.bit.GPIO19 = 3; // Asynch input GPIO19 (SPISTEA)
155
156 //
157 //Configure SPI-A pins using GPIO regs
158 //
159 // This specifies which of the possible GPIO pins will be SPI functional
160 // pins.
161 // Comment out other unwanted lines.
162 //
163 GpioCtrlRegs.GPAMUX2.bit.GPIO16 = 1; // Configure GPIO16 as SPISIMOA
164 // GpioCtrlRegs.GPAMUX1.bit.GPIO5 = 2; // Configure GPIO5 as SPISIMOA
165 GpioCtrlRegs.GPAMUX2.bit.GPIO17 = 1; // Configure GPIO17 as SPISOMIA
166 // GpioCtrlRegs.GPAMUX1.bit.GPIO3 = 2; // Configure GPIO3 as SPISOMIA
167 GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 1; // Configure GPIO18 as SPICLKA
168 GpioCtrlRegs.GPAMUX2.bit.GPIO19 = 1; // Configure GPIO19 as SPISTEA
169
170 EDIS;
171 }
172
173 //
174 // End of file
175 //
176