1 //########################################################################### 2 // 3 // FILE: F2837xD_cla.h 4 // 5 // TITLE: CLA Register Definitions. 6 // 7 //########################################################################### 8 // $TI Release: F2837xD Support Library v3.05.00.00 $ 9 // $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ 10 // $Copyright: 11 // Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ 12 // 13 // Redistribution and use in source and binary forms, with or without 14 // modification, are permitted provided that the following conditions 15 // are met: 16 // 17 // Redistributions of source code must retain the above copyright 18 // notice, this list of conditions and the following disclaimer. 19 // 20 // Redistributions in binary form must reproduce the above copyright 21 // notice, this list of conditions and the following disclaimer in the 22 // documentation and/or other materials provided with the 23 // distribution. 24 // 25 // Neither the name of Texas Instruments Incorporated nor the names of 26 // its contributors may be used to endorse or promote products derived 27 // from this software without specific prior written permission. 28 // 29 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 // $ 41 //########################################################################### 42 43 #ifndef __F2837xD_CLA_H__ 44 #define __F2837xD_CLA_H__ 45 46 #ifdef __cplusplus 47 extern "C" { 48 #endif 49 50 51 //--------------------------------------------------------------------------- 52 // CLA Individual Register Bit Definitions: 53 54 struct MCTL_BITS { // bits description 55 Uint16 HARDRESET:1; // 0 Hard Reset 56 Uint16 SOFTRESET:1; // 1 Soft Reset 57 Uint16 IACKE:1; // 2 IACK enable 58 Uint16 rsvd1:13; // 15:3 Reserved 59 }; 60 61 union MCTL_REG { 62 Uint16 all; 63 struct MCTL_BITS bit; 64 }; 65 66 struct MIFR_BITS { // bits description 67 Uint16 INT1:1; // 0 Task 1 Interrupt Flag 68 Uint16 INT2:1; // 1 Task 2 Interrupt Flag 69 Uint16 INT3:1; // 2 Task 3 Interrupt Flag 70 Uint16 INT4:1; // 3 Task 4 Interrupt Flag 71 Uint16 INT5:1; // 4 Task 5 Interrupt Flag 72 Uint16 INT6:1; // 5 Task 6 Interrupt Flag 73 Uint16 INT7:1; // 6 Task 7 Interrupt Flag 74 Uint16 INT8:1; // 7 Task 8 Interrupt Flag 75 Uint16 rsvd1:8; // 15:8 Reserved 76 }; 77 78 union MIFR_REG { 79 Uint16 all; 80 struct MIFR_BITS bit; 81 }; 82 83 struct MIOVF_BITS { // bits description 84 Uint16 INT1:1; // 0 Task 1 Interrupt Overflow Flag 85 Uint16 INT2:1; // 1 Task 2 Interrupt Overflow Flag 86 Uint16 INT3:1; // 2 Task 3 Interrupt Overflow Flag 87 Uint16 INT4:1; // 3 Task 4 Interrupt Overflow Flag 88 Uint16 INT5:1; // 4 Task 5 Interrupt Overflow Flag 89 Uint16 INT6:1; // 5 Task 6 Interrupt Overflow Flag 90 Uint16 INT7:1; // 6 Task 7 Interrupt Overflow Flag 91 Uint16 INT8:1; // 7 Task 8 Interrupt Overflow Flag 92 Uint16 rsvd1:8; // 15:8 Reserved 93 }; 94 95 union MIOVF_REG { 96 Uint16 all; 97 struct MIOVF_BITS bit; 98 }; 99 100 struct MIFRC_BITS { // bits description 101 Uint16 INT1:1; // 0 Task 1 Interrupt Force 102 Uint16 INT2:1; // 1 Task 2 Interrupt Force 103 Uint16 INT3:1; // 2 Task 3 Interrupt Force 104 Uint16 INT4:1; // 3 Task 4 Interrupt Force 105 Uint16 INT5:1; // 4 Task 5 Interrupt Force 106 Uint16 INT6:1; // 5 Task 6 Interrupt Force 107 Uint16 INT7:1; // 6 Task 7 Interrupt Force 108 Uint16 INT8:1; // 7 Task 8 Interrupt Force 109 Uint16 rsvd1:8; // 15:8 Reserved 110 }; 111 112 union MIFRC_REG { 113 Uint16 all; 114 struct MIFRC_BITS bit; 115 }; 116 117 struct MICLR_BITS { // bits description 118 Uint16 INT1:1; // 0 Task 1 Interrupt Flag Clear 119 Uint16 INT2:1; // 1 Task 2 Interrupt Flag Clear 120 Uint16 INT3:1; // 2 Task 3 Interrupt Flag Clear 121 Uint16 INT4:1; // 3 Task 4 Interrupt Flag Clear 122 Uint16 INT5:1; // 4 Task 5 Interrupt Flag Clear 123 Uint16 INT6:1; // 5 Task 6 Interrupt Flag Clear 124 Uint16 INT7:1; // 6 Task 7 Interrupt Flag Clear 125 Uint16 INT8:1; // 7 Task 8 Interrupt Flag Clear 126 Uint16 rsvd1:8; // 15:8 Reserved 127 }; 128 129 union MICLR_REG { 130 Uint16 all; 131 struct MICLR_BITS bit; 132 }; 133 134 struct MICLROVF_BITS { // bits description 135 Uint16 INT1:1; // 0 Task 1 Interrupt Overflow Flag Clear 136 Uint16 INT2:1; // 1 Task 2 Interrupt Overflow Flag Clear 137 Uint16 INT3:1; // 2 Task 3 Interrupt Overflow Flag Clear 138 Uint16 INT4:1; // 3 Task 4 Interrupt Overflow Flag Clear 139 Uint16 INT5:1; // 4 Task 5 Interrupt Overflow Flag Clear 140 Uint16 INT6:1; // 5 Task 6 Interrupt Overflow Flag Clear 141 Uint16 INT7:1; // 6 Task 7 Interrupt Overflow Flag Clear 142 Uint16 INT8:1; // 7 Task 8 Interrupt Overflow Flag Clear 143 Uint16 rsvd1:8; // 15:8 Reserved 144 }; 145 146 union MICLROVF_REG { 147 Uint16 all; 148 struct MICLROVF_BITS bit; 149 }; 150 151 struct MIER_BITS { // bits description 152 Uint16 INT1:1; // 0 Task 1 Interrupt Enable 153 Uint16 INT2:1; // 1 Task 2 Interrupt Enable 154 Uint16 INT3:1; // 2 Task 3 Interrupt Enable 155 Uint16 INT4:1; // 3 Task 4 Interrupt Enable 156 Uint16 INT5:1; // 4 Task 5 Interrupt Enable 157 Uint16 INT6:1; // 5 Task 6 Interrupt Enable 158 Uint16 INT7:1; // 6 Task 7 Interrupt Enable 159 Uint16 INT8:1; // 7 Task 8 Interrupt Enable 160 Uint16 rsvd1:8; // 15:8 Reserved 161 }; 162 163 union MIER_REG { 164 Uint16 all; 165 struct MIER_BITS bit; 166 }; 167 168 struct MIRUN_BITS { // bits description 169 Uint16 INT1:1; // 0 Task 1 Run Status 170 Uint16 INT2:1; // 1 Task 2 Run Status 171 Uint16 INT3:1; // 2 Task 3 Run Status 172 Uint16 INT4:1; // 3 Task 4 Run Status 173 Uint16 INT5:1; // 4 Task 5 Run Status 174 Uint16 INT6:1; // 5 Task 6 Run Status 175 Uint16 INT7:1; // 6 Task 7 Run Status 176 Uint16 INT8:1; // 7 Task 8 Run Status 177 Uint16 rsvd1:8; // 15:8 Reserved 178 }; 179 180 union MIRUN_REG { 181 Uint16 all; 182 struct MIRUN_BITS bit; 183 }; 184 185 struct _MSTF_BITS { // bits description 186 Uint16 LVF:1; // 0 Latched Overflow Flag 187 Uint16 LUF:1; // 1 Latched Underflow Flag 188 Uint16 NF:1; // 2 Negative Float Flag 189 Uint16 ZF:1; // 3 Zero Float Flag 190 Uint16 rsvd1:2; // 5:4 Reserved 191 Uint16 TF:1; // 6 Test Flag 192 Uint16 rsvd2:2; // 8:7 Reserved 193 Uint16 RNDF32:1; // 9 Round 32-bit Floating-Point Mode 194 Uint16 rsvd3:1; // 10 Reserved 195 Uint16 MEALLOW:1; // 11 MEALLOW Status 196 Uint32 _RPC:16; // 27:12 Return PC 197 Uint16 rsvd4:4; // 31:28 Reserved 198 }; 199 200 union _MSTF_REG { 201 Uint32 all; 202 struct _MSTF_BITS bit; 203 }; 204 205 union MR_REG { 206 Uint32 i32; 207 float f32; 208 }; 209 210 struct CLA_REGS { 211 Uint16 MVECT1; // Task Interrupt Vector 212 Uint16 MVECT2; // Task Interrupt Vector 213 Uint16 MVECT3; // Task Interrupt Vector 214 Uint16 MVECT4; // Task Interrupt Vector 215 Uint16 MVECT5; // Task Interrupt Vector 216 Uint16 MVECT6; // Task Interrupt Vector 217 Uint16 MVECT7; // Task Interrupt Vector 218 Uint16 MVECT8; // Task Interrupt Vector 219 Uint16 rsvd1[8]; // Reserved 220 union MCTL_REG MCTL; // Control Register 221 Uint16 rsvd2[15]; // Reserved 222 union MIFR_REG MIFR; // Interrupt Flag Register 223 union MIOVF_REG MIOVF; // Interrupt Overflow Flag Register 224 union MIFRC_REG MIFRC; // Interrupt Force Register 225 union MICLR_REG MICLR; // Interrupt Flag Clear Register 226 union MICLROVF_REG MICLROVF; // Interrupt Overflow Flag Clear Register 227 union MIER_REG MIER; // Interrupt Enable Register 228 union MIRUN_REG MIRUN; // Interrupt Run Status Register 229 Uint16 rsvd3; // Reserved 230 Uint16 _MPC; // CLA Program Counter 231 Uint16 rsvd4; // Reserved 232 Uint16 _MAR0; // CLA Auxiliary Register 0 233 Uint16 _MAR1; // CLA Auxiliary Register 1 234 Uint16 rsvd5[2]; // Reserved 235 union _MSTF_REG _MSTF; // CLA Floating-Point Status Register 236 union MR_REG _MR0; // CLA Floating-Point Result Register 0 237 Uint16 rsvd6[2]; // Reserved 238 union MR_REG _MR1; // CLA Floating-Point Result Register 1 239 Uint16 rsvd7[2]; // Reserved 240 union MR_REG _MR2; // CLA Floating-Point Result Register 2 241 Uint16 rsvd8[2]; // Reserved 242 union MR_REG _MR3; // CLA Floating-Point Result Register 3 243 }; 244 245 struct SOFTINTEN_BITS { // bits description 246 Uint16 TASK1:1; // 0 Task 1 Software Interrupt Enable 247 Uint16 TASK2:1; // 1 Task 2 Software Interrupt Enable 248 Uint16 TASK3:1; // 2 Task 3 Software Interrupt Enable 249 Uint16 TASK4:1; // 3 Task 4 Software Interrupt Enable 250 Uint16 TASK5:1; // 4 Task 5 Software Interrupt Enable 251 Uint16 TASK6:1; // 5 Task 6 Software Interrupt Enable 252 Uint16 TASK7:1; // 6 Task 7 Software Interrupt Enable 253 Uint16 TASK8:1; // 7 Task 8 Software Interrupt Enable 254 Uint16 rsvd1:8; // 15:8 Reserved 255 Uint16 rsvd2:16; // 31:16 Reserved 256 }; 257 258 union SOFTINTEN_REG { 259 Uint32 all; 260 struct SOFTINTEN_BITS bit; 261 }; 262 263 struct SOFTINTFRC_BITS { // bits description 264 Uint16 TASK1:1; // 0 Task 1 Software Interrupt Force 265 Uint16 TASK2:1; // 1 Task 2 Software Interrupt Force 266 Uint16 TASK3:1; // 2 Task 3 Software Interrupt Force 267 Uint16 TASK4:1; // 3 Task 4 Software Interrupt Force 268 Uint16 TASK5:1; // 4 Task 5 Software Interrupt Force 269 Uint16 TASK6:1; // 5 Task 6 Software Interrupt Force 270 Uint16 TASK7:1; // 6 Task 7 Software Interrupt Force 271 Uint16 TASK8:1; // 7 Task 8 Software Interrupt Force 272 Uint16 rsvd1:8; // 15:8 Reserved 273 Uint16 rsvd2:16; // 31:16 Reserved 274 }; 275 276 union SOFTINTFRC_REG { 277 Uint32 all; 278 struct SOFTINTFRC_BITS bit; 279 }; 280 281 struct CLA_SOFTINT_REGS { 282 union SOFTINTEN_REG SOFTINTEN; // CLA Software Interrupt Enable Register 283 union SOFTINTFRC_REG SOFTINTFRC; // CLA Software Interrupt Force Register 284 }; 285 286 //--------------------------------------------------------------------------- 287 // CLA External References & Function Declarations: 288 // 289 #ifdef CPU1 290 extern volatile struct CLA_SOFTINT_REGS Cla1SoftIntRegs; 291 extern volatile struct CLA_REGS Cla1Regs; 292 #endif 293 #ifdef CPU2 294 extern volatile struct CLA_SOFTINT_REGS Cla1SoftIntRegs; 295 extern volatile struct CLA_REGS Cla1Regs; 296 #endif 297 #ifdef __cplusplus 298 } 299 #endif /* extern "C" */ 300 301 #endif 302 303 //=========================================================================== 304 // End of file. 305 //=========================================================================== 306