1 //########################################################################### 2 // 3 // FILE: F2837xD_ecap.h 4 // 5 // TITLE: ECAP Register Definitions. 6 // 7 //########################################################################### 8 // $TI Release: F2837xD Support Library v3.05.00.00 $ 9 // $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ 10 // $Copyright: 11 // Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ 12 // 13 // Redistribution and use in source and binary forms, with or without 14 // modification, are permitted provided that the following conditions 15 // are met: 16 // 17 // Redistributions of source code must retain the above copyright 18 // notice, this list of conditions and the following disclaimer. 19 // 20 // Redistributions in binary form must reproduce the above copyright 21 // notice, this list of conditions and the following disclaimer in the 22 // documentation and/or other materials provided with the 23 // distribution. 24 // 25 // Neither the name of Texas Instruments Incorporated nor the names of 26 // its contributors may be used to endorse or promote products derived 27 // from this software without specific prior written permission. 28 // 29 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 // $ 41 //########################################################################### 42 43 #ifndef __F2837xD_ECAP_H__ 44 #define __F2837xD_ECAP_H__ 45 46 #ifdef __cplusplus 47 extern "C" { 48 #endif 49 50 51 //--------------------------------------------------------------------------- 52 // ECAP Individual Register Bit Definitions: 53 54 struct ECCTL1_BITS { // bits description 55 Uint16 CAP1POL:1; // 0 Capture Event 1 Polarity select 56 Uint16 CTRRST1:1; // 1 Counter Reset on Capture Event 1 57 Uint16 CAP2POL:1; // 2 Capture Event 2 Polarity select 58 Uint16 CTRRST2:1; // 3 Counter Reset on Capture Event 2 59 Uint16 CAP3POL:1; // 4 Capture Event 3 Polarity select 60 Uint16 CTRRST3:1; // 5 Counter Reset on Capture Event 3 61 Uint16 CAP4POL:1; // 6 Capture Event 4 Polarity select 62 Uint16 CTRRST4:1; // 7 Counter Reset on Capture Event 4 63 Uint16 CAPLDEN:1; // 8 Enable Loading CAP1-4 regs on a Cap Event 64 Uint16 PRESCALE:5; // 13:9 Event Filter prescale select 65 Uint16 FREE_SOFT:2; // 15:14 Emulation mode 66 }; 67 68 union ECCTL1_REG { 69 Uint16 all; 70 struct ECCTL1_BITS bit; 71 }; 72 73 struct ECCTL2_BITS { // bits description 74 Uint16 CONT_ONESHT:1; // 0 Continuous or one-shot 75 Uint16 STOP_WRAP:2; // 2:1 Stop value for one-shot, Wrap for continuous 76 Uint16 REARM:1; // 3 One-shot re-arm 77 Uint16 TSCTRSTOP:1; // 4 TSCNT counter stop 78 Uint16 SYNCI_EN:1; // 5 Counter sync-in select 79 Uint16 SYNCO_SEL:2; // 7:6 Sync-out mode 80 Uint16 SWSYNC:1; // 8 SW forced counter sync 81 Uint16 CAP_APWM:1; // 9 CAP/APWM operating mode select 82 Uint16 APWMPOL:1; // 10 APWM output polarity select 83 Uint16 rsvd1:5; // 15:11 Reserved 84 }; 85 86 union ECCTL2_REG { 87 Uint16 all; 88 struct ECCTL2_BITS bit; 89 }; 90 91 struct ECEINT_BITS { // bits description 92 Uint16 rsvd1:1; // 0 Reserved 93 Uint16 CEVT1:1; // 1 Capture Event 1 Interrupt Enable 94 Uint16 CEVT2:1; // 2 Capture Event 2 Interrupt Enable 95 Uint16 CEVT3:1; // 3 Capture Event 3 Interrupt Enable 96 Uint16 CEVT4:1; // 4 Capture Event 4 Interrupt Enable 97 Uint16 CTROVF:1; // 5 Counter Overflow Interrupt Enable 98 Uint16 CTR_EQ_PRD:1; // 6 Period Equal Interrupt Enable 99 Uint16 CTR_EQ_CMP:1; // 7 Compare Equal Interrupt Enable 100 Uint16 rsvd2:8; // 15:8 Reserved 101 }; 102 103 union ECEINT_REG { 104 Uint16 all; 105 struct ECEINT_BITS bit; 106 }; 107 108 struct ECFLG_BITS { // bits description 109 Uint16 INT:1; // 0 Global Flag 110 Uint16 CEVT1:1; // 1 Capture Event 1 Interrupt Flag 111 Uint16 CEVT2:1; // 2 Capture Event 2 Interrupt Flag 112 Uint16 CEVT3:1; // 3 Capture Event 3 Interrupt Flag 113 Uint16 CEVT4:1; // 4 Capture Event 4 Interrupt Flag 114 Uint16 CTROVF:1; // 5 Counter Overflow Interrupt Flag 115 Uint16 CTR_PRD:1; // 6 Period Equal Interrupt Flag 116 Uint16 CTR_CMP:1; // 7 Compare Equal Interrupt Flag 117 Uint16 rsvd1:8; // 15:8 Reserved 118 }; 119 120 union ECFLG_REG { 121 Uint16 all; 122 struct ECFLG_BITS bit; 123 }; 124 125 struct ECCLR_BITS { // bits description 126 Uint16 INT:1; // 0 ECAP Global Interrupt Status Clear 127 Uint16 CEVT1:1; // 1 Capture Event 1 Status Clear 128 Uint16 CEVT2:1; // 2 Capture Event 2 Status Clear 129 Uint16 CEVT3:1; // 3 Capture Event 3 Status Clear 130 Uint16 CEVT4:1; // 4 Capture Event 4 Status Clear 131 Uint16 CTROVF:1; // 5 Counter Overflow Status Clear 132 Uint16 CTR_PRD:1; // 6 Period Equal Status Clear 133 Uint16 CTR_CMP:1; // 7 Compare Equal Status Clear 134 Uint16 rsvd1:8; // 15:8 Reserved 135 }; 136 137 union ECCLR_REG { 138 Uint16 all; 139 struct ECCLR_BITS bit; 140 }; 141 142 struct ECFRC_BITS { // bits description 143 Uint16 rsvd1:1; // 0 Reserved 144 Uint16 CEVT1:1; // 1 Capture Event 1 Force Interrupt 145 Uint16 CEVT2:1; // 2 Capture Event 2 Force Interrupt 146 Uint16 CEVT3:1; // 3 Capture Event 3 Force Interrupt 147 Uint16 CEVT4:1; // 4 Capture Event 4 Force Interrupt 148 Uint16 CTROVF:1; // 5 Counter Overflow Force Interrupt 149 Uint16 CTR_PRD:1; // 6 Period Equal Force Interrupt 150 Uint16 CTR_CMP:1; // 7 Compare Equal Force Interrupt 151 Uint16 rsvd2:8; // 15:8 Reserved 152 }; 153 154 union ECFRC_REG { 155 Uint16 all; 156 struct ECFRC_BITS bit; 157 }; 158 159 struct ECAP_REGS { 160 Uint32 TSCTR; // Time-Stamp Counter 161 Uint32 CTRPHS; // Counter Phase Offset Value Register 162 Uint32 CAP1; // Capture 1 Register 163 Uint32 CAP2; // Capture 2 Register 164 Uint32 CAP3; // Capture 3 Register 165 Uint32 CAP4; // Capture 4 Register 166 Uint16 rsvd1[8]; // Reserved 167 union ECCTL1_REG ECCTL1; // Capture Control Register 1 168 union ECCTL2_REG ECCTL2; // Capture Control Register 2 169 union ECEINT_REG ECEINT; // Capture Interrupt Enable Register 170 union ECFLG_REG ECFLG; // Capture Interrupt Flag Register 171 union ECCLR_REG ECCLR; // Capture Interrupt Clear Register 172 union ECFRC_REG ECFRC; // Capture Interrupt Force Register 173 Uint16 rsvd2[6]; // Reserved 174 }; 175 176 //--------------------------------------------------------------------------- 177 // ECAP External References & Function Declarations: 178 // 179 #ifdef CPU1 180 extern volatile struct ECAP_REGS ECap1Regs; 181 extern volatile struct ECAP_REGS ECap2Regs; 182 extern volatile struct ECAP_REGS ECap3Regs; 183 extern volatile struct ECAP_REGS ECap4Regs; 184 extern volatile struct ECAP_REGS ECap5Regs; 185 extern volatile struct ECAP_REGS ECap6Regs; 186 #endif 187 #ifdef CPU2 188 extern volatile struct ECAP_REGS ECap1Regs; 189 extern volatile struct ECAP_REGS ECap2Regs; 190 extern volatile struct ECAP_REGS ECap3Regs; 191 extern volatile struct ECAP_REGS ECap4Regs; 192 extern volatile struct ECAP_REGS ECap5Regs; 193 extern volatile struct ECAP_REGS ECap6Regs; 194 #endif 195 #ifdef __cplusplus 196 } 197 #endif /* extern "C" */ 198 199 #endif 200 201 //=========================================================================== 202 // End of file. 203 //=========================================================================== 204