1 //########################################################################### 2 // 3 // FILE: F2837xD_emif.h 4 // 5 // TITLE: EMIF Register Definitions. 6 // 7 //########################################################################### 8 // $TI Release: F2837xD Support Library v3.05.00.00 $ 9 // $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ 10 // $Copyright: 11 // Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ 12 // 13 // Redistribution and use in source and binary forms, with or without 14 // modification, are permitted provided that the following conditions 15 // are met: 16 // 17 // Redistributions of source code must retain the above copyright 18 // notice, this list of conditions and the following disclaimer. 19 // 20 // Redistributions in binary form must reproduce the above copyright 21 // notice, this list of conditions and the following disclaimer in the 22 // documentation and/or other materials provided with the 23 // distribution. 24 // 25 // Neither the name of Texas Instruments Incorporated nor the names of 26 // its contributors may be used to endorse or promote products derived 27 // from this software without specific prior written permission. 28 // 29 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 // $ 41 //########################################################################### 42 43 #ifndef __F2837xD_EMIF_H__ 44 #define __F2837xD_EMIF_H__ 45 46 #ifdef __cplusplus 47 extern "C" { 48 #endif 49 50 51 //--------------------------------------------------------------------------- 52 // EMIF Individual Register Bit Definitions: 53 54 struct RCSR_BITS { // bits description 55 Uint16 MINOR_REVISION:8; // 7:0 Minor Revision. 56 Uint16 MAJOR_REVISION:8; // 15:8 Major Revision. 57 Uint16 MODULE_ID:14; // 29:16 EMIF module ID. 58 Uint16 FR:1; // 30 EMIF is running in full rate or half rate. 59 Uint16 BE:1; // 31 EMIF endian mode. 60 }; 61 62 union RCSR_REG { 63 Uint32 all; 64 struct RCSR_BITS bit; 65 }; 66 67 struct ASYNC_WCCR_BITS { // bits description 68 Uint16 MAX_EXT_WAIT:8; // 7:0 Maximum Extended Wait cycles. 69 Uint16 rsvd1:8; // 15:8 Reserved 70 Uint16 rsvd2:2; // 17:16 Reserved 71 Uint16 rsvd3:2; // 19:18 Reserved 72 Uint16 rsvd4:2; // 21:20 Reserved 73 Uint16 rsvd5:2; // 23:22 Reserved 74 Uint16 rsvd6:4; // 27:24 Reserved 75 Uint16 WP0:1; // 28 Polarity for EMxWAIT. 76 Uint16 rsvd7:1; // 29 Reserved 77 Uint16 rsvd8:1; // 30 Reserved 78 Uint16 rsvd9:1; // 31 Reserved 79 }; 80 81 union ASYNC_WCCR_REG { 82 Uint32 all; 83 struct ASYNC_WCCR_BITS bit; 84 }; 85 86 struct SDRAM_CR_BITS { // bits description 87 Uint16 PAGESIGE:3; // 2:0 Page Size. 88 Uint16 rsvd1:1; // 3 Reserved 89 Uint16 IBANK:3; // 6:4 Internal Bank setup of SDRAM devices. 90 Uint16 rsvd2:1; // 7 Reserved 91 Uint16 BIT_11_9_LOCK:1; // 8 Bits 11 to 9 are writable only if this bit is set. 92 Uint16 CL:3; // 11:9 CAS Latency. 93 Uint16 rsvd3:1; // 12 Reserved 94 Uint16 rsvd4:1; // 13 Reserved 95 Uint16 NM:1; // 14 Narrow Mode. 96 Uint16 rsvd5:1; // 15 Reserved 97 Uint16 rsvd6:1; // 16 Reserved 98 Uint16 rsvd7:2; // 18:17 Reserved 99 Uint16 rsvd8:1; // 19 Reserved 100 Uint16 rsvd9:3; // 22:20 Reserved 101 Uint16 rsvd10:3; // 25:23 Reserved 102 Uint16 rsvd11:3; // 28:26 Reserved 103 Uint16 PDWR:1; // 29 Perform refreshes during Power Down. 104 Uint16 PD:1; // 30 Power Down. 105 Uint16 SR:1; // 31 Self Refresh. 106 }; 107 108 union SDRAM_CR_REG { 109 Uint32 all; 110 struct SDRAM_CR_BITS bit; 111 }; 112 113 struct SDRAM_RCR_BITS { // bits description 114 Uint16 REFRESH_RATE:13; // 12:0 Refresh Rate. 115 Uint16 rsvd1:3; // 15:13 Reserved 116 Uint16 rsvd2:3; // 18:16 Reserved 117 Uint16 rsvd3:13; // 31:19 Reserved 118 }; 119 120 union SDRAM_RCR_REG { 121 Uint32 all; 122 struct SDRAM_RCR_BITS bit; 123 }; 124 125 struct ASYNC_CS2_CR_BITS { // bits description 126 Uint16 ASIZE:2; // 1:0 Asynchronous Memory Size. 127 Uint16 TA:2; // 3:2 Turn Around cycles. 128 Uint16 R_HOLD:3; // 6:4 Read Strobe Hold cycles. 129 Uint16 R_STROBE:6; // 12:7 Read Strobe Duration cycles. 130 Uint32 R_SETUP:4; // 16:13 Read Strobe Setup cycles. 131 Uint16 W_HOLD:3; // 19:17 Write Strobe Hold cycles. 132 Uint16 W_STROBE:6; // 25:20 Write Strobe Duration cycles. 133 Uint16 W_SETUP:4; // 29:26 Write Strobe Setup cycles. 134 Uint16 EW:1; // 30 Extend Wait mode. 135 Uint16 SS:1; // 31 Select Strobe mode. 136 }; 137 138 union ASYNC_CS2_CR_REG { 139 Uint32 all; 140 struct ASYNC_CS2_CR_BITS bit; 141 }; 142 143 struct ASYNC_CS3_CR_BITS { // bits description 144 Uint16 ASIZE:2; // 1:0 Asynchronous Memory Size. 145 Uint16 TA:2; // 3:2 Turn Around cycles. 146 Uint16 R_HOLD:3; // 6:4 Read Strobe Hold cycles. 147 Uint16 R_STROBE:6; // 12:7 Read Strobe Duration cycles. 148 Uint32 R_SETUP:4; // 16:13 Read Strobe Setup cycles. 149 Uint16 W_HOLD:3; // 19:17 Write Strobe Hold cycles. 150 Uint16 W_STROBE:6; // 25:20 Write Strobe Duration cycles. 151 Uint16 W_SETUP:4; // 29:26 Write Strobe Setup cycles. 152 Uint16 EW:1; // 30 Extend Wait mode. 153 Uint16 SS:1; // 31 Select Strobe mode. 154 }; 155 156 union ASYNC_CS3_CR_REG { 157 Uint32 all; 158 struct ASYNC_CS3_CR_BITS bit; 159 }; 160 161 struct ASYNC_CS4_CR_BITS { // bits description 162 Uint16 ASIZE:2; // 1:0 Asynchronous Memory Size. 163 Uint16 TA:2; // 3:2 Turn Around cycles. 164 Uint16 R_HOLD:3; // 6:4 Read Strobe Hold cycles. 165 Uint16 R_STROBE:6; // 12:7 Read Strobe Duration cycles. 166 Uint32 R_SETUP:4; // 16:13 Read Strobe Setup cycles. 167 Uint16 W_HOLD:3; // 19:17 Write Strobe Hold cycles. 168 Uint16 W_STROBE:6; // 25:20 Write Strobe Duration cycles. 169 Uint16 W_SETUP:4; // 29:26 Write Strobe Setup cycles. 170 Uint16 EW:1; // 30 Extend Wait mode. 171 Uint16 SS:1; // 31 Select Strobe mode. 172 }; 173 174 union ASYNC_CS4_CR_REG { 175 Uint32 all; 176 struct ASYNC_CS4_CR_BITS bit; 177 }; 178 179 struct SDRAM_TR_BITS { // bits description 180 Uint16 rsvd1:4; // 3:0 Reserved 181 Uint16 T_RRD:3; // 6:4 Activate to Activate timing for different bank. 182 Uint16 rsvd2:1; // 7 Reserved 183 Uint16 T_RC:4; // 11:8 Activate to Activate timing . 184 Uint16 T_RAS:4; // 15:12 Activate to Precharge timing. 185 Uint16 T_WR:3; // 18:16 Last Write to Precharge timing. 186 Uint16 rsvd3:1; // 19 Reserved 187 Uint16 T_RCD:3; // 22:20 Activate to Read/Write timing. 188 Uint16 rsvd4:1; // 23 Reserved 189 Uint16 T_RP:3; // 26:24 Precharge to Activate/Refresh timing. 190 Uint16 T_RFC:5; // 31:27 Refresh/Load Mode to Refresh/Activate timing 191 }; 192 193 union SDRAM_TR_REG { 194 Uint32 all; 195 struct SDRAM_TR_BITS bit; 196 }; 197 198 struct SDR_EXT_TMNG_BITS { // bits description 199 Uint16 T_XS:5; // 4:0 Self Refresh exit to new command timing. 200 Uint16 rsvd1:11; // 15:5 Reserved 201 Uint16 rsvd2:16; // 31:16 Reserved 202 }; 203 204 union SDR_EXT_TMNG_REG { 205 Uint32 all; 206 struct SDR_EXT_TMNG_BITS bit; 207 }; 208 209 struct INT_RAW_BITS { // bits description 210 Uint16 AT:1; // 0 Asynchronous Timeout. 211 Uint16 LT:1; // 1 Line Trap. 212 Uint16 WR:4; // 5:2 Wait Rise. 213 Uint16 rsvd1:10; // 15:6 Reserved 214 Uint16 rsvd2:16; // 31:16 Reserved 215 }; 216 217 union INT_RAW_REG { 218 Uint32 all; 219 struct INT_RAW_BITS bit; 220 }; 221 222 struct INT_MSK_BITS { // bits description 223 Uint16 AT_MASKED:1; // 0 Asynchronous Timeout. 224 Uint16 LT_MASKED:1; // 1 Line Trap. 225 Uint16 WR_MASKED:4; // 5:2 Wait Rise. 226 Uint16 rsvd1:10; // 15:6 Reserved 227 Uint16 rsvd2:16; // 31:16 Reserved 228 }; 229 230 union INT_MSK_REG { 231 Uint32 all; 232 struct INT_MSK_BITS bit; 233 }; 234 235 struct INT_MSK_SET_BITS { // bits description 236 Uint16 AT_MASK_SET:1; // 0 Asynchronous Timeout. 237 Uint16 LT_MASK_SET:1; // 1 Line Trap. 238 Uint16 WR_MASK_SET:4; // 5:2 Wait Rise. 239 Uint16 rsvd1:10; // 15:6 Reserved 240 Uint16 rsvd2:16; // 31:16 Reserved 241 }; 242 243 union INT_MSK_SET_REG { 244 Uint32 all; 245 struct INT_MSK_SET_BITS bit; 246 }; 247 248 struct INT_MSK_CLR_BITS { // bits description 249 Uint16 AT_MASK_CLR:1; // 0 Asynchronous Timeout. 250 Uint16 LT_MASK_CLR:1; // 1 Line Trap. 251 Uint16 WR_MASK_CLR:4; // 5:2 Wait Rise. 252 Uint16 rsvd1:10; // 15:6 Reserved 253 Uint16 rsvd2:16; // 31:16 Reserved 254 }; 255 256 union INT_MSK_CLR_REG { 257 Uint32 all; 258 struct INT_MSK_CLR_BITS bit; 259 }; 260 261 struct EMIF_REGS { 262 union RCSR_REG RCSR; // Revision Code and Status Register 263 union ASYNC_WCCR_REG ASYNC_WCCR; // Async Wait Cycle Config Register 264 union SDRAM_CR_REG SDRAM_CR; // SDRAM (EMxCS0n) Config Register 265 union SDRAM_RCR_REG SDRAM_RCR; // SDRAM Refresh Control Register 266 union ASYNC_CS2_CR_REG ASYNC_CS2_CR; // Async 1 (EMxCS2n) Config Register 267 union ASYNC_CS3_CR_REG ASYNC_CS3_CR; // Async 2 (EMxCS3n) Config Register 268 union ASYNC_CS4_CR_REG ASYNC_CS4_CR; // Async 3 (EMxCS4n) Config Register 269 Uint16 rsvd1[2]; // Reserved 270 union SDRAM_TR_REG SDRAM_TR; // SDRAM Timing Register 271 Uint16 rsvd2[6]; // Reserved 272 Uint32 TOTAL_SDRAM_AR; // Total SDRAM Accesses Register 273 Uint32 TOTAL_SDRAM_ACTR; // Total SDRAM Activate Register 274 Uint16 rsvd3[2]; // Reserved 275 union SDR_EXT_TMNG_REG SDR_EXT_TMNG; // SDRAM SR/PD Exit Timing Register 276 union INT_RAW_REG INT_RAW; // Interrupt Raw Register 277 union INT_MSK_REG INT_MSK; // Interrupt Masked Register 278 union INT_MSK_SET_REG INT_MSK_SET; // Interrupt Mask Set Register 279 union INT_MSK_CLR_REG INT_MSK_CLR; // Interrupt Mask Clear Register 280 Uint16 rsvd4[72]; // Reserved 281 }; 282 283 //--------------------------------------------------------------------------- 284 // EMIF External References & Function Declarations: 285 // 286 #ifdef CPU1 287 extern volatile struct EMIF_REGS Emif1Regs; 288 extern volatile struct EMIF_REGS Emif2Regs; 289 #endif 290 #ifdef CPU2 291 extern volatile struct EMIF_REGS Emif1Regs; 292 extern volatile struct EMIF_REGS Emif2Regs; 293 #endif 294 #ifdef __cplusplus 295 } 296 #endif /* extern "C" */ 297 298 #endif 299 300 //=========================================================================== 301 // End of file. 302 //=========================================================================== 303