1 //########################################################################### 2 // 3 // FILE: F2837xD_sdfm.h 4 // 5 // TITLE: SDFM Register Definitions. 6 // 7 //########################################################################### 8 // $TI Release: F2837xD Support Library v3.05.00.00 $ 9 // $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ 10 // $Copyright: 11 // Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ 12 // 13 // Redistribution and use in source and binary forms, with or without 14 // modification, are permitted provided that the following conditions 15 // are met: 16 // 17 // Redistributions of source code must retain the above copyright 18 // notice, this list of conditions and the following disclaimer. 19 // 20 // Redistributions in binary form must reproduce the above copyright 21 // notice, this list of conditions and the following disclaimer in the 22 // documentation and/or other materials provided with the 23 // distribution. 24 // 25 // Neither the name of Texas Instruments Incorporated nor the names of 26 // its contributors may be used to endorse or promote products derived 27 // from this software without specific prior written permission. 28 // 29 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 // $ 41 //########################################################################### 42 43 #ifndef __F2837xD_SDFM_H__ 44 #define __F2837xD_SDFM_H__ 45 46 #ifdef __cplusplus 47 extern "C" { 48 #endif 49 50 51 //--------------------------------------------------------------------------- 52 // SDFM Individual Register Bit Definitions: 53 54 struct SDIFLG_BITS { // bits description 55 Uint16 IFH1:1; // 0 High-level Interrupt flag Filter 1 56 Uint16 IFL1:1; // 1 Low-Level Interrupt flag Filter 1 57 Uint16 IFH2:1; // 2 High-level Interrupt flag Filter 2 58 Uint16 IFL2:1; // 3 Low-Level Interrupt flag Filter 2 59 Uint16 IFH3:1; // 4 High-level Interrupt flag Filter 3 60 Uint16 IFL3:1; // 5 Low-Level Interrupt flag Filter 3 61 Uint16 IFH4:1; // 6 High-level Interrupt flag Filter 4 62 Uint16 IFL4:1; // 7 Low-Level Interrupt flag Filter 4 63 Uint16 MF1:1; // 8 Modulator Failure for Filter 1 64 Uint16 MF2:1; // 9 Modulator Failure for Filter 2 65 Uint16 MF3:1; // 10 Modulator Failure for Filter 3 66 Uint16 MF4:1; // 11 Modulator Failure for Filter 4 67 Uint16 AF1:1; // 12 Acknowledge flag for Filter 1 68 Uint16 AF2:1; // 13 Acknowledge flag for Filter 2 69 Uint16 AF3:1; // 14 Acknowledge flag for Filter 3 70 Uint16 AF4:1; // 15 Acknowledge flag for Filter 4 71 Uint16 rsvd1:15; // 30:16 Reserved 72 Uint16 MIF:1; // 31 Master Interrupt Flag 73 }; 74 75 union SDIFLG_REG { 76 Uint32 all; 77 struct SDIFLG_BITS bit; 78 }; 79 80 struct SDIFLGCLR_BITS { // bits description 81 Uint16 IFH1:1; // 0 High-level Interrupt flag Filter 1 82 Uint16 IFL1:1; // 1 Low-Level Interrupt flag Filter 1 83 Uint16 IFH2:1; // 2 High-level Interrupt flag Filter 2 84 Uint16 IFL2:1; // 3 Low-Level Interrupt flag Filter 2 85 Uint16 IFH3:1; // 4 High-level Interrupt flag Filter 3 86 Uint16 IFL3:1; // 5 Low-Level Interrupt flag Filter 3 87 Uint16 IFH4:1; // 6 High-level Interrupt flag Filter 4 88 Uint16 IFL4:1; // 7 Low-Level Interrupt flag Filter 4 89 Uint16 MF1:1; // 8 Modulator Failure for Filter 1 90 Uint16 MF2:1; // 9 Modulator Failure for Filter 2 91 Uint16 MF3:1; // 10 Modulator Failure for Filter 3 92 Uint16 MF4:1; // 11 Modulator Failure for Filter 4 93 Uint16 AF1:1; // 12 Acknowledge flag for Filter 1 94 Uint16 AF2:1; // 13 Acknowledge flag for Filter 2 95 Uint16 AF3:1; // 14 Acknowledge flag for Filter 3 96 Uint16 AF4:1; // 15 Acknowledge flag for Filter 4 97 Uint16 rsvd1:15; // 30:16 Reserved 98 Uint16 MIF:1; // 31 Master Interrupt Flag 99 }; 100 101 union SDIFLGCLR_REG { 102 Uint32 all; 103 struct SDIFLGCLR_BITS bit; 104 }; 105 106 struct SDCTL_BITS { // bits description 107 Uint16 rsvd1:13; // 12:0 Reserved 108 Uint16 MIE:1; // 13 Master Interrupt enable 109 Uint16 rsvd2:1; // 14 Reserved 110 Uint16 rsvd3:1; // 15 Reserved 111 }; 112 113 union SDCTL_REG { 114 Uint16 all; 115 struct SDCTL_BITS bit; 116 }; 117 118 struct SDMFILEN_BITS { // bits description 119 Uint16 rsvd1:4; // 3:0 Reserved 120 Uint16 rsvd2:3; // 6:4 Reserved 121 Uint16 rsvd3:2; // 8:7 Reserved 122 Uint16 rsvd4:1; // 9 Reserved 123 Uint16 rsvd5:1; // 10 Reserved 124 Uint16 MFE:1; // 11 Master Filter Enable. 125 Uint16 rsvd6:1; // 12 Reserved 126 Uint16 rsvd7:3; // 15:13 Reserved 127 }; 128 129 union SDMFILEN_REG { 130 Uint16 all; 131 struct SDMFILEN_BITS bit; 132 }; 133 134 struct SDCTLPARM1_BITS { // bits description 135 Uint16 MOD:2; // 1:0 Delta-Sigma Modulator mode 136 Uint16 rsvd1:1; // 2 Reserved 137 Uint16 rsvd2:1; // 3 Reserved 138 Uint16 rsvd3:1; // 4 Reserved 139 Uint16 rsvd4:11; // 15:5 Reserved 140 }; 141 142 union SDCTLPARM1_REG { 143 Uint16 all; 144 struct SDCTLPARM1_BITS bit; 145 }; 146 147 struct SDDFPARM1_BITS { // bits description 148 Uint16 DOSR:8; // 7:0 Data Filter Oversample Ratio= DOSR+1 149 Uint16 FEN:1; // 8 Filter Enable 150 Uint16 AE:1; // 9 Ack Enable 151 Uint16 SST:2; // 11:10 Data Filter Structure (DataFast/1/2/3) 152 Uint16 SDSYNCEN:1; // 12 Data FILTER Reset Enable 153 Uint16 rsvd1:3; // 15:13 Reserved 154 }; 155 156 union SDDFPARM1_REG { 157 Uint16 all; 158 struct SDDFPARM1_BITS bit; 159 }; 160 161 struct SDDPARM1_BITS { // bits description 162 Uint16 rsvd1:7; // 6:0 Reserved 163 Uint16 rsvd2:1; // 7 Reserved 164 Uint16 rsvd3:1; // 8 Reserved 165 Uint16 rsvd4:1; // 9 Reserved 166 Uint16 DR:1; // 10 Data Representation (0/1 = 16/32b 2's complement) 167 Uint16 SH:5; // 15:11 Shift Control (# bits to shift in 16b mode) 168 }; 169 170 union SDDPARM1_REG { 171 Uint16 all; 172 struct SDDPARM1_BITS bit; 173 }; 174 175 struct SDCMPH1_BITS { // bits description 176 Uint16 HLT:15; // 14:0 High-level threshold for the comparator filter output. 177 Uint16 rsvd1:1; // 15 Reserved 178 }; 179 180 union SDCMPH1_REG { 181 Uint16 all; 182 struct SDCMPH1_BITS bit; 183 }; 184 185 struct SDCMPL1_BITS { // bits description 186 Uint16 LLT:15; // 14:0 Low-level threshold for the comparator filter output. 187 Uint16 rsvd1:1; // 15 Reserved 188 }; 189 190 union SDCMPL1_REG { 191 Uint16 all; 192 struct SDCMPL1_BITS bit; 193 }; 194 195 struct SDCPARM1_BITS { // bits description 196 Uint16 COSR:5; // 4:0 Comparator Oversample Ratio = COSR + 1 197 Uint16 IEH:1; // 5 High-level interrupt enable 198 Uint16 IEL:1; // 6 Low-level interrupt enable 199 Uint16 CS1_CS0:2; // 8:7 Comparator filter structure (Sincfast/Sinc1/Sinc2/Sinc3 200 Uint16 MFIE:1; // 9 Modulator Failure Interrupt enable 201 Uint16 rsvd1:6; // 15:10 Reserved 202 }; 203 204 union SDCPARM1_REG { 205 Uint16 all; 206 struct SDCPARM1_BITS bit; 207 }; 208 209 struct SDDATA1_BITS { // bits description 210 Uint16 DATA16:16; // 15:0 16-bit Data in 16b mode, Lo-order 16b in 32b mode 211 Uint16 DATA32HI:16; // 31:16 Hi-order 16b in 32b mode 212 }; 213 214 union SDDATA1_REG { 215 Uint32 all; 216 struct SDDATA1_BITS bit; 217 }; 218 219 struct SDCTLPARM2_BITS { // bits description 220 Uint16 MOD:2; // 1:0 Delta-Sigma Modulator mode 221 Uint16 rsvd1:1; // 2 Reserved 222 Uint16 rsvd2:1; // 3 Reserved 223 Uint16 rsvd3:1; // 4 Reserved 224 Uint16 rsvd4:11; // 15:5 Reserved 225 }; 226 227 union SDCTLPARM2_REG { 228 Uint16 all; 229 struct SDCTLPARM2_BITS bit; 230 }; 231 232 struct SDDFPARM2_BITS { // bits description 233 Uint16 DOSR:8; // 7:0 Data Filter Oversample Ratio= DOSR+1 234 Uint16 FEN:1; // 8 Filter Enable 235 Uint16 AE:1; // 9 Ack Enable 236 Uint16 SST:2; // 11:10 Data Filter Structure (SincFast/1/2/3) 237 Uint16 SDSYNCEN:1; // 12 Data FILTER Reset Enable 238 Uint16 rsvd1:3; // 15:13 Reserved 239 }; 240 241 union SDDFPARM2_REG { 242 Uint16 all; 243 struct SDDFPARM2_BITS bit; 244 }; 245 246 struct SDDPARM2_BITS { // bits description 247 Uint16 rsvd1:7; // 6:0 Reserved 248 Uint16 rsvd2:1; // 7 Reserved 249 Uint16 rsvd3:1; // 8 Reserved 250 Uint16 rsvd4:1; // 9 Reserved 251 Uint16 DR:1; // 10 Data Representation (0/1 = 16/32b 2's complement) 252 Uint16 SH:5; // 15:11 Shift Control (# bits to shift in 16b mode) 253 }; 254 255 union SDDPARM2_REG { 256 Uint16 all; 257 struct SDDPARM2_BITS bit; 258 }; 259 260 struct SDCMPH2_BITS { // bits description 261 Uint16 HLT:15; // 14:0 High-level threshold for the comparator filter output. 262 Uint16 rsvd1:1; // 15 Reserved 263 }; 264 265 union SDCMPH2_REG { 266 Uint16 all; 267 struct SDCMPH2_BITS bit; 268 }; 269 270 struct SDCMPL2_BITS { // bits description 271 Uint16 LLT:15; // 14:0 Low-level threshold for the comparator filter output. 272 Uint16 rsvd1:1; // 15 Reserved 273 }; 274 275 union SDCMPL2_REG { 276 Uint16 all; 277 struct SDCMPL2_BITS bit; 278 }; 279 280 struct SDCPARM2_BITS { // bits description 281 Uint16 COSR:5; // 4:0 Comparator Oversample Ratio = COSR + 1 282 Uint16 IEH:1; // 5 High-level interrupt enable 283 Uint16 IEL:1; // 6 Low-level interrupt enable 284 Uint16 CS1_CS0:2; // 8:7 Comparator filter structure (Sincfast/Sinc1/Sinc2/Sinc3 285 Uint16 MFIE:1; // 9 Modulator Failure Interrupt enable 286 Uint16 rsvd1:6; // 15:10 Reserved 287 }; 288 289 union SDCPARM2_REG { 290 Uint16 all; 291 struct SDCPARM2_BITS bit; 292 }; 293 294 struct SDDATA2_BITS { // bits description 295 Uint16 DATA16:16; // 15:0 16-bit Data in 16b mode, Lo-order 16b in 32b mode 296 Uint16 DATA32HI:16; // 31:16 Hi-order 16b in 32b mode 297 }; 298 299 union SDDATA2_REG { 300 Uint32 all; 301 struct SDDATA2_BITS bit; 302 }; 303 304 struct SDCTLPARM3_BITS { // bits description 305 Uint16 MOD:2; // 1:0 Delta-Sigma Modulator mode 306 Uint16 rsvd1:1; // 2 Reserved 307 Uint16 rsvd2:1; // 3 Reserved 308 Uint16 rsvd3:1; // 4 Reserved 309 Uint16 rsvd4:11; // 15:5 Reserved 310 }; 311 312 union SDCTLPARM3_REG { 313 Uint16 all; 314 struct SDCTLPARM3_BITS bit; 315 }; 316 317 struct SDDFPARM3_BITS { // bits description 318 Uint16 DOSR:8; // 7:0 Data Filter Oversample Ratio= DOSR+1 319 Uint16 FEN:1; // 8 Filter Enable 320 Uint16 AE:1; // 9 Ack Enable 321 Uint16 SST:2; // 11:10 Data filter structure (SincFast/1/2/3) 322 Uint16 SDSYNCEN:1; // 12 Data FILTER Reset Enable 323 Uint16 rsvd1:3; // 15:13 Reserved 324 }; 325 326 union SDDFPARM3_REG { 327 Uint16 all; 328 struct SDDFPARM3_BITS bit; 329 }; 330 331 struct SDDPARM3_BITS { // bits description 332 Uint16 rsvd1:7; // 6:0 Reserved 333 Uint16 rsvd2:1; // 7 Reserved 334 Uint16 rsvd3:1; // 8 Reserved 335 Uint16 rsvd4:1; // 9 Reserved 336 Uint16 DR:1; // 10 Data Representation (0/1 = 16/32b 2's complement) 337 Uint16 SH:5; // 15:11 Shift Control (# bits to shift in 16b mode) 338 }; 339 340 union SDDPARM3_REG { 341 Uint16 all; 342 struct SDDPARM3_BITS bit; 343 }; 344 345 struct SDCMPH3_BITS { // bits description 346 Uint16 HLT:15; // 14:0 High-level threshold for the comparator filter output. 347 Uint16 rsvd1:1; // 15 Reserved 348 }; 349 350 union SDCMPH3_REG { 351 Uint16 all; 352 struct SDCMPH3_BITS bit; 353 }; 354 355 struct SDCMPL3_BITS { // bits description 356 Uint16 LLT:15; // 14:0 Low-level threshold for the comparator filter output. 357 Uint16 rsvd1:1; // 15 Reserved 358 }; 359 360 union SDCMPL3_REG { 361 Uint16 all; 362 struct SDCMPL3_BITS bit; 363 }; 364 365 struct SDCPARM3_BITS { // bits description 366 Uint16 COSR:5; // 4:0 Comparator Oversample Ratio = COSR + 1 367 Uint16 IEH:1; // 5 High-level interrupt enable 368 Uint16 IEL:1; // 6 Low-level interrupt enable 369 Uint16 CS1_CS0:2; // 8:7 Comparator filter structure (Sincfast/Sinc1/Sinc2/Sinc3 370 Uint16 MFIE:1; // 9 Modulator Failure Interrupt enable 371 Uint16 rsvd1:6; // 15:10 Reserved 372 }; 373 374 union SDCPARM3_REG { 375 Uint16 all; 376 struct SDCPARM3_BITS bit; 377 }; 378 379 struct SDDATA3_BITS { // bits description 380 Uint16 DATA16:16; // 15:0 16-bit Data in 16b mode, Lo-order 16b in 32b mode 381 Uint16 DATA32HI:16; // 31:16 Hi-order 16b in 32b mode 382 }; 383 384 union SDDATA3_REG { 385 Uint32 all; 386 struct SDDATA3_BITS bit; 387 }; 388 389 struct SDCTLPARM4_BITS { // bits description 390 Uint16 MOD:2; // 1:0 Delta-Sigma Modulator mode 391 Uint16 rsvd1:1; // 2 Reserved 392 Uint16 rsvd2:1; // 3 Reserved 393 Uint16 rsvd3:1; // 4 Reserved 394 Uint16 rsvd4:11; // 15:5 Reserved 395 }; 396 397 union SDCTLPARM4_REG { 398 Uint16 all; 399 struct SDCTLPARM4_BITS bit; 400 }; 401 402 struct SDDFPARM4_BITS { // bits description 403 Uint16 DOSR:8; // 7:0 SINC Filter Oversample Ratio= DOSR+1 404 Uint16 FEN:1; // 8 Filter Enable 405 Uint16 AE:1; // 9 Ack Enable 406 Uint16 SST:2; // 11:10 Data filter structure (SincFast/1/2/3) 407 Uint16 SDSYNCEN:1; // 12 SINC FILTER Reset Enable 408 Uint16 rsvd1:3; // 15:13 Reserved 409 }; 410 411 union SDDFPARM4_REG { 412 Uint16 all; 413 struct SDDFPARM4_BITS bit; 414 }; 415 416 struct SDDPARM4_BITS { // bits description 417 Uint16 rsvd1:7; // 6:0 Reserved 418 Uint16 rsvd2:1; // 7 Reserved 419 Uint16 rsvd3:1; // 8 Reserved 420 Uint16 rsvd4:1; // 9 Reserved 421 Uint16 DR:1; // 10 Data Representation (0/1 = 16/32b 2's complement) 422 Uint16 SH:5; // 15:11 Shift Control (# bits to shift in 16b mode) 423 }; 424 425 union SDDPARM4_REG { 426 Uint16 all; 427 struct SDDPARM4_BITS bit; 428 }; 429 430 struct SDCMPH4_BITS { // bits description 431 Uint16 HLT:15; // 14:0 High-level threshold for the comparator filter output. 432 Uint16 rsvd1:1; // 15 Reserved 433 }; 434 435 union SDCMPH4_REG { 436 Uint16 all; 437 struct SDCMPH4_BITS bit; 438 }; 439 440 struct SDCMPL4_BITS { // bits description 441 Uint16 LLT:15; // 14:0 Low-level threshold for the comparator filter output. 442 Uint16 rsvd1:1; // 15 Reserved 443 }; 444 445 union SDCMPL4_REG { 446 Uint16 all; 447 struct SDCMPL4_BITS bit; 448 }; 449 450 struct SDCPARM4_BITS { // bits description 451 Uint16 COSR:5; // 4:0 Comparator Oversample Ratio = COSR + 1 452 Uint16 IEH:1; // 5 High-level interrupt enable 453 Uint16 IEL:1; // 6 Low-level interrupt enable 454 Uint16 CS1_CS0:2; // 8:7 Comparator filter structure (Sincfast/Sinc1/Sinc2/Sinc3 455 Uint16 MFIE:1; // 9 Modulator Failure Interrupt enable 456 Uint16 rsvd1:6; // 15:10 Reserved 457 }; 458 459 union SDCPARM4_REG { 460 Uint16 all; 461 struct SDCPARM4_BITS bit; 462 }; 463 464 struct SDDATA4_BITS { // bits description 465 Uint16 DATA16:16; // 15:0 16-bit Data in 16b mode, Lo-order 16b in 32b mode 466 Uint16 DATA32HI:16; // 31:16 Hi-order 16b in 32b mode 467 }; 468 469 union SDDATA4_REG { 470 Uint32 all; 471 struct SDDATA4_BITS bit; 472 }; 473 474 struct SDFM_REGS { 475 union SDIFLG_REG SDIFLG; // Interrupt Flag Register 476 union SDIFLGCLR_REG SDIFLGCLR; // Interrupt Flag Clear Register 477 union SDCTL_REG SDCTL; // SD Control Register 478 Uint16 rsvd1; // Reserved 479 union SDMFILEN_REG SDMFILEN; // SD Master Filter Enable 480 Uint16 rsvd2[9]; // Reserved 481 union SDCTLPARM1_REG SDCTLPARM1; // Control Parameter Register for Ch1 482 union SDDFPARM1_REG SDDFPARM1; // Data Filter Parameter Register for Ch1 483 union SDDPARM1_REG SDDPARM1; // Integer Parameter Register for Ch1 484 union SDCMPH1_REG SDCMPH1; // High-level Threshold Register for Ch1 485 union SDCMPL1_REG SDCMPL1; // Low-level Threshold Register for Ch1 486 union SDCPARM1_REG SDCPARM1; // Comparator Parameter Register for Ch1 487 union SDDATA1_REG SDDATA1; // Filter Data Register (16 or 32bit) for Ch1 488 Uint16 rsvd3[8]; // Reserved 489 union SDCTLPARM2_REG SDCTLPARM2; // Control Parameter Register for Ch2 490 union SDDFPARM2_REG SDDFPARM2; // Data Filter Parameter Register for Ch2 491 union SDDPARM2_REG SDDPARM2; // Integer Parameter Register for Ch2 492 union SDCMPH2_REG SDCMPH2; // High-level Threshold Register for Ch2 493 union SDCMPL2_REG SDCMPL2; // Low-level Threshold Register for Ch2 494 union SDCPARM2_REG SDCPARM2; // Comparator Parameter Register for Ch2 495 union SDDATA2_REG SDDATA2; // Filter Data Register (16 or 32bit) for Ch2 496 Uint16 rsvd4[8]; // Reserved 497 union SDCTLPARM3_REG SDCTLPARM3; // Control Parameter Register for Ch3 498 union SDDFPARM3_REG SDDFPARM3; // Data Filter Parameter Register for Ch3 499 union SDDPARM3_REG SDDPARM3; // Integer Parameter Register for Ch3 500 union SDCMPH3_REG SDCMPH3; // High-level Threshold Register for Ch3 501 union SDCMPL3_REG SDCMPL3; // Low-level Threshold Register for Ch3 502 union SDCPARM3_REG SDCPARM3; // Comparator Parameter Register for Ch3 503 union SDDATA3_REG SDDATA3; // Filter Data Register (16 or 32bit) for Ch3 504 Uint16 rsvd5[8]; // Reserved 505 union SDCTLPARM4_REG SDCTLPARM4; // Control Parameter Register for Ch4 506 union SDDFPARM4_REG SDDFPARM4; // Data Filter Parameter Register for Ch4 507 union SDDPARM4_REG SDDPARM4; // Integer Parameter Register for Ch4 508 union SDCMPH4_REG SDCMPH4; // High-level Threshold Register for Ch4 509 union SDCMPL4_REG SDCMPL4; // Low-level Threshold Register for Ch4 510 union SDCPARM4_REG SDCPARM4; // Comparator Parameter Register for Ch4 511 union SDDATA4_REG SDDATA4; // Filter Data Register (16 or 32bit) for Ch4 512 Uint16 rsvd6[56]; // Reserved 513 }; 514 515 //--------------------------------------------------------------------------- 516 // SDFM External References & Function Declarations: 517 // 518 #ifdef CPU1 519 extern volatile struct SDFM_REGS Sdfm1Regs; 520 extern volatile struct SDFM_REGS Sdfm2Regs; 521 #endif 522 #ifdef CPU2 523 extern volatile struct SDFM_REGS Sdfm1Regs; 524 extern volatile struct SDFM_REGS Sdfm2Regs; 525 #endif 526 #ifdef __cplusplus 527 } 528 #endif /* extern "C" */ 529 530 #endif 531 532 //=========================================================================== 533 // End of file. 534 //=========================================================================== 535