1 //########################################################################### 2 // 3 // FILE: F2837xD_spi.h 4 // 5 // TITLE: SPI Register Definitions. 6 // 7 //########################################################################### 8 // $TI Release: F2837xD Support Library v3.05.00.00 $ 9 // $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ 10 // $Copyright: 11 // Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ 12 // 13 // Redistribution and use in source and binary forms, with or without 14 // modification, are permitted provided that the following conditions 15 // are met: 16 // 17 // Redistributions of source code must retain the above copyright 18 // notice, this list of conditions and the following disclaimer. 19 // 20 // Redistributions in binary form must reproduce the above copyright 21 // notice, this list of conditions and the following disclaimer in the 22 // documentation and/or other materials provided with the 23 // distribution. 24 // 25 // Neither the name of Texas Instruments Incorporated nor the names of 26 // its contributors may be used to endorse or promote products derived 27 // from this software without specific prior written permission. 28 // 29 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 // $ 41 //########################################################################### 42 43 #ifndef __F2837xD_SPI_H__ 44 #define __F2837xD_SPI_H__ 45 46 #ifdef __cplusplus 47 extern "C" { 48 #endif 49 50 51 //--------------------------------------------------------------------------- 52 // SPI Individual Register Bit Definitions: 53 54 struct SPICCR_BITS { // bits description 55 Uint16 SPICHAR:4; // 3:0 Character Length Control 56 Uint16 SPILBK:1; // 4 SPI Loopback 57 Uint16 HS_MODE:1; // 5 High Speed mode control 58 Uint16 CLKPOLARITY:1; // 6 Shift Clock Polarity 59 Uint16 SPISWRESET:1; // 7 SPI Software Reset 60 Uint16 rsvd1:8; // 15:8 Reserved 61 }; 62 63 union SPICCR_REG { 64 Uint16 all; 65 struct SPICCR_BITS bit; 66 }; 67 68 struct SPICTL_BITS { // bits description 69 Uint16 SPIINTENA:1; // 0 SPI Interupt Enable 70 Uint16 TALK:1; // 1 Master/Slave Transmit Enable 71 Uint16 MASTER_SLAVE:1; // 2 SPI Network Mode Control 72 Uint16 CLK_PHASE:1; // 3 SPI Clock Phase 73 Uint16 OVERRUNINTENA:1; // 4 Overrun Interrupt Enable 74 Uint16 rsvd1:11; // 15:5 Reserved 75 }; 76 77 union SPICTL_REG { 78 Uint16 all; 79 struct SPICTL_BITS bit; 80 }; 81 82 struct SPISTS_BITS { // bits description 83 Uint16 rsvd1:5; // 4:0 Reserved 84 Uint16 BUFFULL_FLAG:1; // 5 SPI Transmit Buffer Full Flag 85 Uint16 INT_FLAG:1; // 6 SPI Interrupt Flag 86 Uint16 OVERRUN_FLAG:1; // 7 SPI Receiver Overrun Flag 87 Uint16 rsvd2:8; // 15:8 Reserved 88 }; 89 90 union SPISTS_REG { 91 Uint16 all; 92 struct SPISTS_BITS bit; 93 }; 94 95 struct SPIBRR_BITS { // bits description 96 Uint16 SPI_BIT_RATE:7; // 6:0 SPI Bit Rate Control 97 Uint16 rsvd1:9; // 15:7 Reserved 98 }; 99 100 union SPIBRR_REG { 101 Uint16 all; 102 struct SPIBRR_BITS bit; 103 }; 104 105 struct SPIFFTX_BITS { // bits description 106 Uint16 TXFFIL:5; // 4:0 TXFIFO Interrupt Level 107 Uint16 TXFFIENA:1; // 5 TXFIFO Interrupt Enable 108 Uint16 TXFFINTCLR:1; // 6 TXFIFO Interrupt Clear 109 Uint16 TXFFINT:1; // 7 TXFIFO Interrupt Flag 110 Uint16 TXFFST:5; // 12:8 Transmit FIFO Status 111 Uint16 TXFIFO:1; // 13 TXFIFO Reset 112 Uint16 SPIFFENA:1; // 14 FIFO Enhancements Enable 113 Uint16 SPIRST:1; // 15 SPI Reset 114 }; 115 116 union SPIFFTX_REG { 117 Uint16 all; 118 struct SPIFFTX_BITS bit; 119 }; 120 121 struct SPIFFRX_BITS { // bits description 122 Uint16 RXFFIL:5; // 4:0 RXFIFO Interrupt Level 123 Uint16 RXFFIENA:1; // 5 RXFIFO Interrupt Enable 124 Uint16 RXFFINTCLR:1; // 6 RXFIFO Interupt Clear 125 Uint16 RXFFINT:1; // 7 RXFIFO Interrupt Flag 126 Uint16 RXFFST:5; // 12:8 Receive FIFO Status 127 Uint16 RXFIFORESET:1; // 13 RXFIFO Reset 128 Uint16 RXFFOVFCLR:1; // 14 Receive FIFO Overflow Clear 129 Uint16 RXFFOVF:1; // 15 Receive FIFO Overflow Flag 130 }; 131 132 union SPIFFRX_REG { 133 Uint16 all; 134 struct SPIFFRX_BITS bit; 135 }; 136 137 struct SPIFFCT_BITS { // bits description 138 Uint16 TXDLY:8; // 7:0 FIFO Transmit Delay Bits 139 Uint16 rsvd1:8; // 15:8 Reserved 140 }; 141 142 union SPIFFCT_REG { 143 Uint16 all; 144 struct SPIFFCT_BITS bit; 145 }; 146 147 struct SPIPRI_BITS { // bits description 148 Uint16 TRIWIRE:1; // 0 3-wire mode select bit 149 Uint16 STEINV:1; // 1 SPISTE inversion bit 150 Uint16 rsvd1:2; // 3:2 Reserved 151 Uint16 FREE:1; // 4 Free emulation mode 152 Uint16 SOFT:1; // 5 Soft emulation mode 153 Uint16 rsvd2:1; // 6 Reserved 154 Uint16 rsvd3:9; // 15:7 Reserved 155 }; 156 157 union SPIPRI_REG { 158 Uint16 all; 159 struct SPIPRI_BITS bit; 160 }; 161 162 struct SPI_REGS { 163 union SPICCR_REG SPICCR; // SPI Configuration Control Register 164 union SPICTL_REG SPICTL; // SPI Operation Control Register 165 union SPISTS_REG SPISTS; // SPI Status Register 166 Uint16 rsvd1; // Reserved 167 union SPIBRR_REG SPIBRR; // SPI Baud Rate Register 168 Uint16 rsvd2; // Reserved 169 Uint16 SPIRXEMU; // SPI Emulation Buffer Register 170 Uint16 SPIRXBUF; // SPI Serial Input Buffer Register 171 Uint16 SPITXBUF; // SPI Serial Output Buffer Register 172 Uint16 SPIDAT; // SPI Serial Data Register 173 union SPIFFTX_REG SPIFFTX; // SPI FIFO Transmit Register 174 union SPIFFRX_REG SPIFFRX; // SPI FIFO Receive Register 175 union SPIFFCT_REG SPIFFCT; // SPI FIFO Control Register 176 Uint16 rsvd3[2]; // Reserved 177 union SPIPRI_REG SPIPRI; // SPI Priority Control Register 178 }; 179 180 //--------------------------------------------------------------------------- 181 // SPI External References & Function Declarations: 182 // 183 #ifdef CPU1 184 extern volatile struct SPI_REGS SpiaRegs; 185 extern volatile struct SPI_REGS SpibRegs; 186 extern volatile struct SPI_REGS SpicRegs; 187 #endif 188 #ifdef CPU2 189 extern volatile struct SPI_REGS SpiaRegs; 190 extern volatile struct SPI_REGS SpibRegs; 191 extern volatile struct SPI_REGS SpicRegs; 192 #endif 193 #ifdef __cplusplus 194 } 195 #endif /* extern "C" */ 196 197 #endif 198 199 //=========================================================================== 200 // End of file. 201 //=========================================================================== 202