1 /** 2 ****************************************************************************** 3 * @file HAL_rcc.h 4 * @author IC Applications Department 5 * @version V0.8 6 * @date 2019_08_02 7 * @brief This file contains all the functions prototypes for the RCC firmware 8 * library. 9 ****************************************************************************** 10 * @copy 11 * 12 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 13 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 14 * TIME. AS A RESULT, HOLOCENE SHALL NOT BE HELD LIABLE FOR ANY 15 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 16 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 17 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 18 * 19 * <h2><center>© COPYRIGHT 2016 HOLOCENE</center></h2> 20 */ 21 22 /* Define to prevent recursive inclusion -------------------------------------*/ 23 #ifndef __HAL_RCC_H 24 #define __HAL_RCC_H 25 26 /* Includes ------------------------------------------------------------------*/ 27 #include "HAL_device.h" 28 29 /** @addtogroup StdPeriph_Driver 30 * @{ 31 */ 32 33 /** @addtogroup RCC 34 * @{ 35 */ 36 37 /** @defgroup RCC_Exported_Types 38 * @{ 39 */ 40 41 typedef struct 42 { 43 uint32_t SYSCLK_Frequency; 44 uint32_t HCLK_Frequency; 45 uint32_t PCLK1_Frequency; 46 uint32_t PCLK2_Frequency; 47 uint32_t ADCCLK_Frequency; 48 }RCC_ClocksTypeDef; 49 50 /** 51 * @} 52 */ 53 54 /** @defgroup RCC_Exported_Constants 55 * @{ 56 */ 57 58 /** @defgroup HSE_configuration 59 * @{ 60 */ 61 62 #define RCC_HSE_OFF ((uint32_t)0x00000000) 63 #define RCC_HSE_ON ((uint32_t)0x00010000) 64 #define RCC_HSE_Bypass ((uint32_t)0x00040000) 65 #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \ 66 ((HSE) == RCC_HSE_Bypass)) 67 68 /** 69 * @} 70 */ 71 72 /** @defgroup PLL_entry_clock_source 73 * @{ 74 */ 75 76 #define RCC_PLLSource_HSI_Div4 ((uint32_t)0x00000000) 77 #define RCC_PLLSource_HSE_Div2 ((uint32_t)0x00420000) 78 #define RCC_PLLSource_HSE_Div1 ((uint32_t)0x00400000) 79 #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div4) || \ 80 ((SOURCE) == RCC_PLLSource_HSE_Div1) || \ 81 ((SOURCE) == RCC_PLLSource_HSE_Div2)) 82 /** 83 * @} 84 */ 85 86 87 /** @defgroup System_clock_source 88 * @{ 89 */ 90 91 #define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000) 92 #define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001) 93 #define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002) 94 #define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \ 95 ((SOURCE) == RCC_SYSCLKSource_HSE) || \ 96 ((SOURCE) == RCC_SYSCLKSource_PLLCLK)) 97 /** 98 * @} 99 */ 100 101 /** @defgroup AHB_clock_source 102 * @{ 103 */ 104 105 #define RCC_SYSCLK_Div1 ((uint32_t)0x00000000) 106 #define RCC_SYSCLK_Div2 ((uint32_t)0x00000080) 107 #define RCC_SYSCLK_Div4 ((uint32_t)0x00000090) 108 #define RCC_SYSCLK_Div8 ((uint32_t)0x000000A0) 109 #define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0) 110 #define RCC_SYSCLK_Div64 ((uint32_t)0x000000C0) 111 #define RCC_SYSCLK_Div128 ((uint32_t)0x000000D0) 112 #define RCC_SYSCLK_Div256 ((uint32_t)0x000000E0) 113 #define RCC_SYSCLK_Div512 ((uint32_t)0x000000F0) 114 #define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \ 115 ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \ 116 ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \ 117 ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \ 118 ((HCLK) == RCC_SYSCLK_Div512)) 119 /** 120 * @} 121 */ 122 123 /** @defgroup APB1_APB2_clock_source 124 * @{ 125 */ 126 127 #define RCC_HCLK_Div1 ((uint32_t)0x00000000) 128 #define RCC_HCLK_Div2 ((uint32_t)0x00000400) 129 #define RCC_HCLK_Div4 ((uint32_t)0x00000500) 130 #define RCC_HCLK_Div8 ((uint32_t)0x00000600) 131 #define RCC_HCLK_Div16 ((uint32_t)0x00000700) 132 #define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \ 133 ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \ 134 ((PCLK) == RCC_HCLK_Div16)) 135 136 /** 137 * @} 138 */ 139 140 /** @defgroup PLL_multiplication_factor 141 * @{ 142 */ 143 144 #define RCC_PLLMul_2 ((uint32_t)0x00000000) 145 #define RCC_PLLMul_3 ((uint32_t)0x00040000) 146 #define RCC_PLLMul_4 ((uint32_t)0x00080000) 147 #define RCC_PLLMul_5 ((uint32_t)0x000C0000) 148 #define RCC_PLLMul_6 ((uint32_t)0x00100000) 149 #define RCC_PLLMul_7 ((uint32_t)0x00140000) 150 #define RCC_PLLMul_8 ((uint32_t)0x00180000) 151 #define RCC_PLLMul_9 ((uint32_t)0x001C0000) 152 #define RCC_PLLMul_10 ((uint32_t)0x00200000) 153 #define RCC_PLLMul_11 ((uint32_t)0x00240000) 154 #define RCC_PLLMul_12 ((uint32_t)0x00280000) 155 #define RCC_PLLMul_13 ((uint32_t)0x002C0000) 156 #define RCC_PLLMul_14 ((uint32_t)0x00300000) 157 #define RCC_PLLMul_15 ((uint32_t)0x00340000) 158 #define RCC_PLLMul_16 ((uint32_t)0x00380000) 159 #define RCC_PLLMul_17 ((uint32_t)0x003C0000) 160 #define RCC_PLLMul_18 ((uint32_t)0x00400000) 161 #define RCC_PLLMul_19 ((uint32_t)0x004C0000) 162 #define RCC_PLLMul_20 ((uint32_t)0x00500000) 163 #define RCC_PLLMul_21 ((uint32_t)0x00540000) 164 #define RCC_PLLMul_22 ((uint32_t)0x00580000) 165 #define RCC_PLLMul_23 ((uint32_t)0x005C0001) 166 #define RCC_PLLMul_24 ((uint32_t)0x00600002) 167 #define RCC_PLLMul_25 ((uint32_t)0x00680003) 168 #define RCC_PLLMul_26 ((uint32_t)0x006C0004) 169 #define RCC_PLLMul_27 ((uint32_t)0x00700005) 170 #define RCC_PLLMul_28 ((uint32_t)0x00780006) 171 #define RCC_PLLMul_29 ((uint32_t)0x007C0007) 172 #define RCC_PLLMul_30 ((uint32_t)0x00800008) 173 #define RCC_PLLMul_31 ((uint32_t)0x00880009) 174 #define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_2) || ((MUL) == RCC_PLLMul_3) || \ 175 ((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \ 176 ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \ 177 ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \ 178 ((MUL) == RCC_PLLMul_10) || ((MUL) == RCC_PLLMul_11) || \ 179 ((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_13) || \ 180 ((MUL) == RCC_PLLMul_14) || ((MUL) == RCC_PLLMul_15) || \ 181 ((MUL) == RCC_PLLMul_16)) 182 183 184 /** 185 * @} 186 */ 187 188 /** @defgroup RCC_Interrupt_source 189 * @{ 190 */ 191 192 #define RCC_IT_LSIRDY ((uint8_t)0x01) 193 #define RCC_IT_LSERDY ((uint8_t)0x02) 194 #define RCC_IT_HSIRDY ((uint8_t)0x04) 195 #define RCC_IT_HSERDY ((uint8_t)0x08) 196 #define RCC_IT_PLLRDY ((uint8_t)0x10) 197 #define RCC_IT_CSS ((uint8_t)0x80) 198 #define IS_RCC_IT(IT) ((((IT) & (uint8_t)0xE0) == 0x00) && ((IT) != 0x00)) 199 #define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \ 200 ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \ 201 ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS)) 202 203 #define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x60) == 0x00) && ((IT) != 0x00)) 204 /** 205 * @} 206 */ 207 208 /** @defgroup USB_clock_source 209 * @{ 210 */ 211 212 #define RCC_USBCLKSource_PLLCLK_1Div5 ((uint8_t)0x00) 213 #define RCC_USBCLKSource_PLLCLK_Div1 ((uint8_t)0x01) 214 #define IS_RCC_USBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSource_PLLCLK_1Div5) || \ 215 ((SOURCE) == RCC_USBCLKSource_PLLCLK_Div1)) 216 /** 217 * @} 218 */ 219 220 /** @defgroup ADC_clock_source 221 * @{ 222 */ 223 224 #define RCC_PCLK2_Div2 ((uint32_t)0x00000000) 225 #define RCC_PCLK2_Div4 ((uint32_t)0x00004000) 226 #define RCC_PCLK2_Div6 ((uint32_t)0x00008000) 227 #define RCC_PCLK2_Div8 ((uint32_t)0x0000C000) 228 #define IS_RCC_ADCCLK(ADCCLK) (((ADCCLK) == RCC_PCLK2_Div2) || ((ADCCLK) == RCC_PCLK2_Div4) || \ 229 ((ADCCLK) == RCC_PCLK2_Div6) || ((ADCCLK) == RCC_PCLK2_Div8)) 230 /** 231 * @} 232 */ 233 234 /** @defgroup LSE_configuration 235 * @{ 236 */ 237 238 #define RCC_LSE_OFF ((uint8_t)0x00) 239 #define RCC_LSE_ON ((uint8_t)0x01) 240 #define RCC_LSE_Bypass ((uint8_t)0x04) 241 #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \ 242 ((LSE) == RCC_LSE_Bypass)) 243 /** 244 * @} 245 */ 246 247 /** @defgroup RTC_clock_source 248 * @{ 249 */ 250 251 #define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100) 252 #define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200) 253 #define RCC_RTCCLKSource_HSE_Div128 ((uint32_t)0x00000300) 254 #define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \ 255 ((SOURCE) == RCC_RTCCLKSource_LSI) || \ 256 ((SOURCE) == RCC_RTCCLKSource_HSE_Div128)) 257 /** 258 * @} 259 */ 260 261 /** @defgroup AHB_peripheral 262 * @{ 263 */ 264 265 #define RCC_AHBPeriph_LTDC ((uint32_t)0x80000000) 266 #define RCC_AHBPeriph_DMA1 ((uint32_t)0x00200000) 267 #define RCC_AHBPeriph_DMA2 ((uint32_t)0x00400000) 268 #define RCC_AHBPeriph_SRAM ((uint32_t)0x00000004) 269 #define RCC_AHBPeriph_FLITF ((uint32_t)0x00000010) 270 #define RCC_AHBPeriph_CRC ((uint32_t)0x00000001<<12) 271 #define RCC_AHBPeriph_FSMC ((uint32_t)0x00000100) 272 #define RCC_AHBPeriph_SDIO ((uint32_t)0x00000400) 273 274 #define RCC_AHBPeriph_GPIOA ((uint32_t)0x00000001) 275 #define RCC_AHBPeriph_GPIOB ((uint32_t)0x00000002) 276 #define RCC_AHBPeriph_GPIOC ((uint32_t)0x0000004) 277 #define RCC_AHBPeriph_GPIOD ((uint32_t)0x0000008) 278 #define RCC_AHBPeriph_GPIOE ((uint32_t)0x0000010) 279 280 #define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFAA8) == 0x00) && ((PERIPH) != 0x00)) 281 /** 282 * @} 283 */ 284 285 /** @defgroup APB2_peripheral 286 * @{ 287 */ 288 289 290 291 #define RCC_APB2Periph_TIM1 ((uint32_t)0x00000001) 292 #define RCC_APB2Periph_TIM2 ((uint32_t)0x00000002) 293 294 #define RCC_APB2Periph_UART1 ((uint32_t)0x00000004) 295 #define RCC_APB2Periph_UART2 ((uint32_t)0x00000008) 296 #define RCC_APB2Periph_UART3 ((uint32_t)0x00000010) 297 #define RCC_APB2Periph_UART4 ((uint32_t)0x00000020) 298 #define RCC_APB2Periph_UART5 ((uint32_t)0x00000040) 299 #define RCC_APB2Periph_ADC1 ((uint32_t)0x00000100) 300 301 #define RCC_APB2Periph_SDIO1 ((uint32_t)0x00000800) 302 #define RCC_APB2Periph_SDIO2 ((uint32_t)0x00001000) 303 #define RCC_APB2Periph_SYSCFG ((uint32_t)0x00004000) 304 #define RCC_APB2Periph_SPI1 ((uint32_t)0x00100000) 305 #define RCC_APB2Periph_SPI2 ((uint32_t)0x00200000) 306 #define RCC_APB2Periph_SPI3 ((uint32_t)0x00400000) 307 #define RCC_APB2Periph_SPI4 ((uint32_t)0x00800000) 308 #define RCC_APB2Periph_QSPI ((uint32_t)0x01000000) 309 310 #define RCC_AHB2Periph_TK80 ((uint32_t)0x80000000) 311 312 #define RCC_APB2Periph_ALL ((uint32_t)0x0003FFFD) 313 #define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFFC0002) == 0x00) && ((PERIPH) != 0x00)) 314 /** 315 * @} 316 */ 317 318 /** @defgroup APB1_peripheral 319 * @{ 320 */ 321 322 323 #define RCC_APB1Periph_TIM3 ((uint32_t)0x00000001<<0) 324 #define RCC_APB1Periph_TIM4 ((uint32_t)0x00000001<<1) 325 #define RCC_APB1Periph_TIM5 ((uint32_t)0x00000001<<2) 326 #define RCC_APB1Periph_TIM6 ((uint32_t)0x00000001<<3) 327 #define RCC_APB1Periph_TIM7 ((uint32_t)0x00000001<<4) 328 #define RCC_APB1Periph_TIM8 ((uint32_t)0x00000001<<5) 329 #define RCC_APB1Periph_TIM9 ((uint32_t)0x00000001<<6) 330 #define RCC_APB1Periph_TIM10 ((uint32_t)0x00000001<<7) 331 332 333 334 335 #define RCC_APB1Periph_WWDG ((uint32_t)0x00000800) 336 337 #define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000) 338 339 #define RCC_APB1Periph_UART2 ((uint32_t)0x00020000) 340 341 #define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000) 342 343 #define RCC_APB1Periph_PWR ((uint32_t)0x10000000) 344 345 #define RCC_APB1Periph_CAN1 ((uint32_t)0x04000000) 346 #define RCC_APB1Periph_CAN2 ((uint32_t)0x08000000) 347 348 #define RCC_APB1Periph_USB ((uint32_t)0x10000000) 349 350 351 352 #define RCC_APB1Periph_ALL ((uint32_t)0x3AFEC83F) 353 354 #define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0xC50137C0) == 0x00) && ((PERIPH) != 0x00)) 355 /** 356 * @} 357 */ 358 359 /** @defgroup Clock_source_to_output_on_MCO_pin 360 * @{ 361 */ 362 363 #define RCC_MCO_NoClock ((uint8_t)0x00) 364 #define RCC_MCO_SYSCLK ((uint8_t)0x04) 365 #define RCC_MCO_HSI ((uint8_t)0x05) 366 #define RCC_MCO_HSE ((uint8_t)0x06) 367 #define RCC_MCO_PLLCLK_Div2 ((uint8_t)0x07) 368 #define RCC_MCO_LSI ((uint8_t)0x02) 369 #define RCC_MCO_LSE ((uint8_t)0x03) 370 #define IS_RCC_MCO(MCO) (((MCO) == RCC_MCO_NoClock) || ((MCO) == RCC_MCO_HSI) || \ 371 ((MCO) == RCC_MCO_SYSCLK) || ((MCO) == RCC_MCO_HSE) || \ 372 ((MCO) == RCC_MCO_PLLCLK_Div2)||((MCO) == RCC_MCO_LSI)||\ 373 ((MCO) == RCC_MCO_LSE)) 374 /** 375 * @} 376 */ 377 378 /** @defgroup RCC_Flag 379 * @{ 380 */ 381 382 #define RCC_FLAG_HSIRDY ((uint8_t)0x21) 383 #define RCC_FLAG_HSERDY ((uint8_t)0x31) 384 #define RCC_FLAG_PLLRDY ((uint8_t)0x39) 385 #define RCC_FLAG_LSERDY ((uint8_t)0x41) 386 #define RCC_FLAG_LSIRDY ((uint8_t)0x61) 387 #define RCC_FLAG_PINRST ((uint8_t)0x7A) 388 #define RCC_FLAG_PORRST ((uint8_t)0x7B) 389 #define RCC_FLAG_SFTRST ((uint8_t)0x7C) 390 #define RCC_FLAG_IWDGRST ((uint8_t)0x7D) 391 #define RCC_FLAG_WWDGRST ((uint8_t)0x7E) 392 #define RCC_FLAG_LPWRRST ((uint8_t)0x7F) 393 #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \ 394 ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \ 395 ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_PINRST) || \ 396 ((FLAG) == RCC_FLAG_PORRST) || ((FLAG) == RCC_FLAG_SFTRST) || \ 397 ((FLAG) == RCC_FLAG_IWDGRST)|| ((FLAG) == RCC_FLAG_WWDGRST)|| \ 398 ((FLAG) == RCC_FLAG_LPWRRST)) 399 400 #define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F) 401 /** 402 * @} 403 */ 404 405 /** 406 * @} 407 */ 408 409 /** @defgroup RCC_Exported_Macros 410 * @{ 411 */ 412 413 /** 414 * @} 415 */ 416 417 /** @defgroup RCC_Exported_Functions 418 * @{ 419 */ 420 void SystemClk_HSEInit(uint32_t PLL_DN); 421 void RCC_DeInit(void); 422 void RCC_HSEConfig(uint32_t RCC_HSE); 423 ErrorStatus RCC_WaitForHSEStartUp(void); 424 void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue); 425 void RCC_HSICmd(FunctionalState NewState); 426 void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul); 427 void RCC_PLLCmd(FunctionalState NewState); 428 void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource); 429 uint8_t RCC_GetSYSCLKSource(void); 430 void RCC_HCLKConfig(uint32_t RCC_SYSCLK); 431 void RCC_PCLK1Config(uint32_t RCC_HCLK); 432 void RCC_PCLK2Config(uint32_t RCC_HCLK); 433 void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState); 434 void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource); 435 void RCC_ADCCLKConfig(uint32_t RCC_PCLK2); 436 void RCC_LSEConfig(uint8_t RCC_LSE); 437 void RCC_LSICmd(FunctionalState NewState); 438 void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource); 439 void RCC_RTCCLKCmd(FunctionalState NewState); 440 void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks); 441 void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState); 442 void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); 443 void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); 444 void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); 445 void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); 446 void RCC_BackupResetCmd(FunctionalState NewState); 447 void RCC_ClockSecuritySystemCmd(FunctionalState NewState); 448 void RCC_MCOConfig(uint8_t RCC_MCO); 449 FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG); 450 void RCC_ClearFlag(void); 451 ITStatus RCC_GetITStatus(uint8_t RCC_IT); 452 void RCC_ClearITPendingBit(uint8_t RCC_IT); 453 void getSystemClock(u32 *sysclk); 454 #endif /* __HAL_RCC_H */ 455 /** 456 * @} 457 */ 458 459 /** 460 * @} 461 */ 462 463 /** 464 * @} 465 */ 466 467 /*-------------------------(C) COPYRIGHT 2016 HOLOCENE ----------------------*/ 468