1 /** 2 ****************************************************************************** 3 * @file HAL_spi.h 4 * @author IC Applications Department 5 * @version V0.8 6 * @date 2019_08_02 7 * @brief This file contains all the functions prototypes for the SPI firmware 8 * library. 9 ****************************************************************************** 10 * @copy 11 * 12 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 13 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 14 * TIME. AS A RESULT, HOLOCENE SHALL NOT BE HELD LIABLE FOR ANY 15 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 16 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 17 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 18 * 19 * <h2><center>© COPYRIGHT 2016 HOLOCENE</center></h2> 20 */ 21 22 /* Define to prevent recursive inclusion -------------------------------------*/ 23 #ifndef __HAL_SPI_H 24 #define __HAL_SPI_H 25 26 /* Includes ------------------------------------------------------------------*/ 27 #include "HAL_device.h" 28 29 /** @addtogroup StdPeriph_Driver 30 * @{ 31 */ 32 33 /** @addtogroup SPI 34 * @{ 35 */ 36 37 /** @defgroup SPI_Exported_Types 38 * @{ 39 */ 40 41 /** 42 * @brief SPI Init structure definition 43 */ 44 45 typedef struct 46 { 47 uint16_t SPI_Mode; 48 uint16_t SPI_DataSize; 49 uint16_t SPI_DataWidth; 50 uint16_t SPI_CPOL; 51 uint16_t SPI_CPHA; 52 uint16_t SPI_NSS; 53 uint16_t SPI_BaudRatePrescaler; 54 uint16_t SPI_FirstBit; 55 }SPI_InitTypeDef; 56 57 58 /** 59 * @} 60 */ 61 62 /** @defgroup SPI_Exported_Constants 63 * @{ 64 */ 65 66 #define IS_SPI_ALL_PERIPH(PERIPH) (((*(uint32_t*)&(PERIPH)) == SPI0_BASE) || \ 67 ((*(uint32_t*)&(PERIPH)) == SPI1_BASE)) 68 69 #define IS_SPI_2_PERIPH(PERIPH) ((*(uint32_t*)&(PERIPH)) == SPI1_BASE) 70 71 72 /** 73 * @} 74 */ 75 76 /** @defgroup SPI_master_slave_mode 77 * @{ 78 */ 79 80 #define SPI_Mode_Master ((uint16_t)0x0004) 81 #define SPI_Mode_Slave ((uint16_t)0x0000) 82 #define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \ 83 ((MODE) == SPI_Mode_Slave)) 84 /** 85 * @} 86 */ 87 88 /** @defgroup SPI_data_size 89 * @{ 90 */ 91 92 #define SPI_DataSize_32b ((uint16_t)0x0800) 93 #define SPI_DataSize_8b ((uint16_t)0x0000) 94 #define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DataSize_32b) || \ 95 ((DATASIZE) == SPI_DataSize_8b)) 96 97 /** 98 * @} 99 */ 100 101 102 /** @defgroup SPI_7bit_8bit data width 103 * @{ 104 */ 105 106 #define SPI_DataWidth_7b ((uint16_t)0x0000) 107 #define SPI_DataWidth_8b ((uint16_t)0x0008) 108 #define IS_SPI_DATAWIDRH(WIDTH) (((WIDTH) == SPI_DataWidth_7b) || \ 109 ((WIDTH) == SPI_DataWidth_8b)) 110 /** 111 * @} 112 */ 113 114 115 /** @defgroup SPI_Clock_Polarity 116 * @{ 117 */ 118 119 #define SPI_CPOL_Low ((uint16_t)0x0000) 120 #define SPI_CPOL_High ((uint16_t)0x0002) 121 #define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \ 122 ((CPOL) == SPI_CPOL_High)) 123 /** 124 * @} 125 */ 126 127 /** @defgroup SPI_Clock_Phase 128 * @{ 129 */ 130 131 #define SPI_CPHA_1Edge ((uint16_t)0x0001) 132 #define SPI_CPHA_2Edge ((uint16_t)0x0000) 133 #define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \ 134 ((CPHA) == SPI_CPHA_2Edge)) 135 /** 136 * @} 137 */ 138 139 /** @defgroup SPI_Slave_Select_management 140 * @{ 141 */ 142 143 #define SPI_NSS_Soft ((uint16_t)0x0000) 144 #define SPI_NSS_Hard ((uint16_t)0x0400) 145 #define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \ 146 ((NSS) == SPI_NSS_Hard)) 147 148 149 /** 150 * @} 151 */ 152 153 /** @defgroup SPI_NSS_internal_software_mangement 154 * @{ 155 */ 156 157 #define SPI_NSSInternalSoft_Set ((uint16_t)0x0001) 158 #define SPI_NSSInternalSoft_Reset ((uint16_t)0xFFFE) 159 #define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \ 160 ((INTERNAL) == SPI_NSSInternalSoft_Reset)) 161 /** 162 * @} 163 */ 164 165 /** 166 * @} 167 */ 168 169 /** @defgroup SPI_BaudRate_Prescaler_ 170 * @{ 171 */ 172 173 174 #define SPI_BaudRatePrescaler_2 ((uint16_t)0x0002) 175 #define SPI_BaudRatePrescaler_4 ((uint16_t)0x0004) 176 #define SPI_BaudRatePrescaler_8 ((uint16_t)0x0008) 177 #define SPI_BaudRatePrescaler_16 ((uint16_t)0x0010) 178 #define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020) 179 #define SPI_BaudRatePrescaler_64 ((uint16_t)0x0040) 180 #define SPI_BaudRatePrescaler_128 ((uint16_t)0x0080) 181 #define SPI_BaudRatePrescaler_256 ((uint16_t)0x0100) 182 #define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \ 183 ((PRESCALER) == SPI_BaudRatePrescaler_4) || \ 184 ((PRESCALER) == SPI_BaudRatePrescaler_8) || \ 185 ((PRESCALER) == SPI_BaudRatePrescaler_16) || \ 186 ((PRESCALER) == SPI_BaudRatePrescaler_32) || \ 187 ((PRESCALER) == SPI_BaudRatePrescaler_64) || \ 188 ((PRESCALER) == SPI_BaudRatePrescaler_128) || \ 189 ((PRESCALER) == SPI_BaudRatePrescaler_256)) 190 /** 191 * @} 192 */ 193 194 /** @defgroup SPI_MSB_LSB_transmission 195 * @{ 196 */ 197 198 #define SPI_FirstBit_MSB ((uint16_t)0x0000) 199 #define SPI_FirstBit_LSB ((uint16_t)0x0004) 200 #define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \ 201 ((BIT) == SPI_FirstBit_LSB)) 202 203 204 /** 205 * @} 206 */ 207 208 /** @defgroup SPI_DMA_transfer_requests 209 * @{ 210 */ 211 212 #define SPI_DMAReq_EN ((uint16_t)0x0200) 213 #define IS_SPI_DMAREQ(DMAREQ) ((DMAREQ) == SPI_DMAReq_EN) 214 215 216 /** 217 * @} 218 */ 219 220 /** @defgroup SPI TX Fifo and RX Fifo trigger level 221 * @{ 222 */ 223 #define SPI_TXTLF ((uint16_t)0x0080) 224 #define SPI_RXTLF ((uint16_t)0x0020) 225 #define IS_SPI_FIFOTRIGGER(TRIGGER) (((TRIGGER) == SPI_TXTLF) && ((TRIGGER) == SPI_RXTLF)) 226 227 228 229 230 231 232 233 /** 234 * @} 235 */ 236 237 /** @defgroup SPI_NSS_internal_software_mangement 238 * @{ 239 */ 240 241 #define SPI_CS_BIT0 ((uint16_t)0xfffe) 242 #define SPI_CS_BIT1 ((uint16_t)0xfffd) 243 #define SPI_CS_BIT2 ((uint16_t)0xfffb) 244 #define SPI_CS_BIT3 ((uint16_t)0xfff7) 245 #define SPI_CS_BIT4 ((uint16_t)0xffef) 246 #define SPI_CS_BIT5 ((uint16_t)0xffdf) 247 #define SPI_CS_BIT6 ((uint16_t)0xffbf) 248 #define SPI_CS_BIT7 ((uint16_t)0xff7f) 249 #define IS_SPI_CS(CS) (((CS) == SPI_CS_BIT0) || ((CS) == SPI_CS_BIT1)||\ 250 ((CS) == SPI_CS_BIT2) || ((CS) == SPI_CS_BIT3)||\ 251 ((CS) == SPI_CS_BIT4) || ((CS) == SPI_CS_BIT5)||\ 252 ((CS) == SPI_CS_BIT6) || ((CS) == SPI_CS_BIT7)) 253 /** 254 * @} 255 */ 256 257 258 /** @defgroup SPI_direction_transmit_receive 259 * @{ 260 */ 261 262 #define SPI_Direction_Rx ((uint16_t)0x0010) 263 #define SPI_Direction_Tx ((uint16_t)0x0008) 264 #define SPI_Disable_Tx ((uint16_t)0xfff7) 265 #define SPI_Disable_Rx ((uint16_t)0xffef) 266 #define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \ 267 ((DIRECTION) == SPI_Direction_Tx) || \ 268 ((DIRECTION) == SPI_Disable_Tx) || \ 269 ((DIRECTION) == SPI_Disable_Rx)) 270 /** 271 * @} 272 */ 273 274 /** @defgroup SPI_interrupts_definition 275 * @{ 276 */ 277 #define SPI_INT_EN ((uint16_t)0x0002) 278 279 #define SPI_IT_TX ((uint8_t)0x01) 280 #define SPI_IT_RX ((uint8_t)0x02) 281 282 #define IS_SPI_CONFIG_IT(IT) (((IT) == SPI_IT_TX) || \ 283 ((IT) == SPI_IT_RX)) 284 285 #define SPI_IT_UNDERRUN ((uint8_t)0x04) 286 #define SPI_IT_RXOVER ((uint8_t)0x08) 287 #define SPI_IT_RXMATCH ((uint8_t)0x10) 288 #define SPI_IT_RXFULL ((uint8_t)0x20) 289 #define SPI_IT_TXEPT ((uint8_t)0x40) 290 291 #define IS_SPI_GET_IT(IT) (((IT) == SPI_IT_TX) || ((IT) == SPI_IT_RX) || \ 292 ((IT) == SPI_IT_UNDERRUN) || ((IT) == SPI_IT_RXOVER) || \ 293 ((IT) == SPI_IT_RXMATCH) || ((IT) == SPI_IT_RXFULL) || \ 294 ((IT) == SPI_IT_TXEPT)) 295 /** 296 * @} 297 */ 298 299 /** @defgroup SPI_flags_definition 300 * @{ 301 */ 302 303 304 #define SPI_FLAG_RXAVL ((uint16_t)0x0002) 305 #define SPI_FLAG_TXEPT ((uint16_t)0x0001) 306 307 #define IS_SPI_GET_FLAG(FLAG) (((FLAG) == SPI_FLAG_RXAVL) || \ 308 ((FLAG) == SPI_FLAG_TXEPT)) 309 310 /** 311 * @} 312 */ 313 314 /** @defgroup SPI mode tx data transmit phase adjust set 315 *in slave mode according to txedge bit of CCTL register 316 * @{ 317 */ 318 319 320 #define SPI_SlaveAdjust_FAST ((uint16_t)0x0020) 321 #define SPI_SlaveAdjust_LOW ((uint16_t)0xffdf) 322 323 #define IS_SPI_SlaveAdjust(ADJUST) (((ADJUST) == SPI_SlaveAdjust_FAST) || \ 324 ((ADJUST) == SPI_SlaveAdjust_LOW)) 325 326 327 /** 328 * @} 329 */ 330 331 /** @defgroup SPI_Exported_Macros 332 * @{ 333 */ 334 335 /** 336 * @} 337 */ 338 339 /** @defgroup SPI_Exported_Functions 340 * @{ 341 */ 342 343 void SPI_DeInit(SPI_TypeDef* SPIx); 344 void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct); 345 void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct); 346 void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState); 347 void SPI_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_IT, FunctionalState NewState); 348 void SPI_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_DMAReq, FunctionalState NewState); 349 void SPI_FifoTrigger(SPI_TypeDef* SPIx, uint16_t SPI_FifoTriggerValue, FunctionalState NewState); 350 void SPI_SendData(SPI_TypeDef* SPIx, uint16_t Data); 351 uint16_t SPI_ReceiveData(SPI_TypeDef* SPIx); 352 void SPI_CSInternalSelected(SPI_TypeDef* SPIx, uint16_t SPI_CSInternalSelected,FunctionalState NewState); 353 void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft); 354 void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize); 355 void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction); 356 FlagStatus SPI_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_FLAG); 357 ITStatus SPI_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_IT); 358 void SPI_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_IT); 359 void SPI_RxBytes(SPI_TypeDef* SPIx, uint16_t Number); 360 void SPI_SlaveAdjust(SPI_TypeDef* SPIx, uint16_t AdjustValue); 361 #endif /*__HAL_SPI_H */ 362 /** 363 * @} 364 */ 365 366 /** 367 * @} 368 */ 369 370 /** 371 * @} 372 */ 373 374 /*-------------------------(C) COPYRIGHT 2016 HOLOCENE ----------------------*/ 375