1 /** 2 ****************************************************************************** 3 * @file HAL_tim.h 4 * @author IC Applications Department 5 * @version V0.8 6 * @date 2019_08_02 7 * @brief This file contains all the functions prototypes for the TIM firmware 8 * library. 9 ****************************************************************************** 10 * @copy 11 * 12 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 13 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 14 * TIME. AS A RESULT, HOLOCENE SHALL NOT BE HELD LIABLE FOR ANY 15 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 16 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 17 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 18 * 19 * <h2><center>© COPYRIGHT 2016 HOLOCENE</center></h2> 20 */ 21 22 /* Define to prevent recursive inclusion -------------------------------------*/ 23 #ifndef __HAL_TIM_H 24 #define __HAL_TIM_H 25 26 #ifdef __cplusplus 27 extern "C" { 28 #endif 29 30 /* Includes ------------------------------------------------------------------*/ 31 #include "HAL_device.h" 32 33 /** @addtogroup StdPeriph_Driver 34 * @{ 35 */ 36 37 /** @addtogroup TIM 38 * @{ 39 */ 40 41 /* Exported types ------------------------------------------------------------*/ 42 43 /** 44 * @brief TIM Time Base Init structure definition 45 * @note This sturcture is used with all TIMx. 46 */ 47 48 typedef struct 49 { 50 uint16_t TIM_Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. 51 This parameter can be a number between 0x0000 and 0xFFFF */ 52 53 uint16_t TIM_CounterMode; /*!< Specifies the counter mode. 54 This parameter can be a value of @ref TIM_Counter_Mode */ 55 56 uint32_t TIM_Period; 57 /*!< Auto-Reload Register at the next update event. 58 This parameter must be a number between 0x0000 and 0xFFFF. */ 59 60 uint16_t TIM_ClockDivision; /*!< Specifies the clock division. 61 This parameter can be a value of @ref TIM_Clock_Division_CKD */ 62 63 uint8_t TIM_RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter 64 reaches zero, an update event is generated and counting restarts 65 from the RCR value (N). 66 This means in PWM mode that (N+1) corresponds to: 67 - the number of PWM periods in edge-aligned mode 68 - the number of half PWM period in center-aligned mode 69 This parameter must be a number between 0x00 and 0xFF. 70 @note This parameter is valid only for TIM1. */ 71 } TIM_TimeBaseInitTypeDef; 72 73 /** 74 * @brief TIM Output Compare Init structure definition 75 */ 76 77 typedef struct 78 { 79 uint16_t TIM_OCMode; /*!< Specifies the TIM mode. 80 This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ 81 82 uint16_t TIM_OutputState; /*!< Specifies the TIM Output Compare state. 83 This parameter can be a value of @ref TIM_Output_Compare_state */ 84 85 uint16_t TIM_OutputNState; /*!< Specifies the TIM complementary Output Compare state. 86 This parameter can be a value of @ref TIM_Output_Compare_N_state 87 @note This parameter is valid only for TIM1. */ 88 89 uint32_t TIM_Pulse; 90 uint16_t TIM_OCPolarity; 91 uint16_t TIM_OCNPolarity; 92 uint16_t TIM_OCIdleState; 93 uint16_t TIM_OCNIdleState; 94 } TIM_OCInitTypeDef; 95 96 /** 97 * @brief TIM Input Capture Init structure definition 98 */ 99 100 typedef struct 101 { 102 uint16_t TIM_Channel; 103 uint16_t TIM_ICPolarity; 104 uint16_t TIM_ICSelection; 105 uint16_t TIM_ICPrescaler; 106 uint16_t TIM_ICFilter; 107 } TIM_ICInitTypeDef; 108 109 /** 110 * @brief BDTR structure definition 111 */ 112 113 typedef struct 114 { 115 uint16_t TIM_OSSRState; 116 uint16_t TIM_OSSIState; 117 uint16_t TIM_LOCKLevel; 118 uint16_t TIM_DeadTime; 119 uint16_t TIM_Break; 120 uint16_t TIM_BreakPolarity; 121 uint16_t TIM_AutomaticOutput; 122 } TIM_BDTRInitTypeDef; 123 124 /** @defgroup TIM_Exported_constants 125 * @{ 126 */ 127 128 #define IS_TIM_ALL_PERIPH(PERIPH) (((*(uint32_t*)&(PERIPH)) == TIM1_BASE) || \ 129 ((*(uint32_t*)&(PERIPH)) == TIM2_BASE) || \ 130 ((*(uint32_t*)&(PERIPH)) == TIM3_BASE) || \ 131 ((*(uint32_t*)&(PERIPH)) == TIM4_BASE)) 132 133 /* LIST4: TIM 1, 2, 3, 14, 15, 16 and 17 */ 134 #define IS_TIM_LIST4_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ 135 ((PERIPH) == TIM2) || \ 136 ((PERIPH) == TIM3) || \ 137 ((PERIPH) == TIM14) || \ 138 ((PERIPH) == TIM16)|| \ 139 ((PERIPH) == TIM17)) 140 141 /* LIST5: TIM 1, 2, 3, 15, 16 and 17 */ 142 #define IS_TIM_LIST5_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ 143 ((PERIPH) == TIM2) || \ 144 ((PERIPH) == TIM3) || \ 145 ((PERIPH) == TIM16)|| \ 146 ((PERIPH) == TIM17)) 147 148 /* LIST6: TIM 1, 2, 3 */ 149 #define IS_TIM_LIST6_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ 150 ((PERIPH) == TIM2) || \ 151 ((PERIPH) == TIM3)) 152 153 /* LIST7: TIM 1, 2, 3 and 14 */ 154 #define IS_TIM_LIST7_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ 155 ((PERIPH) == TIM2) || \ 156 ((PERIPH) == TIM3) || \ 157 ((PERIPH) == TIM14)) 158 159 /* LIST8: TIM 1, 2, 3 and 14 */ 160 #define IS_TIM_LIST8_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ 161 ((PERIPH) == TIM2) || \ 162 ((PERIPH) == TIM3) || \ 163 ((PERIPH) == TIM14)) 164 165 /* LIST9: TIM 1, 2, 3 */ 166 #define IS_TIM_LIST9_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ 167 ((PERIPH) == TIM2) || \ 168 ((PERIPH) == TIM3)) 169 170 /* LIST10: TIM 1, 2, 3, 16 and 17 */ 171 #define IS_TIM_LIST10_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ 172 ((PERIPH) == TIM2) || \ 173 ((PERIPH) == TIM3) || \ 174 ((PERIPH) == TIM16)|| \ 175 ((PERIPH) == TIM17)) 176 177 /* LIST1: TIM 11 */ 178 #define IS_TIM_LIST11_PERIPH(PERIPH) ((PERIPH) == TIM14) 179 180 181 /** 182 * @} 183 */ 184 185 /** @defgroup TIM_Output_Compare_and_PWM_modes 186 * @{ 187 */ 188 189 #define TIM_OCMode_Timing ((uint16_t)0x0000) 190 #define TIM_OCMode_Active ((uint16_t)0x0010) 191 #define TIM_OCMode_Inactive ((uint16_t)0x0020) 192 #define TIM_OCMode_Toggle ((uint16_t)0x0030) 193 #define TIM_OCMode_PWM1 ((uint16_t)0x0060) 194 #define TIM_OCMode_PWM2 ((uint16_t)0x0070) 195 #define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) || \ 196 ((MODE) == TIM_OCMode_Active) || \ 197 ((MODE) == TIM_OCMode_Inactive) || \ 198 ((MODE) == TIM_OCMode_Toggle)|| \ 199 ((MODE) == TIM_OCMode_PWM1) || \ 200 ((MODE) == TIM_OCMode_PWM2)) 201 #define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) || \ 202 ((MODE) == TIM_OCMode_Active) || \ 203 ((MODE) == TIM_OCMode_Inactive) || \ 204 ((MODE) == TIM_OCMode_Toggle)|| \ 205 ((MODE) == TIM_OCMode_PWM1) || \ 206 ((MODE) == TIM_OCMode_PWM2) || \ 207 ((MODE) == TIM_ForcedAction_Active) || \ 208 ((MODE) == TIM_ForcedAction_InActive)) 209 /** 210 * @} 211 */ 212 213 /** @defgroup TIM_One_Pulse_Mode 214 * @{ 215 */ 216 217 #define TIM_OPMode_Single ((uint16_t)0x0008) 218 #define TIM_OPMode_Repetitive ((uint16_t)0x0000) 219 #define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || \ 220 ((MODE) == TIM_OPMode_Repetitive)) 221 /** 222 * @} 223 */ 224 225 /** @defgroup TIM_Channel 226 * @{ 227 */ 228 229 #define TIM_Channel_1 ((uint16_t)0x0000) 230 #define TIM_Channel_2 ((uint16_t)0x0004) 231 #define TIM_Channel_3 ((uint16_t)0x0008) 232 #define TIM_Channel_4 ((uint16_t)0x000C) 233 234 #define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ 235 ((CHANNEL) == TIM_Channel_2) || \ 236 ((CHANNEL) == TIM_Channel_3) || \ 237 ((CHANNEL) == TIM_Channel_4)) 238 #define IS_TIM_COMPLEMENTARY_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ 239 ((CHANNEL) == TIM_Channel_2) || \ 240 ((CHANNEL) == TIM_Channel_3)) 241 #define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ 242 ((CHANNEL) == TIM_Channel_2)) 243 244 /** 245 * @} 246 */ 247 248 /** @defgroup TIM_Clock_Division_CKD 249 * @{ 250 */ 251 252 #define TIM_CKD_DIV1 ((uint16_t)0x0000) 253 #define TIM_CKD_DIV2 ((uint16_t)0x0100) 254 #define TIM_CKD_DIV4 ((uint16_t)0x0200) 255 #define IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) || \ 256 ((DIV) == TIM_CKD_DIV2) || \ 257 ((DIV) == TIM_CKD_DIV4)) 258 /** 259 * @} 260 */ 261 262 /** @defgroup TIM_Counter_Mode 263 * @{ 264 */ 265 266 #define TIM_CounterMode_Up ((uint16_t)0x0000) 267 #define TIM_CounterMode_Down ((uint16_t)0x0010) 268 #define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020) 269 #define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040) 270 #define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060) 271 #define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) || \ 272 ((MODE) == TIM_CounterMode_Down) || \ 273 ((MODE) == TIM_CounterMode_CenterAligned1) || \ 274 ((MODE) == TIM_CounterMode_CenterAligned2) || \ 275 ((MODE) == TIM_CounterMode_CenterAligned3)) 276 /** 277 * @} 278 */ 279 280 /** @defgroup TIM_Output_Compare_Polarity 281 * @{ 282 */ 283 284 #define TIM_OCPolarity_High ((uint16_t)0x0000) 285 #define TIM_OCPolarity_Low ((uint16_t)0x0002) 286 #define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) || \ 287 ((POLARITY) == TIM_OCPolarity_Low)) 288 /** 289 * @} 290 */ 291 292 /** @defgroup TIM_Output_Compare_N_Polarity 293 * @{ 294 */ 295 296 #define TIM_OCNPolarity_High ((uint16_t)0x0000) 297 #define TIM_OCNPolarity_Low ((uint16_t)0x0008) 298 #define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPolarity_High) || \ 299 ((POLARITY) == TIM_OCNPolarity_Low)) 300 /** 301 * @} 302 */ 303 304 /** @defgroup TIM_Output_Compare_state 305 * @{ 306 */ 307 308 #define TIM_OutputState_Disable ((uint16_t)0x0000) 309 #define TIM_OutputState_Enable ((uint16_t)0x0001) 310 #define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) || \ 311 ((STATE) == TIM_OutputState_Enable)) 312 /** 313 * @} 314 */ 315 316 /** @defgroup TIM_Output_Compare_N_state 317 * @{ 318 */ 319 320 #define TIM_OutputNState_Disable ((uint16_t)0x0000) 321 #define TIM_OutputNState_Enable ((uint16_t)0x0004) 322 #define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OutputNState_Disable) || \ 323 ((STATE) == TIM_OutputNState_Enable)) 324 /** 325 * @} 326 */ 327 328 /** @defgroup TIM_Capture_Compare_state 329 * @{ 330 */ 331 332 #define TIM_CCx_Enable ((uint16_t)0x0001) 333 #define TIM_CCx_Disable ((uint16_t)0x0000) 334 #define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) || \ 335 ((CCX) == TIM_CCx_Disable)) 336 /** 337 * @} 338 */ 339 340 /** @defgroup TIM_Capture_Compare_N_state 341 * @{ 342 */ 343 344 #define TIM_CCxN_Enable ((uint16_t)0x0004) 345 #define TIM_CCxN_Disable ((uint16_t)0x0000) 346 #define IS_TIM_CCXN(CCXN) (((CCXN) == TIM_CCxN_Enable) || \ 347 ((CCXN) == TIM_CCxN_Disable)) 348 /** 349 * @} 350 */ 351 352 /** @defgroup TIM_Break_Input_enable_disable 353 * @{ 354 */ 355 356 #define TIM_Break_Enable ((uint16_t)0x1000) 357 #define TIM_Break_Disable ((uint16_t)0x0000) 358 #define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_Break_Enable) || \ 359 ((STATE) == TIM_Break_Disable)) 360 /** 361 * @} 362 */ 363 364 /** @defgroup TIM_Break_Polarity 365 * @{ 366 */ 367 368 #define TIM_BreakPolarity_Low ((uint16_t)0x0000) 369 #define TIM_BreakPolarity_High ((uint16_t)0x2000) 370 #define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BreakPolarity_Low) || \ 371 ((POLARITY) == TIM_BreakPolarity_High)) 372 /** 373 * @} 374 */ 375 376 /** @defgroup TIM_AOE_Bit_Set_Reset 377 * @{ 378 */ 379 380 #define TIM_AutomaticOutput_Enable ((uint16_t)0x4000) 381 #define TIM_AutomaticOutput_Disable ((uint16_t)0x0000) 382 #define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AutomaticOutput_Enable) || \ 383 ((STATE) == TIM_AutomaticOutput_Disable)) 384 /** 385 * @} 386 */ 387 388 /** @defgroup TIM_Lock_level 389 * @{ 390 */ 391 392 #define TIM_LOCKLevel_OFF ((uint16_t)0x0000) 393 #define TIM_LOCKLevel_1 ((uint16_t)0x0100) 394 #define TIM_LOCKLevel_2 ((uint16_t)0x0200) 395 #define TIM_LOCKLevel_3 ((uint16_t)0x0300) 396 #define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLevel_OFF) || \ 397 ((LEVEL) == TIM_LOCKLevel_1) || \ 398 ((LEVEL) == TIM_LOCKLevel_2) || \ 399 ((LEVEL) == TIM_LOCKLevel_3)) 400 /** 401 * @} 402 */ 403 404 /** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state 405 * @{ 406 */ 407 408 #define TIM_OSSIState_Enable ((uint16_t)0x0400) 409 #define TIM_OSSIState_Disable ((uint16_t)0x0000) 410 #define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSIState_Enable) || \ 411 ((STATE) == TIM_OSSIState_Disable)) 412 /** 413 * @} 414 */ 415 416 /** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state 417 * @{ 418 */ 419 420 #define TIM_OSSRState_Enable ((uint16_t)0x0800) 421 #define TIM_OSSRState_Disable ((uint16_t)0x0000) 422 #define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSRState_Enable) || \ 423 ((STATE) == TIM_OSSRState_Disable)) 424 /** 425 * @} 426 */ 427 428 /** @defgroup TIM_Output_Compare_Idle_State 429 * @{ 430 */ 431 432 #define TIM_OCIdleState_Set ((uint16_t)0x0100) 433 #define TIM_OCIdleState_Reset ((uint16_t)0x0000) 434 #define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIdleState_Set) || \ 435 ((STATE) == TIM_OCIdleState_Reset)) 436 /** 437 * @} 438 */ 439 440 /** @defgroup TIM_Output_Compare_N_Idle_State 441 * @{ 442 */ 443 444 #define TIM_OCNIdleState_Set ((uint16_t)0x0200) 445 #define TIM_OCNIdleState_Reset ((uint16_t)0x0000) 446 #define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIdleState_Set) || \ 447 ((STATE) == TIM_OCNIdleState_Reset)) 448 /** 449 * @} 450 */ 451 452 /** @defgroup TIM_Input_Capture_Polarity 453 * @{ 454 */ 455 456 #define TIM_ICPolarity_Rising ((uint16_t)0x0000) 457 #define TIM_ICPolarity_Falling ((uint16_t)0x0002) 458 #define TIM_ICPolarity_BothEdge ((uint16_t)0x000A) 459 #define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \ 460 ((POLARITY) == TIM_ICPolarity_Falling)|| \ 461 ((POLARITY) == TIM_ICPolarity_BothEdge)) 462 /** 463 * @} 464 */ 465 466 /** @defgroup TIM_Input_Capture_Selection 467 * @{ 468 */ 469 470 #define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /*!< TIM Input 1, 2, 3 or 4 is selected to be 471 connected to IC1, IC2, IC3 or IC4, respectively */ 472 #define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /*!< TIM Input 1, 2, 3 or 4 is selected to be 473 connected to IC2, IC1, IC4 or IC3, respectively. */ 474 #define TIM_ICSelection_TRC ((uint16_t)0x0003) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */ 475 #define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) || \ 476 ((SELECTION) == TIM_ICSelection_IndirectTI) || \ 477 ((SELECTION) == TIM_ICSelection_TRC)) 478 /** 479 * @} 480 */ 481 482 /** @defgroup TIM_Input_Capture_Prescaler 483 * @{ 484 */ 485 486 #define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input. */ 487 #define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /*!< Capture performed once every 2 events. */ 488 #define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /*!< Capture performed once every 4 events. */ 489 #define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /*!< Capture performed once every 8 events. */ 490 #define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \ 491 ((PRESCALER) == TIM_ICPSC_DIV2) || \ 492 ((PRESCALER) == TIM_ICPSC_DIV4) || \ 493 ((PRESCALER) == TIM_ICPSC_DIV8)) 494 /** 495 * @} 496 */ 497 498 /** @defgroup TIM_interrupt_sources 499 * @{ 500 */ 501 502 #define TIM_IT_Update ((uint16_t)0x0001) 503 #define TIM_IT_CC1 ((uint16_t)0x0002) 504 #define TIM_IT_CC2 ((uint16_t)0x0004) 505 #define TIM_IT_CC3 ((uint16_t)0x0008) 506 #define TIM_IT_CC4 ((uint16_t)0x0010) 507 #define TIM_IT_COM ((uint16_t)0x0020) 508 #define TIM_IT_Trigger ((uint16_t)0x0040) 509 #define TIM_IT_Break ((uint16_t)0x0080) 510 #define IS_TIM_IT(IT) ((((IT) & (uint16_t)0xFF00) == 0x0000) && ((IT) != 0x0000)) 511 512 #define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) || \ 513 ((IT) == TIM_IT_CC1) || \ 514 ((IT) == TIM_IT_CC2) || \ 515 ((IT) == TIM_IT_CC3) || \ 516 ((IT) == TIM_IT_CC4) || \ 517 ((IT) == TIM_IT_COM) || \ 518 ((IT) == TIM_IT_Trigger) || \ 519 ((IT) == TIM_IT_Break)) 520 /** 521 * @} 522 */ 523 524 /** @defgroup TIM_DMA_Base_address 525 * @{ 526 */ 527 528 #define TIM_DMABase_CR1 ((uint16_t)0x0000) 529 #define TIM_DMABase_CR2 ((uint16_t)0x0001) 530 #define TIM_DMABase_SMCR ((uint16_t)0x0002) 531 #define TIM_DMABase_DIER ((uint16_t)0x0003) 532 #define TIM_DMABase_SR ((uint16_t)0x0004) 533 #define TIM_DMABase_EGR ((uint16_t)0x0005) 534 #define TIM_DMABase_CCMR1 ((uint16_t)0x0006) 535 #define TIM_DMABase_CCMR2 ((uint16_t)0x0007) 536 #define TIM_DMABase_CCER ((uint16_t)0x0008) 537 #define TIM_DMABase_CNT ((uint16_t)0x0009) 538 #define TIM_DMABase_PSC ((uint16_t)0x000A) 539 #define TIM_DMABase_ARR ((uint16_t)0x000B) 540 #define TIM_DMABase_RCR ((uint16_t)0x000C) 541 #define TIM_DMABase_CCR1 ((uint16_t)0x000D) 542 #define TIM_DMABase_CCR2 ((uint16_t)0x000E) 543 #define TIM_DMABase_CCR3 ((uint16_t)0x000F) 544 #define TIM_DMABase_CCR4 ((uint16_t)0x0010) 545 #define TIM_DMABase_BDTR ((uint16_t)0x0011) 546 #define TIM_DMABase_DCR ((uint16_t)0x0012) 547 #define TIM_DMABase_OR ((uint16_t)0x0013) 548 #define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \ 549 ((BASE) == TIM_DMABase_CR2) || \ 550 ((BASE) == TIM_DMABase_SMCR) || \ 551 ((BASE) == TIM_DMABase_DIER) || \ 552 ((BASE) == TIM_DMABase_SR) || \ 553 ((BASE) == TIM_DMABase_EGR) || \ 554 ((BASE) == TIM_DMABase_CCMR1) || \ 555 ((BASE) == TIM_DMABase_CCMR2) || \ 556 ((BASE) == TIM_DMABase_CCER) || \ 557 ((BASE) == TIM_DMABase_CNT) || \ 558 ((BASE) == TIM_DMABase_PSC) || \ 559 ((BASE) == TIM_DMABase_ARR) || \ 560 ((BASE) == TIM_DMABase_RCR) || \ 561 ((BASE) == TIM_DMABase_CCR1) || \ 562 ((BASE) == TIM_DMABase_CCR2) || \ 563 ((BASE) == TIM_DMABase_CCR3) || \ 564 ((BASE) == TIM_DMABase_CCR4) || \ 565 ((BASE) == TIM_DMABase_BDTR) || \ 566 ((BASE) == TIM_DMABase_DCR) || \ 567 ((BASE) == TIM_DMABase_OR)) 568 /** 569 * @} 570 */ 571 572 573 /** @defgroup TIM_DMA_Burst_Length 574 * @{ 575 */ 576 577 #define TIM_DMABurstLength_1Transfer ((uint16_t)0x0000) 578 #define TIM_DMABurstLength_2Transfers ((uint16_t)0x0100) 579 #define TIM_DMABurstLength_3Transfers ((uint16_t)0x0200) 580 #define TIM_DMABurstLength_4Transfers ((uint16_t)0x0300) 581 #define TIM_DMABurstLength_5Transfers ((uint16_t)0x0400) 582 #define TIM_DMABurstLength_6Transfers ((uint16_t)0x0500) 583 #define TIM_DMABurstLength_7Transfers ((uint16_t)0x0600) 584 #define TIM_DMABurstLength_8Transfers ((uint16_t)0x0700) 585 #define TIM_DMABurstLength_9Transfers ((uint16_t)0x0800) 586 #define TIM_DMABurstLength_10Transfers ((uint16_t)0x0900) 587 #define TIM_DMABurstLength_11Transfers ((uint16_t)0x0A00) 588 #define TIM_DMABurstLength_12Transfers ((uint16_t)0x0B00) 589 #define TIM_DMABurstLength_13Transfers ((uint16_t)0x0C00) 590 #define TIM_DMABurstLength_14Transfers ((uint16_t)0x0D00) 591 #define TIM_DMABurstLength_15Transfers ((uint16_t)0x0E00) 592 #define TIM_DMABurstLength_16Transfers ((uint16_t)0x0F00) 593 #define TIM_DMABurstLength_17Transfers ((uint16_t)0x1000) 594 #define TIM_DMABurstLength_18Transfers ((uint16_t)0x1100) 595 #define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer) || \ 596 ((LENGTH) == TIM_DMABurstLength_2Transfers) || \ 597 ((LENGTH) == TIM_DMABurstLength_3Transfers) || \ 598 ((LENGTH) == TIM_DMABurstLength_4Transfers) || \ 599 ((LENGTH) == TIM_DMABurstLength_5Transfers) || \ 600 ((LENGTH) == TIM_DMABurstLength_6Transfers) || \ 601 ((LENGTH) == TIM_DMABurstLength_7Transfers) || \ 602 ((LENGTH) == TIM_DMABurstLength_8Transfers) || \ 603 ((LENGTH) == TIM_DMABurstLength_9Transfers) || \ 604 ((LENGTH) == TIM_DMABurstLength_10Transfers) || \ 605 ((LENGTH) == TIM_DMABurstLength_11Transfers) || \ 606 ((LENGTH) == TIM_DMABurstLength_12Transfers) || \ 607 ((LENGTH) == TIM_DMABurstLength_13Transfers) || \ 608 ((LENGTH) == TIM_DMABurstLength_14Transfers) || \ 609 ((LENGTH) == TIM_DMABurstLength_15Transfers) || \ 610 ((LENGTH) == TIM_DMABurstLength_16Transfers) || \ 611 ((LENGTH) == TIM_DMABurstLength_17Transfers) || \ 612 ((LENGTH) == TIM_DMABurstLength_18Transfers)) 613 /** 614 * @} 615 */ 616 617 /** @defgroup TIM_DMA_sources 618 * @{ 619 */ 620 621 #define TIM_DMA_Update ((uint16_t)0x0100) 622 #define TIM_DMA_CC1 ((uint16_t)0x0200) 623 #define TIM_DMA_CC2 ((uint16_t)0x0400) 624 #define TIM_DMA_CC3 ((uint16_t)0x0800) 625 #define TIM_DMA_CC4 ((uint16_t)0x1000) 626 #define TIM_DMA_COM ((uint16_t)0x2000) 627 #define TIM_DMA_Trigger ((uint16_t)0x4000) 628 #define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000)) 629 630 /** 631 * @} 632 */ 633 634 /** @defgroup TIM_External_Trigger_Prescaler 635 * @{ 636 */ 637 638 #define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000) 639 #define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000) 640 #define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000) 641 #define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000) 642 #define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) || \ 643 ((PRESCALER) == TIM_ExtTRGPSC_DIV2) || \ 644 ((PRESCALER) == TIM_ExtTRGPSC_DIV4) || \ 645 ((PRESCALER) == TIM_ExtTRGPSC_DIV8)) 646 /** 647 * @} 648 */ 649 650 /** @defgroup TIM_Internal_Trigger_Selection 651 * @{ 652 */ 653 654 #define TIM_TS_ITR0 ((uint16_t)0x0000) 655 #define TIM_TS_ITR1 ((uint16_t)0x0010) 656 #define TIM_TS_ITR2 ((uint16_t)0x0020) 657 #define TIM_TS_ITR3 ((uint16_t)0x0030) 658 #define TIM_TS_TI1F_ED ((uint16_t)0x0040) 659 #define TIM_TS_TI1FP1 ((uint16_t)0x0050) 660 #define TIM_TS_TI2FP2 ((uint16_t)0x0060) 661 #define TIM_TS_ETRF ((uint16_t)0x0070) 662 #define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ 663 ((SELECTION) == TIM_TS_ITR1) || \ 664 ((SELECTION) == TIM_TS_ITR2) || \ 665 ((SELECTION) == TIM_TS_ITR3) || \ 666 ((SELECTION) == TIM_TS_TI1F_ED) || \ 667 ((SELECTION) == TIM_TS_TI1FP1) || \ 668 ((SELECTION) == TIM_TS_TI2FP2) || \ 669 ((SELECTION) == TIM_TS_ETRF)) 670 #define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ 671 ((SELECTION) == TIM_TS_ITR1) || \ 672 ((SELECTION) == TIM_TS_ITR2) || \ 673 ((SELECTION) == TIM_TS_ITR3)) 674 /** 675 * @} 676 */ 677 678 /** @defgroup TIM_TIx_External_Clock_Source 679 * @{ 680 */ 681 682 #define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050) 683 #define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060) 684 #define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040) 685 686 /** 687 * @} 688 */ 689 690 /** @defgroup TIM_External_Trigger_Polarity 691 * @{ 692 */ 693 #define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000) 694 #define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000) 695 #define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) || \ 696 ((POLARITY) == TIM_ExtTRGPolarity_NonInverted)) 697 /** 698 * @} 699 */ 700 701 /** @defgroup TIM_Prescaler_Reload_Mode 702 * @{ 703 */ 704 705 #define TIM_PSCReloadMode_Update ((uint16_t)0x0000) 706 #define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001) 707 #define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) || \ 708 ((RELOAD) == TIM_PSCReloadMode_Immediate)) 709 /** 710 * @} 711 */ 712 713 /** @defgroup TIM_Forced_Action 714 * @{ 715 */ 716 717 #define TIM_ForcedAction_Active ((uint16_t)0x0050) 718 #define TIM_ForcedAction_InActive ((uint16_t)0x0040) 719 #define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) || \ 720 ((ACTION) == TIM_ForcedAction_InActive)) 721 /** 722 * @} 723 */ 724 725 /** @defgroup TIM_Encoder_Mode 726 * @{ 727 */ 728 729 #define TIM_EncoderMode_TI1 ((uint16_t)0x0001) 730 #define TIM_EncoderMode_TI2 ((uint16_t)0x0002) 731 #define TIM_EncoderMode_TI12 ((uint16_t)0x0003) 732 #define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) || \ 733 ((MODE) == TIM_EncoderMode_TI2) || \ 734 ((MODE) == TIM_EncoderMode_TI12)) 735 /** 736 * @} 737 */ 738 739 740 /** @defgroup TIM_Event_Source 741 * @{ 742 */ 743 744 #define TIM_EventSource_Update ((uint16_t)0x0001) 745 #define TIM_EventSource_CC1 ((uint16_t)0x0002) 746 #define TIM_EventSource_CC2 ((uint16_t)0x0004) 747 #define TIM_EventSource_CC3 ((uint16_t)0x0008) 748 #define TIM_EventSource_CC4 ((uint16_t)0x0010) 749 #define TIM_EventSource_COM ((uint16_t)0x0020) 750 #define TIM_EventSource_Trigger ((uint16_t)0x0040) 751 #define TIM_EventSource_Break ((uint16_t)0x0080) 752 #define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xFF00) == 0x0000) && ((SOURCE) != 0x0000)) 753 754 /** 755 * @} 756 */ 757 758 /** @defgroup TIM_Update_Source 759 * @{ 760 */ 761 762 #define TIM_UpdateSource_Global ((uint16_t)0x0000) /*!< Source of update is the counter overflow/underflow 763 or the setting of UG bit, or an update generation 764 through the slave mode controller. */ 765 #define TIM_UpdateSource_Regular ((uint16_t)0x0001) /*!< Source of update is counter overflow/underflow. */ 766 #define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || \ 767 ((SOURCE) == TIM_UpdateSource_Regular)) 768 /** 769 * @} 770 */ 771 772 /** @defgroup TIM_Output_Compare_Preload_State 773 * @{ 774 */ 775 776 #define TIM_OCPreload_Enable ((uint16_t)0x0008) 777 #define TIM_OCPreload_Disable ((uint16_t)0x0000) 778 #define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || \ 779 ((STATE) == TIM_OCPreload_Disable)) 780 /** 781 * @} 782 */ 783 784 /** @defgroup TIM_Output_Compare_Fast_State 785 * @{ 786 */ 787 788 #define TIM_OCFast_Enable ((uint16_t)0x0004) 789 #define TIM_OCFast_Disable ((uint16_t)0x0000) 790 #define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) || \ 791 ((STATE) == TIM_OCFast_Disable)) 792 793 /** 794 * @} 795 */ 796 797 /** @defgroup TIM_Output_Compare_Clear_State 798 * @{ 799 */ 800 801 #define TIM_OCClear_Enable ((uint16_t)0x0080) 802 #define TIM_OCClear_Disable ((uint16_t)0x0000) 803 #define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) || \ 804 ((STATE) == TIM_OCClear_Disable)) 805 /** 806 * @} 807 */ 808 809 /** @defgroup TIM_Trigger_Output_Source 810 * @{ 811 */ 812 813 #define TIM_TRGOSource_Reset ((uint16_t)0x0000) 814 #define TIM_TRGOSource_Enable ((uint16_t)0x0010) 815 #define TIM_TRGOSource_Update ((uint16_t)0x0020) 816 #define TIM_TRGOSource_OC1 ((uint16_t)0x0030) 817 #define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040) 818 #define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050) 819 #define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060) 820 #define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070) 821 #define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) || \ 822 ((SOURCE) == TIM_TRGOSource_Enable) || \ 823 ((SOURCE) == TIM_TRGOSource_Update) || \ 824 ((SOURCE) == TIM_TRGOSource_OC1) || \ 825 ((SOURCE) == TIM_TRGOSource_OC1Ref) || \ 826 ((SOURCE) == TIM_TRGOSource_OC2Ref) || \ 827 ((SOURCE) == TIM_TRGOSource_OC3Ref) || \ 828 ((SOURCE) == TIM_TRGOSource_OC4Ref)) 829 /** 830 * @} 831 */ 832 833 /** @defgroup TIM_Slave_Mode 834 * @{ 835 */ 836 837 #define TIM_SlaveMode_Reset ((uint16_t)0x0004) 838 #define TIM_SlaveMode_Gated ((uint16_t)0x0005) 839 #define TIM_SlaveMode_Trigger ((uint16_t)0x0006) 840 #define TIM_SlaveMode_External1 ((uint16_t)0x0007) 841 #define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) || \ 842 ((MODE) == TIM_SlaveMode_Gated) || \ 843 ((MODE) == TIM_SlaveMode_Trigger) || \ 844 ((MODE) == TIM_SlaveMode_External1)) 845 /** 846 * @} 847 */ 848 849 /** @defgroup TIM_Master_Slave_Mode 850 * @{ 851 */ 852 853 #define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080) 854 #define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000) 855 #define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) || \ 856 ((STATE) == TIM_MasterSlaveMode_Disable)) 857 /** 858 * @} 859 */ 860 861 /** @defgroup TIM_Flags 862 * @{ 863 */ 864 865 #define TIM_FLAG_Update ((uint16_t)0x0001) 866 #define TIM_FLAG_CC1 ((uint16_t)0x0002) 867 #define TIM_FLAG_CC2 ((uint16_t)0x0004) 868 #define TIM_FLAG_CC3 ((uint16_t)0x0008) 869 #define TIM_FLAG_CC4 ((uint16_t)0x0010) 870 #define TIM_FLAG_COM ((uint16_t)0x0020) 871 #define TIM_FLAG_Trigger ((uint16_t)0x0040) 872 #define TIM_FLAG_Break ((uint16_t)0x0080) 873 #define TIM_FLAG_CC1OF ((uint16_t)0x0200) 874 #define TIM_FLAG_CC2OF ((uint16_t)0x0400) 875 #define TIM_FLAG_CC3OF ((uint16_t)0x0800) 876 #define TIM_FLAG_CC4OF ((uint16_t)0x1000) 877 #define IS_TIM_GET_FLAG(FLAG) (((FLAG) == TIM_FLAG_Update) || \ 878 ((FLAG) == TIM_FLAG_CC1) || \ 879 ((FLAG) == TIM_FLAG_CC2) || \ 880 ((FLAG) == TIM_FLAG_CC3) || \ 881 ((FLAG) == TIM_FLAG_CC4) || \ 882 ((FLAG) == TIM_FLAG_COM) || \ 883 ((FLAG) == TIM_FLAG_Trigger) || \ 884 ((FLAG) == TIM_FLAG_Break) || \ 885 ((FLAG) == TIM_FLAG_CC1OF) || \ 886 ((FLAG) == TIM_FLAG_CC2OF) || \ 887 ((FLAG) == TIM_FLAG_CC3OF) || \ 888 ((FLAG) == TIM_FLAG_CC4OF)) 889 890 891 #define IS_TIM_CLEAR_FLAG(TIM_FLAG) ((((TIM_FLAG) & (uint16_t)0xE100) == 0x0000) && ((TIM_FLAG) != 0x0000)) 892 /** 893 * @} 894 */ 895 896 897 /** @defgroup TIM_Input_Capture_Filer_Value 898 * @{ 899 */ 900 901 #define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF) 902 /** 903 * @} 904 */ 905 906 /** @defgroup TIM_External_Trigger_Filter 907 * @{ 908 */ 909 910 #define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF) 911 /** 912 * @} 913 */ 914 915 /** @defgroup TIM_OCReferenceClear 916 * @{ 917 */ 918 #define TIM_OCReferenceClear_ETRF ((uint16_t)0x0008) 919 #define TIM_OCReferenceClear_OCREFCLR ((uint16_t)0x0000) 920 #define TIM_OCREFERENCECECLEAR_SOURCE(SOURCE) (((SOURCE) == TIM_OCReferenceClear_ETRF) || \ 921 ((SOURCE) == TIM_OCReferenceClear_OCREFCLR)) 922 923 /** 924 * @} 925 */ 926 /** @defgroup TIM_Remap 927 * @{ 928 */ 929 #define TIM14_GPIO ((uint16_t)0x0000) 930 #define TIM14_RTC_CLK ((uint16_t)0x0001) 931 #define TIM14_HSEDiv32 ((uint16_t)0x0002) 932 #define TIM14_MCO ((uint16_t)0x0003) 933 934 #define IS_TIM_REMAP(TIM_REMAP) (((TIM_REMAP) == TIM14_GPIO)|| \ 935 ((TIM_REMAP) == TIM14_RTC_CLK) || \ 936 ((TIM_REMAP) == TIM14_HSEDiv32) || \ 937 ((TIM_REMAP) == TIM14_MCO)) 938 /** 939 * @} 940 */ 941 942 /** @defgroup TIM_Legacy 943 * @{ 944 */ 945 946 #define TIM_DMABurstLength_1Byte TIM_DMABurstLength_1Transfer 947 #define TIM_DMABurstLength_2Bytes TIM_DMABurstLength_2Transfers 948 #define TIM_DMABurstLength_3Bytes TIM_DMABurstLength_3Transfers 949 #define TIM_DMABurstLength_4Bytes TIM_DMABurstLength_4Transfers 950 #define TIM_DMABurstLength_5Bytes TIM_DMABurstLength_5Transfers 951 #define TIM_DMABurstLength_6Bytes TIM_DMABurstLength_6Transfers 952 #define TIM_DMABurstLength_7Bytes TIM_DMABurstLength_7Transfers 953 #define TIM_DMABurstLength_8Bytes TIM_DMABurstLength_8Transfers 954 #define TIM_DMABurstLength_9Bytes TIM_DMABurstLength_9Transfers 955 #define TIM_DMABurstLength_10Bytes TIM_DMABurstLength_10Transfers 956 #define TIM_DMABurstLength_11Bytes TIM_DMABurstLength_11Transfers 957 #define TIM_DMABurstLength_12Bytes TIM_DMABurstLength_12Transfers 958 #define TIM_DMABurstLength_13Bytes TIM_DMABurstLength_13Transfers 959 #define TIM_DMABurstLength_14Bytes TIM_DMABurstLength_14Transfers 960 #define TIM_DMABurstLength_15Bytes TIM_DMABurstLength_15Transfers 961 #define TIM_DMABurstLength_16Bytes TIM_DMABurstLength_16Transfers 962 #define TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers 963 #define TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers 964 /** 965 * @} 966 */ 967 968 /** 969 * @} 970 */ 971 972 /* Exported macro ------------------------------------------------------------*/ 973 /* Exported functions ------------------------------------------------------- */ 974 975 /* TimeBase management ********************************************************/ 976 void TIM_DeInit(TIM_TypeDef* TIMx); 977 void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct); 978 void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct); 979 void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode); 980 void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode); 981 void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter); 982 void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload); 983 uint32_t TIM_GetCounter(TIM_TypeDef* TIMx); 984 uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx); 985 void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState); 986 void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource); 987 void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState); 988 void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode); 989 void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD); 990 void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState); 991 992 /* Advanced-control timers (TIM1) specific features*******************/ 993 void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct); 994 void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct); 995 void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState); 996 997 /* Output Compare management **************************************************/ 998 void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); 999 void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); 1000 void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); 1001 void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); 1002 void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct); 1003 void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode); 1004 void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1); 1005 void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2); 1006 void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3); 1007 void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4); 1008 void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); 1009 void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); 1010 void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); 1011 void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); 1012 void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState); 1013 void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); 1014 void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); 1015 void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); 1016 void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); 1017 void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); 1018 void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); 1019 void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); 1020 void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); 1021 void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); 1022 void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); 1023 void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); 1024 void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); 1025 void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); 1026 void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); 1027 void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); 1028 void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); 1029 void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); 1030 void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); 1031 void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); 1032 void TIM_SelectOCREFClear(TIM_TypeDef* TIMx, uint16_t TIM_OCReferenceClear); 1033 void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx); 1034 void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN); 1035 void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState); 1036 1037 /* Input Capture management ***************************************************/ 1038 void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct); 1039 void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct); 1040 void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct); 1041 uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx); 1042 uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx); 1043 uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx); 1044 uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx); 1045 void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); 1046 void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); 1047 void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); 1048 void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); 1049 1050 /* Interrupts, DMA and flags management ***************************************/ 1051 void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState); 1052 void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource); 1053 FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG); 1054 void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG); 1055 ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT); 1056 void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT); 1057 void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength); 1058 void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState); 1059 void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState); 1060 1061 /* Clocks management **********************************************************/ 1062 void TIM_InternalClockConfig(TIM_TypeDef* TIMx); 1063 void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); 1064 void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource, 1065 uint16_t TIM_ICPolarity, uint16_t ICFilter); 1066 void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, 1067 uint16_t ExtTRGFilter); 1068 void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, 1069 uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter); 1070 1071 1072 /* Synchronization management *************************************************/ 1073 void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); 1074 void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource); 1075 void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode); 1076 void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode); 1077 void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, 1078 uint16_t ExtTRGFilter); 1079 1080 /* Specific interface management **********************************************/ 1081 void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode, 1082 uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity); 1083 void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState); 1084 1085 /* Specific remapping management **********************************************/ 1086 void TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap); 1087 1088 1089 #ifdef __cplusplus 1090 } 1091 #endif 1092 1093 #endif /*__HAL_TIM_H */ 1094 1095 /** 1096 * @} 1097 */ 1098 1099 /** 1100 * @} 1101 */ 1102 1103 /*-------------------------(C) COPYRIGHT 2016 HOLOCENE ----------------------*/ 1104