1 /** 2 ****************************************************************************** 3 * @file HAL_dma.c 4 * @author IC Applications Department 5 * @version V0.8 6 * @date 2019_08_02 7 * @brief This file provides all the DMA firmware functions. 8 ****************************************************************************** 9 * @copy 10 * 11 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 12 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 13 * TIME. AS A RESULT, HOLOCENE SHALL NOT BE HELD LIABLE FOR ANY 14 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 15 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 16 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 17 * 18 * <h2><center>© COPYRIGHT 2016 HOLOCENE</center></h2> 19 */ 20 21 /* Includes ------------------------------------------------------------------*/ 22 #include "HAL_dma.h" 23 24 //?? 25 #ifdef 0 26 27 28 29 /** @addtogroup StdPeriph_Driver 30 * @{ 31 */ 32 33 /** @defgroup DMA 34 * @brief DMA driver modules 35 * @{ 36 */ 37 38 /** @defgroup DMA_Private_TypesDefinitions 39 * @{ 40 */ 41 /** 42 * @} 43 */ 44 45 /** @defgroup DMA_Private_Defines 46 * @{ 47 */ 48 49 /* DMA ENABLE mask */ 50 #define CCR_ENABLE_Set ((uint32_t)0x00000001) 51 #define CCR_ENABLE_Reset ((uint32_t)0xFFFFFFFE) 52 53 /* DMA1 Channelx interrupt pending bit masks */ 54 #define DMA1_Channel1_IT_Mask ((uint32_t)0x0000000F) 55 #define DMA1_Channel2_IT_Mask ((uint32_t)0x000000F0) 56 #define DMA1_Channel3_IT_Mask ((uint32_t)0x00000F00) 57 #define DMA1_Channel4_IT_Mask ((uint32_t)0x0000F000) 58 #define DMA1_Channel5_IT_Mask ((uint32_t)0x000F0000) 59 60 61 62 63 64 /* DMA registers Masks */ 65 #define CCR_CLEAR_Mask ((uint32_t)0xFFFF800F) 66 67 /** 68 * @} 69 */ 70 71 /** @defgroup DMA_Private_Macros 72 * @{ 73 */ 74 75 /** 76 * @} 77 */ 78 79 /** @defgroup DMA_Private_Variables 80 * @{ 81 */ 82 83 /** 84 * @} 85 */ 86 87 /** @defgroup DMA_Private_FunctionPrototypes 88 * @{ 89 */ 90 91 /** 92 * @} 93 */ 94 95 /** @defgroup DMA_Private_Functions 96 * @{ 97 */ 98 99 /** 100 * @brief Deinitializes the DMAy Channelx registers to their default reset 101 * values. 102 * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and 103 * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the 104 * DMA Channel. 105 * @retval : None 106 */ 107 void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx) 108 { 109 /* Check the parameters */ 110 assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); 111 /* Disable the selected DMAy Channelx */ 112 DMAy_Channelx->CCR &= CCR_ENABLE_Reset; 113 /* Reset DMAy Channelx control register */ 114 DMAy_Channelx->CCR = 0; 115 116 /* Reset DMAy Channelx remaining bytes register */ 117 DMAy_Channelx->CNDTR = 0; 118 119 /* Reset DMAy Channelx peripheral address register */ 120 DMAy_Channelx->CPAR = 0; 121 122 /* Reset DMAy Channelx memory address register */ 123 DMAy_Channelx->CMAR = 0; 124 switch (*(uint32_t*)&DMAy_Channelx) 125 { 126 case DMA1_Channel1_BASE: 127 /* Reset interrupt pending bits for DMA1 Channel1 */ 128 DMA1->IFCR |= DMA1_Channel1_IT_Mask; 129 break; 130 case DMA1_Channel2_BASE: 131 /* Reset interrupt pending bits for DMA1 Channel2 */ 132 DMA1->IFCR |= DMA1_Channel2_IT_Mask; 133 break; 134 case DMA1_Channel3_BASE: 135 /* Reset interrupt pending bits for DMA1 Channel3 */ 136 DMA1->IFCR |= DMA1_Channel3_IT_Mask; 137 break; 138 case DMA1_Channel4_BASE: 139 /* Reset interrupt pending bits for DMA1 Channel4 */ 140 DMA1->IFCR |= DMA1_Channel4_IT_Mask; 141 break; 142 case DMA1_Channel5_BASE: 143 /* Reset interrupt pending bits for DMA1 Channel5 */ 144 DMA1->IFCR |= DMA1_Channel5_IT_Mask; 145 break; 146 147 148 default: 149 break; 150 } 151 } 152 153 /** 154 * @brief Initializes the DMAy Channelx according to the specified 155 * parameters in the DMA_InitStruct. 156 * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and 157 * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the 158 * DMA Channel. 159 * @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure that 160 * contains the configuration information for the specified 161 * DMA Channel. 162 * @retval : None 163 */ 164 void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct) 165 { 166 uint32_t tmpreg = 0; 167 /* Check the parameters */ 168 assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); 169 assert_param(IS_DMA_DIR(DMA_InitStruct->DMA_DIR)); 170 assert_param(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize)); 171 assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc)); 172 assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc)); 173 assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize)); 174 assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize)); 175 assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode)); 176 assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority)); 177 assert_param(IS_DMA_M2M_STATE(DMA_InitStruct->DMA_M2M)); 178 /*--------------------------- DMAy Channelx CCR Configuration -----------------*/ 179 /* Get the DMAy_Channelx CCR value */ 180 tmpreg = DMAy_Channelx->CCR; 181 /* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */ 182 tmpreg &= CCR_CLEAR_Mask; 183 /* Configure DMAy Channelx: data transfer, data size, priority level and mode */ 184 /* Set DIR bit according to DMA_DIR value */ 185 /* Set CIRC bit according to DMA_Mode value */ 186 /* Set PINC bit according to DMA_PeripheralInc value */ 187 /* Set MINC bit according to DMA_MemoryInc value */ 188 /* Set PSIZE bits according to DMA_PeripheralDataSize value */ 189 /* Set MSIZE bits according to DMA_MemoryDataSize value */ 190 /* Set PL bits according to DMA_Priority value */ 191 /* Set the MEM2MEM bit according to DMA_M2M value */ 192 tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode | 193 DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc | 194 DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize | 195 DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M; 196 /* Write to DMAy Channelx CCR */ 197 DMAy_Channelx->CCR = tmpreg; 198 /*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/ 199 /* Write to DMAy Channelx CNDTR */ 200 DMAy_Channelx->CNDTR = DMA_InitStruct->DMA_BufferSize; 201 /*--------------------------- DMAy Channelx CPAR Configuration ----------------*/ 202 /* Write to DMAy Channelx CPAR */ 203 DMAy_Channelx->CPAR = DMA_InitStruct->DMA_PeripheralBaseAddr; 204 /*--------------------------- DMAy Channelx CMAR Configuration ----------------*/ 205 /* Write to DMAy Channelx CMAR */ 206 DMAy_Channelx->CMAR = DMA_InitStruct->DMA_MemoryBaseAddr; 207 } 208 209 /** 210 * @brief Fills each DMA_InitStruct member with its default value. 211 * @param DMA_InitStruct : pointer to a DMA_InitTypeDef structure 212 * which will be initialized. 213 * @retval : None 214 */ 215 void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct) 216 { 217 /*-------------- Reset DMA init structure parameters values ------------------*/ 218 /* Initialize the DMA_PeripheralBaseAddr member */ 219 DMA_InitStruct->DMA_PeripheralBaseAddr = 0; 220 /* Initialize the DMA_MemoryBaseAddr member */ 221 DMA_InitStruct->DMA_MemoryBaseAddr = 0; 222 /* Initialize the DMA_DIR member */ 223 DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC; 224 /* Initialize the DMA_BufferSize member */ 225 DMA_InitStruct->DMA_BufferSize = 0; 226 /* Initialize the DMA_PeripheralInc member */ 227 DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable; 228 /* Initialize the DMA_MemoryInc member */ 229 DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable; 230 /* Initialize the DMA_PeripheralDataSize member */ 231 DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; 232 /* Initialize the DMA_MemoryDataSize member */ 233 DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; 234 /* Initialize the DMA_Mode member */ 235 DMA_InitStruct->DMA_Mode = DMA_Mode_Normal; 236 /* Initialize the DMA_Priority member */ 237 DMA_InitStruct->DMA_Priority = DMA_Priority_Low; 238 /* Initialize the DMA_M2M member */ 239 DMA_InitStruct->DMA_M2M = DMA_M2M_Disable; 240 } 241 242 /** 243 * @brief Enables or disables the specified DMAy Channelx. 244 * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and 245 * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the 246 * DMA Channel. 247 * @param NewState: new state of the DMAy Channelx. 248 * This parameter can be: ENABLE or DISABLE. 249 * @retval : None 250 */ 251 void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState) 252 { 253 /* Check the parameters */ 254 assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); 255 assert_param(IS_FUNCTIONAL_STATE(NewState)); 256 if (NewState != DISABLE) 257 { 258 /* Enable the selected DMAy Channelx */ 259 DMAy_Channelx->CCR |= CCR_ENABLE_Set; 260 } 261 else 262 { 263 /* Disable the selected DMAy Channelx */ 264 DMAy_Channelx->CCR &= CCR_ENABLE_Reset; 265 } 266 } 267 268 /** 269 * @brief Enables or disables the specified DMAy Channelx interrupts. 270 * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and 271 * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the 272 * DMA Channel. 273 * @param DMA_IT: specifies the DMA interrupts sources to be enabled 274 * or disabled. 275 * This parameter can be any combination of the following values: 276 * @arg DMA_IT_TC: Transfer complete interrupt mask 277 * @arg DMA_IT_HT: Half transfer interrupt mask 278 * @arg DMA_IT_TE: Transfer error interrupt mask 279 * @param NewState: new state of the specified DMA interrupts. 280 * This parameter can be: ENABLE or DISABLE. 281 * @retval : None 282 */ 283 void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState) 284 { 285 /* Check the parameters */ 286 assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); 287 assert_param(IS_DMA_CONFIG_IT(DMA_IT)); 288 assert_param(IS_FUNCTIONAL_STATE(NewState)); 289 if (NewState != DISABLE) 290 { 291 /* Enable the selected DMA interrupts */ 292 DMAy_Channelx->CCR |= DMA_IT; 293 } 294 else 295 { 296 /* Disable the selected DMA interrupts */ 297 DMAy_Channelx->CCR &= ~DMA_IT; 298 } 299 } 300 301 /** 302 * @brief Returns the number of remaining data units in the current 303 * DMAy Channelx transfer. 304 * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and 305 * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the 306 * DMA Channel. 307 * @retval : The number of remaining data units in the current DMAy Channelx 308 * transfer. 309 */ 310 uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx) 311 { 312 /* Check the parameters */ 313 assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); 314 /* Return the number of remaining data units for DMAy Channelx */ 315 return ((uint16_t)(DMAy_Channelx->CNDTR)); 316 } 317 318 /** 319 * @brief Checks whether the specified DMAy Channelx flag is set or not. 320 * @param DMA_FLAG: specifies the flag to check. 321 * This parameter can be one of the following values: 322 * @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag. 323 * @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag. 324 * @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag. 325 * @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag. 326 * @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag. 327 * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag. 328 * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag. 329 * @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag. 330 * @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag. 331 * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag. 332 * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag. 333 * @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag. 334 * @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag. 335 * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag. 336 * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag. 337 * @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag. 338 * @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag. 339 * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag. 340 * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag. 341 * @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag. 342 * @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag. 343 * @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag. 344 * @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag. 345 * @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag. 346 * @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag. 347 * @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag. 348 * @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag. 349 * @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag. 350 * @retval : The new state of DMA_FLAG (SET or RESET). 351 */ 352 FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG) 353 { 354 FlagStatus bitstatus = RESET; 355 uint32_t tmpreg = 0; 356 /* Check the parameters */ 357 assert_param(IS_DMA_GET_FLAG(DMA_FLAG)); 358 359 /* Get DMA1 ISR register value */ 360 tmpreg = DMA1->ISR ; 361 362 /* Check the status of the specified DMA flag */ 363 if ((tmpreg & DMA_FLAG) != (uint32_t)RESET) 364 { 365 /* DMA_FLAG is set */ 366 bitstatus = SET; 367 } 368 else 369 { 370 /* DMA_FLAG is reset */ 371 bitstatus = RESET; 372 } 373 374 /* Return the DMA_FLAG status */ 375 return bitstatus; 376 } 377 378 /** 379 * @brief Clears the DMAy Channelx's pending flags. 380 * @param DMA_FLAG: specifies the flag to clear. 381 * This parameter can be any combination (for the same DMA) of 382 * the following values: 383 * @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag. 384 * @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag. 385 * @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag. 386 * @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag. 387 * @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag. 388 * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag. 389 * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag. 390 * @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag. 391 * @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag. 392 * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag. 393 * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag. 394 * @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag. 395 * @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag. 396 * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag. 397 * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag. 398 * @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag. 399 * @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag. 400 * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag. 401 * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag. 402 * @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag. 403 * @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag. 404 * @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag. 405 * @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag. 406 * @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag. 407 * @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag. 408 * @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag. 409 * @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag. 410 * @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag. 411 * @retval : None 412 */ 413 void DMA_ClearFlag(uint32_t DMA_FLAG) 414 { 415 /* Check the parameters */ 416 assert_param(IS_DMA_CLEAR_FLAG(DMA_FLAG)); 417 418 /* Clear the selected DMA flags */ 419 DMA1->IFCR = DMA_FLAG; 420 } 421 422 /** 423 * @brief Checks whether the specified DMAy Channelx interrupt has 424 * occurred or not. 425 * @param DMA_IT: specifies the DMA interrupt source to check. 426 * This parameter can be one of the following values: 427 * @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt. 428 * @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt. 429 * @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt. 430 * @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt. 431 * @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt. 432 * @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt. 433 * @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt. 434 * @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt. 435 * @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt. 436 * @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt. 437 * @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt. 438 * @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt. 439 * @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt. 440 * @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt. 441 * @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt. 442 * @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt. 443 * @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt. 444 * @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt. 445 * @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt. 446 * @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt. 447 * @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt. 448 * @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt. 449 * @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt. 450 * @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt. 451 * @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt. 452 * @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt. 453 * @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt. 454 * @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt. 455 * @retval : The new state of DMA_IT (SET or RESET). 456 */ 457 ITStatus DMA_GetITStatus(uint32_t DMA_IT) 458 { 459 ITStatus bitstatus = RESET; 460 uint32_t tmpreg = 0; 461 /* Check the parameters */ 462 assert_param(IS_DMA_GET_IT(DMA_IT)); 463 464 /* Get DMA1 ISR register value */ 465 tmpreg = DMA1->ISR ; 466 467 /* Check the status of the specified DMA interrupt */ 468 if ((tmpreg & DMA_IT) != (uint32_t)RESET) 469 { 470 /* DMA_IT is set */ 471 bitstatus = SET; 472 } 473 else 474 { 475 /* DMA_IT is reset */ 476 bitstatus = RESET; 477 } 478 /* Return the DMA_IT status */ 479 return bitstatus; 480 } 481 482 /** 483 * @brief Clears the DMAy Channelx’s interrupt pending bits. 484 * @param DMA_IT: specifies the DMA interrupt pending bit to clear. 485 * This parameter can be any combination (for the same DMA) of 486 * the following values: 487 * @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt. 488 * @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt. 489 * @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt. 490 * @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt. 491 * @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt. 492 * @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt. 493 * @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt. 494 * @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt. 495 * @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt. 496 * @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt. 497 * @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt. 498 * @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt. 499 * @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt. 500 * @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt. 501 * @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt. 502 * @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt. 503 * @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt. 504 * @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt. 505 * @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt. 506 * @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt. 507 * @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt. 508 * @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt. 509 * @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt. 510 * @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt. 511 * @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt. 512 * @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt. 513 * @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt. 514 * @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt. 515 * @retval : None 516 */ 517 void DMA_ClearITPendingBit(uint32_t DMA_IT) 518 { 519 /* Check the parameters */ 520 assert_param(IS_DMA_CLEAR_IT(DMA_IT)); 521 522 /* Clear the selected DMA interrupt pending bits */ 523 DMA1->IFCR = DMA_IT; 524 525 } 526 527 /** 528 * @} 529 */ 530 531 /** 532 * @} 533 */ 534 535 /** 536 * @} 537 */ 538 #endif // 0 539 /*-------------------------(C) COPYRIGHT 2016 HOLOCENE ----------------------*/ 540