1 /** 2 ****************************************************************************** 3 * @file HAL_pwr.c 4 * @author IC Applications Department 5 * @version V0.8 6 * @date 2019_08_02 7 * @brief This file provides all the PWR firmware functions. 8 ****************************************************************************** 9 * @copy 10 * 11 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 12 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 13 * TIME. AS A RESULT, HOLOCENE SHALL NOT BE HELD LIABLE FOR ANY 14 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 15 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 16 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 17 * 18 * <h2><center>© COPYRIGHT 2016 HOLOCENE</center></h2> 19 */ 20 21 /* Includes ------------------------------------------------------------------*/ 22 #include "HAL_pwr.h" 23 #include "HAL_rcc.h" 24 25 /** @addtogroup StdPeriph_Driver 26 * @{ 27 */ 28 29 /** @defgroup PWR 30 * @brief PWR driver modules 31 * @{ 32 */ 33 34 /** @defgroup PWR_Private_TypesDefinitions 35 * @{ 36 */ 37 38 /** 39 * @} 40 */ 41 42 /** @defgroup PWR_Private_Defines 43 * @{ 44 */ 45 46 /* --------- PWR registers bit address in the alias region ---------- */ 47 #define PWR_OFFSET (PWR_BASE - PERIPH_BASE) 48 49 /* --- CR Register ---*/ 50 51 /* Alias word address of DBP bit */ 52 #define CR_OFFSET (PWR_OFFSET + 0x00) 53 #define DBP_BitNumber 0x08 54 #define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4)) 55 56 /* Alias word address of PVDE bit */ 57 #define PVDE_BitNumber 0x04 58 #define CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4)) 59 60 /* --- CSR Register ---*/ 61 62 /* Alias word address of EWUP bit */ 63 #define CSR_OFFSET (PWR_OFFSET + 0x04) 64 #define EWUP_BitNumber 0x08 65 #define CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4)) 66 67 /* ------------------ PWR registers bit mask ------------------------ */ 68 69 /* CR register bit mask */ 70 #define CR_PDDS_Set ((uint32_t)0x00000002) 71 #define CR_DS_Mask ((uint32_t)0xFFFFFFFC) 72 #define CR_CWUF_Set ((uint32_t)0x00000004) 73 #define CR_PLS_Mask ((uint32_t)0xFFFFE1FF) 74 75 /* --------- Cortex System Control register bit mask ---------------- */ 76 77 /* Cortex System Control register address */ 78 #define SCB_SysCtrl ((uint32_t)0xE000ED10) 79 80 /* SLEEPDEEP bit mask */ 81 #define SysCtrl_SLEEPDEEP_Set ((uint32_t)0x00000004) 82 /** 83 * @} 84 */ 85 86 /** @defgroup PWR_Private_Macros 87 * @{ 88 */ 89 90 /** 91 * @} 92 */ 93 94 /** @defgroup PWR_Private_Variables 95 * @{ 96 */ 97 98 /** 99 * @} 100 */ 101 102 /** @defgroup PWR_Private_FunctionPrototypes 103 * @{ 104 */ 105 106 /** 107 * @} 108 */ 109 110 /** @defgroup PWR_Private_Functions 111 * @{ 112 */ 113 114 /** 115 * @brief Deinitializes the PWR peripheral registers to their default 116 * reset values. 117 * @param None 118 * @retval : None 119 */ PWR_DeInit(void)120void PWR_DeInit(void) 121 { 122 RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE); 123 RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE); 124 } 125 126 /** 127 * @brief Enables or disables access to the RTC and backup registers. 128 * @param NewState: new state of the access to the RTC and backup 129 * registers. This parameter can be: ENABLE or DISABLE. 130 * @retval : None 131 */ PWR_BackupAccessCmd(FunctionalState NewState)132void PWR_BackupAccessCmd(FunctionalState NewState) 133 { 134 /* Check the parameters */ 135 assert_param(IS_FUNCTIONAL_STATE(NewState)); 136 //*(__IO uint32_t *) CR_DBP_BB = (uint32_t)NewState; 137 if(NewState!=DISABLE) 138 { 139 PWR->CR |= 0x00000100; 140 } 141 else 142 { 143 PWR->CR &= 0xfffffeff; 144 } 145 146 } 147 148 /** 149 * @brief Enables or disables the Power Voltage Detector(PVD). 150 * @param NewState: new state of the PVD. 151 * This parameter can be: ENABLE or DISABLE. 152 * @retval : None 153 */ PWR_PVDCmd(FunctionalState NewState)154void PWR_PVDCmd(FunctionalState NewState) 155 { 156 /* Check the parameters */ 157 assert_param(IS_FUNCTIONAL_STATE(NewState)); 158 159 if(NewState==ENABLE) 160 { 161 PWR->CR |= 0x00000010; 162 } 163 else 164 { 165 PWR->CR &= 0xffffffef; 166 } 167 168 } 169 170 /** 171 * @brief Configures the voltage threshold detected by the Power Voltage 172 * Detector(PVD). 173 * @param PWR_PVDLevel: specifies the PVD detection level 174 * This parameter can be one of the following values: 175 * @arg PWR_PVDLevel_2V6: PVD detection level set to 2.6V 176 * @arg PWR_PVDLevel_2V8: PVD detection level set to 2.8V 177 * @arg PWR_PVDLevel_3V0: PVD detection level set to 3.0V 178 * @arg PWR_PVDLevel_3V2: PVD detection level set to 3.2V 179 * @arg PWR_PVDLevel_3V4: PVD detection level set to 3.4V 180 * @arg PWR_PVDLevel_3V6: PVD detection level set to 3.6V 181 * @arg PWR_PVDLevel_3V8: PVD detection level set to 3.8V 182 * @arg PWR_PVDLevel_4V0: PVD detection level set to 4.0V 183 * @arg PWR_PVDLevel_4V2: PVD detection level set to 4.2V 184 * @arg PWR_PVDLevel_4V4: PVD detection level set to 4.4V 185 * @arg PWR_PVDLevel_4V6: PVD detection level set to 4.6V 186 * @retval : None 187 */ PWR_PVDLevelConfig(uint32_t PWR_PVDLevel)188void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel) 189 { 190 uint32_t tmpreg = 0; 191 /* Check the parameters */ 192 assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel)); 193 tmpreg = PWR->CR; 194 /* Clear PLS[7:5] bits */ 195 tmpreg &= CR_PLS_Mask; 196 /* Set PLS[7:5] bits according to PWR_PVDLevel value */ 197 tmpreg |= PWR_PVDLevel; 198 /* Store the new value */ 199 PWR->CR = tmpreg; 200 } 201 202 /** 203 * @brief Enables or disables the WakeUp Pin functionality. 204 * @param NewState: new state of the WakeUp Pin functionality. 205 * This parameter can be: ENABLE or DISABLE. 206 * @retval : None 207 */ PWR_WakeUpPinCmd(FunctionalState NewState)208void PWR_WakeUpPinCmd(FunctionalState NewState) 209 { 210 /* Check the parameters */ 211 assert_param(IS_FUNCTIONAL_STATE(NewState)); 212 213 if(NewState!=DISABLE) 214 { 215 PWR->CSR |= 0x00000100; 216 } 217 else 218 { 219 PWR->CSR &= 0xfffffeff; 220 } 221 } 222 223 /** 224 * @brief Enters STOP mode. 225 * @param PWR_Regulator: specifies the regulator state in STOP mode. 226 * This parameter can be one of the following values: 227 * @arg PWR_Regulator_ON: STOP mode with regulator ON 228 * @arg PWR_Regulator_LowPower: STOP mode with 229 * regulator in low power mode 230 * @param PWR_STOPEntry: specifies if STOP mode in entered with WFI or 231 * WFE instruction. 232 * This parameter can be one of the following values: 233 * @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction 234 * @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction 235 * @retval : None 236 */ PWR_EnterSTOPMode(uint32_t PWR_Regulator,uint8_t PWR_STOPEntry)237void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry) 238 { 239 uint32_t tmpreg = 0; 240 /* Check the parameters */ 241 assert_param(IS_PWR_REGULATOR(PWR_Regulator)); 242 assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry)); 243 244 /* Select the regulator state in STOP mode ---------------------------------*/ 245 tmpreg = PWR->CR; 246 /* Clear PDDS and LPDS bits */ 247 tmpreg &= CR_DS_Mask; 248 /* Set LPDS bit according to PWR_Regulator value */ 249 tmpreg |= PWR_Regulator; 250 /* Store the new value */ 251 PWR->CR = tmpreg; 252 /* Set SLEEPDEEP bit of Cortex System Control Register */ 253 254 SCB->SCR |= SysCtrl_SLEEPDEEP_Set; 255 256 /* Select STOP mode entry --------------------------------------------------*/ 257 if(PWR_STOPEntry == PWR_STOPEntry_WFI) 258 { 259 /* Request Wait For Interrupt */ 260 __WFI(); 261 } 262 else 263 { 264 /* Request Wait For Event */ 265 __WFE(); 266 } 267 } 268 269 /** 270 * @brief Enters STANDBY mode. 271 * @param None 272 * @retval : None 273 */ PWR_EnterSTANDBYMode(void)274void PWR_EnterSTANDBYMode(void) 275 { 276 /* Clear Wake-up flag */ 277 PWR->CR |= CR_CWUF_Set; 278 /* Select STANDBY mode */ 279 PWR->CR |= CR_PDDS_Set; 280 /* Set SLEEPDEEP bit of Cortex System Control Register */ 281 282 SCB->SCR |= SysCtrl_SLEEPDEEP_Set; 283 /* This option is used to ensure that store operations are completed */ 284 #if defined ( __CC_ARM ) 285 __force_stores(); 286 #endif 287 /* Request Wait For Interrupt */ 288 __WFI(); 289 } 290 291 /** 292 * @brief Checks whether the specified PWR flag is set or not. 293 * @param PWR_FLAG: specifies the flag to check. 294 * This parameter can be one of the following values: 295 * @arg PWR_FLAG_WU: Wake Up flag 296 * @arg PWR_FLAG_SB: StandBy flag 297 * @arg PWR_FLAG_PVDO: PVD Output 298 * @retval : The new state of PWR_FLAG (SET or RESET). 299 */ PWR_GetFlagStatus(uint32_t PWR_FLAG)300FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG) 301 { 302 FlagStatus bitstatus = RESET; 303 /* Check the parameters */ 304 assert_param(IS_PWR_GET_FLAG(PWR_FLAG)); 305 306 if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET) 307 { 308 bitstatus = SET; 309 } 310 else 311 { 312 bitstatus = RESET; 313 } 314 /* Return the flag status */ 315 return bitstatus; 316 } 317 318 /** 319 * @brief Clears the PWR's pending flags. 320 * @param PWR_FLAG: specifies the flag to clear. 321 * This parameter can be one of the following values: 322 * @arg PWR_FLAG_WU: Wake Up flag 323 * @arg PWR_FLAG_SB: StandBy flag 324 * @retval : None 325 */ PWR_ClearFlag(uint32_t PWR_FLAG)326void PWR_ClearFlag(uint32_t PWR_FLAG) 327 { 328 /* Check the parameters */ 329 assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG)); 330 331 PWR->CR |= PWR_FLAG << 2; 332 } 333 334 /** 335 * @} 336 */ 337 338 /** 339 * @} 340 */ 341 342 /** 343 * @} 344 */ 345 346 /*-------------------------(C) COPYRIGHT 2016 HOLOCENE ----------------------*/ 347