1 //***************************************************************************** 2 // 3 // hw_aes.h - Macros used when accessing the AES hardware. 4 // 5 // Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved. 6 // Software License Agreement 7 // 8 // Redistribution and use in source and binary forms, with or without 9 // modification, are permitted provided that the following conditions 10 // are met: 11 // 12 // Redistributions of source code must retain the above copyright 13 // notice, this list of conditions and the following disclaimer. 14 // 15 // Redistributions in binary form must reproduce the above copyright 16 // notice, this list of conditions and the following disclaimer in the 17 // documentation and/or other materials provided with the 18 // distribution. 19 // 20 // Neither the name of Texas Instruments Incorporated nor the names of 21 // its contributors may be used to endorse or promote products derived 22 // from this software without specific prior written permission. 23 // 24 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 27 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 28 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 29 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 30 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 34 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 // 36 // This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. 37 // 38 //***************************************************************************** 39 40 #ifndef __HW_AES_H__ 41 #define __HW_AES_H__ 42 43 //***************************************************************************** 44 // 45 // The following are defines for the AES register offsets. 46 // 47 //***************************************************************************** 48 #define AES_O_KEY2_6 0x00000000 // AES Key 2_6 49 #define AES_O_KEY2_7 0x00000004 // AES Key 2_7 50 #define AES_O_KEY2_4 0x00000008 // AES Key 2_4 51 #define AES_O_KEY2_5 0x0000000C // AES Key 2_5 52 #define AES_O_KEY2_2 0x00000010 // AES Key 2_2 53 #define AES_O_KEY2_3 0x00000014 // AES Key 2_3 54 #define AES_O_KEY2_0 0x00000018 // AES Key 2_0 55 #define AES_O_KEY2_1 0x0000001C // AES Key 2_1 56 #define AES_O_KEY1_6 0x00000020 // AES Key 1_6 57 #define AES_O_KEY1_7 0x00000024 // AES Key 1_7 58 #define AES_O_KEY1_4 0x00000028 // AES Key 1_4 59 #define AES_O_KEY1_5 0x0000002C // AES Key 1_5 60 #define AES_O_KEY1_2 0x00000030 // AES Key 1_2 61 #define AES_O_KEY1_3 0x00000034 // AES Key 1_3 62 #define AES_O_KEY1_0 0x00000038 // AES Key 1_0 63 #define AES_O_KEY1_1 0x0000003C // AES Key 1_1 64 #define AES_O_IV_IN_0 0x00000040 // AES Initialization Vector Input 65 // 0 66 #define AES_O_IV_IN_1 0x00000044 // AES Initialization Vector Input 67 // 1 68 #define AES_O_IV_IN_2 0x00000048 // AES Initialization Vector Input 69 // 2 70 #define AES_O_IV_IN_3 0x0000004C // AES Initialization Vector Input 71 // 3 72 #define AES_O_CTRL 0x00000050 // AES Control 73 #define AES_O_C_LENGTH_0 0x00000054 // AES Crypto Data Length 0 74 #define AES_O_C_LENGTH_1 0x00000058 // AES Crypto Data Length 1 75 #define AES_O_AUTH_LENGTH 0x0000005C // AES Authentication Data Length 76 #define AES_O_DATA_IN_0 0x00000060 // AES Data RW Plaintext/Ciphertext 77 // 0 78 #define AES_O_DATA_IN_1 0x00000064 // AES Data RW Plaintext/Ciphertext 79 // 1 80 #define AES_O_DATA_IN_2 0x00000068 // AES Data RW Plaintext/Ciphertext 81 // 2 82 #define AES_O_DATA_IN_3 0x0000006C // AES Data RW Plaintext/Ciphertext 83 // 3 84 #define AES_O_TAG_OUT_0 0x00000070 // AES Hash Tag Out 0 85 #define AES_O_TAG_OUT_1 0x00000074 // AES Hash Tag Out 1 86 #define AES_O_TAG_OUT_2 0x00000078 // AES Hash Tag Out 2 87 #define AES_O_TAG_OUT_3 0x0000007C // AES Hash Tag Out 3 88 #define AES_O_REVISION 0x00000080 // AES IP Revision Identifier 89 #define AES_O_SYSCONFIG 0x00000084 // AES System Configuration 90 #define AES_O_SYSSTATUS 0x00000088 // AES System Status 91 #define AES_O_IRQSTATUS 0x0000008C // AES Interrupt Status 92 #define AES_O_IRQENABLE 0x00000090 // AES Interrupt Enable 93 #define AES_O_DIRTYBITS 0x00000094 // AES Dirty Bits 94 #define AES_O_DMAIM 0xFFFFA020 // AES DMA Interrupt Mask 95 #define AES_O_DMARIS 0xFFFFA024 // AES DMA Raw Interrupt Status 96 #define AES_O_DMAMIS 0xFFFFA028 // AES DMA Masked Interrupt Status 97 #define AES_O_DMAIC 0xFFFFA02C // AES DMA Interrupt Clear 98 99 //***************************************************************************** 100 // 101 // The following are defines for the bit fields in the AES_O_KEY2_6 register. 102 // 103 //***************************************************************************** 104 #define AES_KEY2_6_KEY_M 0xFFFFFFFF // Key Data 105 #define AES_KEY2_6_KEY_S 0 106 107 //***************************************************************************** 108 // 109 // The following are defines for the bit fields in the AES_O_KEY2_7 register. 110 // 111 //***************************************************************************** 112 #define AES_KEY2_7_KEY_M 0xFFFFFFFF // Key Data 113 #define AES_KEY2_7_KEY_S 0 114 115 //***************************************************************************** 116 // 117 // The following are defines for the bit fields in the AES_O_KEY2_4 register. 118 // 119 //***************************************************************************** 120 #define AES_KEY2_4_KEY_M 0xFFFFFFFF // Key Data 121 #define AES_KEY2_4_KEY_S 0 122 123 //***************************************************************************** 124 // 125 // The following are defines for the bit fields in the AES_O_KEY2_5 register. 126 // 127 //***************************************************************************** 128 #define AES_KEY2_5_KEY_M 0xFFFFFFFF // Key Data 129 #define AES_KEY2_5_KEY_S 0 130 131 //***************************************************************************** 132 // 133 // The following are defines for the bit fields in the AES_O_KEY2_2 register. 134 // 135 //***************************************************************************** 136 #define AES_KEY2_2_KEY_M 0xFFFFFFFF // Key Data 137 #define AES_KEY2_2_KEY_S 0 138 139 //***************************************************************************** 140 // 141 // The following are defines for the bit fields in the AES_O_KEY2_3 register. 142 // 143 //***************************************************************************** 144 #define AES_KEY2_3_KEY_M 0xFFFFFFFF // Key Data 145 #define AES_KEY2_3_KEY_S 0 146 147 //***************************************************************************** 148 // 149 // The following are defines for the bit fields in the AES_O_KEY2_0 register. 150 // 151 //***************************************************************************** 152 #define AES_KEY2_0_KEY_M 0xFFFFFFFF // Key Data 153 #define AES_KEY2_0_KEY_S 0 154 155 //***************************************************************************** 156 // 157 // The following are defines for the bit fields in the AES_O_KEY2_1 register. 158 // 159 //***************************************************************************** 160 #define AES_KEY2_1_KEY_M 0xFFFFFFFF // Key Data 161 #define AES_KEY2_1_KEY_S 0 162 163 //***************************************************************************** 164 // 165 // The following are defines for the bit fields in the AES_O_KEY1_6 register. 166 // 167 //***************************************************************************** 168 #define AES_KEY1_6_KEY_M 0xFFFFFFFF // Key Data 169 #define AES_KEY1_6_KEY_S 0 170 171 //***************************************************************************** 172 // 173 // The following are defines for the bit fields in the AES_O_KEY1_7 register. 174 // 175 //***************************************************************************** 176 #define AES_KEY1_7_KEY_M 0xFFFFFFFF // Key Data 177 #define AES_KEY1_7_KEY_S 0 178 179 //***************************************************************************** 180 // 181 // The following are defines for the bit fields in the AES_O_KEY1_4 register. 182 // 183 //***************************************************************************** 184 #define AES_KEY1_4_KEY_M 0xFFFFFFFF // Key Data 185 #define AES_KEY1_4_KEY_S 0 186 187 //***************************************************************************** 188 // 189 // The following are defines for the bit fields in the AES_O_KEY1_5 register. 190 // 191 //***************************************************************************** 192 #define AES_KEY1_5_KEY_M 0xFFFFFFFF // Key Data 193 #define AES_KEY1_5_KEY_S 0 194 195 //***************************************************************************** 196 // 197 // The following are defines for the bit fields in the AES_O_KEY1_2 register. 198 // 199 //***************************************************************************** 200 #define AES_KEY1_2_KEY_M 0xFFFFFFFF // Key Data 201 #define AES_KEY1_2_KEY_S 0 202 203 //***************************************************************************** 204 // 205 // The following are defines for the bit fields in the AES_O_KEY1_3 register. 206 // 207 //***************************************************************************** 208 #define AES_KEY1_3_KEY_M 0xFFFFFFFF // Key Data 209 #define AES_KEY1_3_KEY_S 0 210 211 //***************************************************************************** 212 // 213 // The following are defines for the bit fields in the AES_O_KEY1_0 register. 214 // 215 //***************************************************************************** 216 #define AES_KEY1_0_KEY_M 0xFFFFFFFF // Key Data 217 #define AES_KEY1_0_KEY_S 0 218 219 //***************************************************************************** 220 // 221 // The following are defines for the bit fields in the AES_O_KEY1_1 register. 222 // 223 //***************************************************************************** 224 #define AES_KEY1_1_KEY_M 0xFFFFFFFF // Key Data 225 #define AES_KEY1_1_KEY_S 0 226 227 //***************************************************************************** 228 // 229 // The following are defines for the bit fields in the AES_O_IV_IN_0 register. 230 // 231 //***************************************************************************** 232 #define AES_IV_IN_0_DATA_M 0xFFFFFFFF // Initialization Vector Input 233 #define AES_IV_IN_0_DATA_S 0 234 235 //***************************************************************************** 236 // 237 // The following are defines for the bit fields in the AES_O_IV_IN_1 register. 238 // 239 //***************************************************************************** 240 #define AES_IV_IN_1_DATA_M 0xFFFFFFFF // Initialization Vector Input 241 #define AES_IV_IN_1_DATA_S 0 242 243 //***************************************************************************** 244 // 245 // The following are defines for the bit fields in the AES_O_IV_IN_2 register. 246 // 247 //***************************************************************************** 248 #define AES_IV_IN_2_DATA_M 0xFFFFFFFF // Initialization Vector Input 249 #define AES_IV_IN_2_DATA_S 0 250 251 //***************************************************************************** 252 // 253 // The following are defines for the bit fields in the AES_O_IV_IN_3 register. 254 // 255 //***************************************************************************** 256 #define AES_IV_IN_3_DATA_M 0xFFFFFFFF // Initialization Vector Input 257 #define AES_IV_IN_3_DATA_S 0 258 259 //***************************************************************************** 260 // 261 // The following are defines for the bit fields in the AES_O_CTRL register. 262 // 263 //***************************************************************************** 264 #define AES_CTRL_CTXTRDY 0x80000000 // Context Data Registers Ready 265 #define AES_CTRL_SVCTXTRDY 0x40000000 // AES TAG/IV Block(s) Ready 266 #define AES_CTRL_SAVE_CONTEXT 0x20000000 // TAG or Result IV Save 267 #define AES_CTRL_CCM_M_M 0x01C00000 // Counter with CBC-MAC (CCM) 268 #define AES_CTRL_CCM_L_M 0x00380000 // L Value 269 #define AES_CTRL_CCM_L_2 0x00080000 // width = 2 270 #define AES_CTRL_CCM_L_4 0x00180000 // width = 4 271 #define AES_CTRL_CCM_L_8 0x00380000 // width = 8 272 #define AES_CTRL_CCM 0x00040000 // AES-CCM Mode Enable 273 #define AES_CTRL_GCM_M 0x00030000 // AES-GCM Mode Enable 274 #define AES_CTRL_GCM_NOP 0x00000000 // No operation 275 #define AES_CTRL_GCM_HLY0ZERO 0x00010000 // GHASH with H loaded and 276 // Y0-encrypted forced to zero 277 #define AES_CTRL_GCM_HLY0CALC 0x00020000 // GHASH with H loaded and 278 // Y0-encrypted calculated 279 // internally 280 #define AES_CTRL_GCM_HY0CALC 0x00030000 // Autonomous GHASH (both H and 281 // Y0-encrypted calculated 282 // internally) 283 #define AES_CTRL_CBCMAC 0x00008000 // AES-CBC MAC Enable 284 #define AES_CTRL_F9 0x00004000 // AES f9 Mode Enable 285 #define AES_CTRL_F8 0x00002000 // AES f8 Mode Enable 286 #define AES_CTRL_XTS_M 0x00001800 // AES-XTS Operation Enabled 287 #define AES_CTRL_XTS_NOP 0x00000000 // No operation 288 #define AES_CTRL_XTS_TWEAKJL 0x00000800 // Previous/intermediate tweak 289 // value and j loaded (value is 290 // loaded via IV, j is loaded via 291 // the AAD length register) 292 #define AES_CTRL_XTS_K2IJL 0x00001000 // Key2, n and j are loaded (n is 293 // loaded via IV, j is loaded via 294 // the AAD length register) 295 #define AES_CTRL_XTS_K2ILJ0 0x00001800 // Key2 and n are loaded; j=0 (n is 296 // loaded via IV) 297 #define AES_CTRL_CFB 0x00000400 // Full block AES cipher feedback 298 // mode (CFB128) Enable 299 #define AES_CTRL_ICM 0x00000200 // AES Integer Counter Mode (ICM) 300 // Enable 301 #define AES_CTRL_CTR_WIDTH_M 0x00000180 // AES-CTR Mode Counter Width 302 #define AES_CTRL_CTR_WIDTH_32 0x00000000 // Counter is 32 bits 303 #define AES_CTRL_CTR_WIDTH_64 0x00000080 // Counter is 64 bits 304 #define AES_CTRL_CTR_WIDTH_96 0x00000100 // Counter is 96 bits 305 #define AES_CTRL_CTR_WIDTH_128 0x00000180 // Counter is 128 bits 306 #define AES_CTRL_CTR 0x00000040 // Counter Mode 307 #define AES_CTRL_MODE 0x00000020 // ECB/CBC Mode 308 #define AES_CTRL_KEY_SIZE_M 0x00000018 // Key Size 309 #define AES_CTRL_KEY_SIZE_128 0x00000008 // Key is 128 bits 310 #define AES_CTRL_KEY_SIZE_192 0x00000010 // Key is 192 bits 311 #define AES_CTRL_KEY_SIZE_256 0x00000018 // Key is 256 bits 312 #define AES_CTRL_DIRECTION 0x00000004 // Encryption/Decryption Selection 313 #define AES_CTRL_INPUT_READY 0x00000002 // Input Ready Status 314 #define AES_CTRL_OUTPUT_READY 0x00000001 // Output Ready Status 315 #define AES_CTRL_CCM_M_S 22 316 317 //***************************************************************************** 318 // 319 // The following are defines for the bit fields in the AES_O_C_LENGTH_0 320 // register. 321 // 322 //***************************************************************************** 323 #define AES_C_LENGTH_0_LENGTH_M 0xFFFFFFFF // Data Length 324 #define AES_C_LENGTH_0_LENGTH_S 0 325 326 //***************************************************************************** 327 // 328 // The following are defines for the bit fields in the AES_O_C_LENGTH_1 329 // register. 330 // 331 //***************************************************************************** 332 #define AES_C_LENGTH_1_LENGTH_M 0xFFFFFFFF // Data Length 333 #define AES_C_LENGTH_1_LENGTH_S 0 334 335 //***************************************************************************** 336 // 337 // The following are defines for the bit fields in the AES_O_AUTH_LENGTH 338 // register. 339 // 340 //***************************************************************************** 341 #define AES_AUTH_LENGTH_AUTH_M 0xFFFFFFFF // Authentication Data Length 342 #define AES_AUTH_LENGTH_AUTH_S 0 343 344 //***************************************************************************** 345 // 346 // The following are defines for the bit fields in the AES_O_DATA_IN_0 347 // register. 348 // 349 //***************************************************************************** 350 #define AES_DATA_IN_0_DATA_M 0xFFFFFFFF // Secure Data RW 351 // Plaintext/Ciphertext 352 #define AES_DATA_IN_0_DATA_S 0 353 354 //***************************************************************************** 355 // 356 // The following are defines for the bit fields in the AES_O_DATA_IN_1 357 // register. 358 // 359 //***************************************************************************** 360 #define AES_DATA_IN_1_DATA_M 0xFFFFFFFF // Secure Data RW 361 // Plaintext/Ciphertext 362 #define AES_DATA_IN_1_DATA_S 0 363 364 //***************************************************************************** 365 // 366 // The following are defines for the bit fields in the AES_O_DATA_IN_2 367 // register. 368 // 369 //***************************************************************************** 370 #define AES_DATA_IN_2_DATA_M 0xFFFFFFFF // Secure Data RW 371 // Plaintext/Ciphertext 372 #define AES_DATA_IN_2_DATA_S 0 373 374 //***************************************************************************** 375 // 376 // The following are defines for the bit fields in the AES_O_DATA_IN_3 377 // register. 378 // 379 //***************************************************************************** 380 #define AES_DATA_IN_3_DATA_M 0xFFFFFFFF // Secure Data RW 381 // Plaintext/Ciphertext 382 #define AES_DATA_IN_3_DATA_S 0 383 384 //***************************************************************************** 385 // 386 // The following are defines for the bit fields in the AES_O_TAG_OUT_0 387 // register. 388 // 389 //***************************************************************************** 390 #define AES_TAG_OUT_0_HASH_M 0xFFFFFFFF // Hash Result 391 #define AES_TAG_OUT_0_HASH_S 0 392 393 //***************************************************************************** 394 // 395 // The following are defines for the bit fields in the AES_O_TAG_OUT_1 396 // register. 397 // 398 //***************************************************************************** 399 #define AES_TAG_OUT_1_HASH_M 0xFFFFFFFF // Hash Result 400 #define AES_TAG_OUT_1_HASH_S 0 401 402 //***************************************************************************** 403 // 404 // The following are defines for the bit fields in the AES_O_TAG_OUT_2 405 // register. 406 // 407 //***************************************************************************** 408 #define AES_TAG_OUT_2_HASH_M 0xFFFFFFFF // Hash Result 409 #define AES_TAG_OUT_2_HASH_S 0 410 411 //***************************************************************************** 412 // 413 // The following are defines for the bit fields in the AES_O_TAG_OUT_3 414 // register. 415 // 416 //***************************************************************************** 417 #define AES_TAG_OUT_3_HASH_M 0xFFFFFFFF // Hash Result 418 #define AES_TAG_OUT_3_HASH_S 0 419 420 //***************************************************************************** 421 // 422 // The following are defines for the bit fields in the AES_O_REVISION register. 423 // 424 //***************************************************************************** 425 #define AES_REVISION_M 0xFFFFFFFF // Revision number 426 #define AES_REVISION_S 0 427 428 //***************************************************************************** 429 // 430 // The following are defines for the bit fields in the AES_O_SYSCONFIG 431 // register. 432 // 433 //***************************************************************************** 434 #define AES_SYSCONFIG_K3 0x00001000 // K3 Select 435 #define AES_SYSCONFIG_KEYENC 0x00000800 // Key Encoding 436 #define AES_SYSCONFIG_MAP_CONTEXT_OUT_ON_DATA_OUT \ 437 0x00000200 // Map Context Out on Data Out 438 // Enable 439 #define AES_SYSCONFIG_DMA_REQ_CONTEXT_OUT_EN \ 440 0x00000100 // DMA Request Context Out Enable 441 #define AES_SYSCONFIG_DMA_REQ_CONTEXT_IN_EN \ 442 0x00000080 // DMA Request Context In Enable 443 #define AES_SYSCONFIG_DMA_REQ_DATA_OUT_EN \ 444 0x00000040 // DMA Request Data Out Enable 445 #define AES_SYSCONFIG_DMA_REQ_DATA_IN_EN \ 446 0x00000020 // DMA Request Data In Enable 447 #define AES_SYSCONFIG_SOFTRESET 0x00000002 // Soft reset 448 449 //***************************************************************************** 450 // 451 // The following are defines for the bit fields in the AES_O_SYSSTATUS 452 // register. 453 // 454 //***************************************************************************** 455 #define AES_SYSSTATUS_RESETDONE 0x00000001 // Reset Done 456 457 //***************************************************************************** 458 // 459 // The following are defines for the bit fields in the AES_O_IRQSTATUS 460 // register. 461 // 462 //***************************************************************************** 463 #define AES_IRQSTATUS_CONTEXT_OUT \ 464 0x00000008 // Context Output Interrupt Status 465 #define AES_IRQSTATUS_DATA_OUT 0x00000004 // Data Out Interrupt Status 466 #define AES_IRQSTATUS_DATA_IN 0x00000002 // Data In Interrupt Status 467 #define AES_IRQSTATUS_CONTEXT_IN \ 468 0x00000001 // Context In Interrupt Status 469 470 //***************************************************************************** 471 // 472 // The following are defines for the bit fields in the AES_O_IRQENABLE 473 // register. 474 // 475 //***************************************************************************** 476 #define AES_IRQENABLE_CONTEXT_OUT \ 477 0x00000008 // Context Out Interrupt Enable 478 #define AES_IRQENABLE_DATA_OUT 0x00000004 // Data Out Interrupt Enable 479 #define AES_IRQENABLE_DATA_IN 0x00000002 // Data In Interrupt Enable 480 #define AES_IRQENABLE_CONTEXT_IN \ 481 0x00000001 // Context In Interrupt Enable 482 483 //***************************************************************************** 484 // 485 // The following are defines for the bit fields in the AES_O_DIRTYBITS 486 // register. 487 // 488 //***************************************************************************** 489 #define AES_DIRTYBITS_S_DIRTY 0x00000002 // AES Dirty Bit 490 #define AES_DIRTYBITS_S_ACCESS 0x00000001 // AES Access Bit 491 492 //***************************************************************************** 493 // 494 // The following are defines for the bit fields in the AES_O_DMAIM register. 495 // 496 //***************************************************************************** 497 #define AES_DMAIM_DOUT 0x00000008 // Data Out DMA Done Interrupt Mask 498 #define AES_DMAIM_DIN 0x00000004 // Data In DMA Done Interrupt Mask 499 #define AES_DMAIM_COUT 0x00000002 // Context Out DMA Done Interrupt 500 // Mask 501 #define AES_DMAIM_CIN 0x00000001 // Context In DMA Done Interrupt 502 // Mask 503 504 //***************************************************************************** 505 // 506 // The following are defines for the bit fields in the AES_O_DMARIS register. 507 // 508 //***************************************************************************** 509 #define AES_DMARIS_DOUT 0x00000008 // Data Out DMA Done Raw Interrupt 510 // Status 511 #define AES_DMARIS_DIN 0x00000004 // Data In DMA Done Raw Interrupt 512 // Status 513 #define AES_DMARIS_COUT 0x00000002 // Context Out DMA Done Raw 514 // Interrupt Status 515 #define AES_DMARIS_CIN 0x00000001 // Context In DMA Done Raw 516 // Interrupt Status 517 518 //***************************************************************************** 519 // 520 // The following are defines for the bit fields in the AES_O_DMAMIS register. 521 // 522 //***************************************************************************** 523 #define AES_DMAMIS_DOUT 0x00000008 // Data Out DMA Done Masked 524 // Interrupt Status 525 #define AES_DMAMIS_DIN 0x00000004 // Data In DMA Done Masked 526 // Interrupt Status 527 #define AES_DMAMIS_COUT 0x00000002 // Context Out DMA Done Masked 528 // Interrupt Status 529 #define AES_DMAMIS_CIN 0x00000001 // Context In DMA Done Raw 530 // Interrupt Status 531 532 //***************************************************************************** 533 // 534 // The following are defines for the bit fields in the AES_O_DMAIC register. 535 // 536 //***************************************************************************** 537 #define AES_DMAIC_DOUT 0x00000008 // Data Out DMA Done Interrupt 538 // Clear 539 #define AES_DMAIC_DIN 0x00000004 // Data In DMA Done Interrupt Clear 540 #define AES_DMAIC_COUT 0x00000002 // Context Out DMA Done Masked 541 // Interrupt Status 542 #define AES_DMAIC_CIN 0x00000001 // Context In DMA Done Raw 543 // Interrupt Status 544 545 #endif // __HW_AES_H__ 546