1 //***************************************************************************** 2 // 3 // hw_can.h - Defines and macros used when accessing the CAN controllers. 4 // 5 // Copyright (c) 2006-2017 Texas Instruments Incorporated. All rights reserved. 6 // Software License Agreement 7 // 8 // Redistribution and use in source and binary forms, with or without 9 // modification, are permitted provided that the following conditions 10 // are met: 11 // 12 // Redistributions of source code must retain the above copyright 13 // notice, this list of conditions and the following disclaimer. 14 // 15 // Redistributions in binary form must reproduce the above copyright 16 // notice, this list of conditions and the following disclaimer in the 17 // documentation and/or other materials provided with the 18 // distribution. 19 // 20 // Neither the name of Texas Instruments Incorporated nor the names of 21 // its contributors may be used to endorse or promote products derived 22 // from this software without specific prior written permission. 23 // 24 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 27 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 28 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 29 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 30 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 34 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 // 36 // This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. 37 // 38 //***************************************************************************** 39 40 #ifndef __HW_CAN_H__ 41 #define __HW_CAN_H__ 42 43 //***************************************************************************** 44 // 45 // The following are defines for the CAN register offsets. 46 // 47 //***************************************************************************** 48 #define CAN_O_CTL 0x00000000 // CAN Control 49 #define CAN_O_STS 0x00000004 // CAN Status 50 #define CAN_O_ERR 0x00000008 // CAN Error Counter 51 #define CAN_O_BIT 0x0000000C // CAN Bit Timing 52 #define CAN_O_INT 0x00000010 // CAN Interrupt 53 #define CAN_O_TST 0x00000014 // CAN Test 54 #define CAN_O_BRPE 0x00000018 // CAN Baud Rate Prescaler 55 // Extension 56 #define CAN_O_IF1CRQ 0x00000020 // CAN IF1 Command Request 57 #define CAN_O_IF1CMSK 0x00000024 // CAN IF1 Command Mask 58 #define CAN_O_IF1MSK1 0x00000028 // CAN IF1 Mask 1 59 #define CAN_O_IF1MSK2 0x0000002C // CAN IF1 Mask 2 60 #define CAN_O_IF1ARB1 0x00000030 // CAN IF1 Arbitration 1 61 #define CAN_O_IF1ARB2 0x00000034 // CAN IF1 Arbitration 2 62 #define CAN_O_IF1MCTL 0x00000038 // CAN IF1 Message Control 63 #define CAN_O_IF1DA1 0x0000003C // CAN IF1 Data A1 64 #define CAN_O_IF1DA2 0x00000040 // CAN IF1 Data A2 65 #define CAN_O_IF1DB1 0x00000044 // CAN IF1 Data B1 66 #define CAN_O_IF1DB2 0x00000048 // CAN IF1 Data B2 67 #define CAN_O_IF2CRQ 0x00000080 // CAN IF2 Command Request 68 #define CAN_O_IF2CMSK 0x00000084 // CAN IF2 Command Mask 69 #define CAN_O_IF2MSK1 0x00000088 // CAN IF2 Mask 1 70 #define CAN_O_IF2MSK2 0x0000008C // CAN IF2 Mask 2 71 #define CAN_O_IF2ARB1 0x00000090 // CAN IF2 Arbitration 1 72 #define CAN_O_IF2ARB2 0x00000094 // CAN IF2 Arbitration 2 73 #define CAN_O_IF2MCTL 0x00000098 // CAN IF2 Message Control 74 #define CAN_O_IF2DA1 0x0000009C // CAN IF2 Data A1 75 #define CAN_O_IF2DA2 0x000000A0 // CAN IF2 Data A2 76 #define CAN_O_IF2DB1 0x000000A4 // CAN IF2 Data B1 77 #define CAN_O_IF2DB2 0x000000A8 // CAN IF2 Data B2 78 #define CAN_O_TXRQ1 0x00000100 // CAN Transmission Request 1 79 #define CAN_O_TXRQ2 0x00000104 // CAN Transmission Request 2 80 #define CAN_O_NWDA1 0x00000120 // CAN New Data 1 81 #define CAN_O_NWDA2 0x00000124 // CAN New Data 2 82 #define CAN_O_MSG1INT 0x00000140 // CAN Message 1 Interrupt Pending 83 #define CAN_O_MSG2INT 0x00000144 // CAN Message 2 Interrupt Pending 84 #define CAN_O_MSG1VAL 0x00000160 // CAN Message 1 Valid 85 #define CAN_O_MSG2VAL 0x00000164 // CAN Message 2 Valid 86 87 //***************************************************************************** 88 // 89 // The following are defines for the bit fields in the CAN_O_CTL register. 90 // 91 //***************************************************************************** 92 #define CAN_CTL_TEST 0x00000080 // Test Mode Enable 93 #define CAN_CTL_CCE 0x00000040 // Configuration Change Enable 94 #define CAN_CTL_DAR 0x00000020 // Disable Automatic-Retransmission 95 #define CAN_CTL_EIE 0x00000008 // Error Interrupt Enable 96 #define CAN_CTL_SIE 0x00000004 // Status Interrupt Enable 97 #define CAN_CTL_IE 0x00000002 // CAN Interrupt Enable 98 #define CAN_CTL_INIT 0x00000001 // Initialization 99 100 //***************************************************************************** 101 // 102 // The following are defines for the bit fields in the CAN_O_STS register. 103 // 104 //***************************************************************************** 105 #define CAN_STS_BOFF 0x00000080 // Bus-Off Status 106 #define CAN_STS_EWARN 0x00000040 // Warning Status 107 #define CAN_STS_EPASS 0x00000020 // Error Passive 108 #define CAN_STS_RXOK 0x00000010 // Received a Message Successfully 109 #define CAN_STS_TXOK 0x00000008 // Transmitted a Message 110 // Successfully 111 #define CAN_STS_LEC_M 0x00000007 // Last Error Code 112 #define CAN_STS_LEC_NONE 0x00000000 // No Error 113 #define CAN_STS_LEC_STUFF 0x00000001 // Stuff Error 114 #define CAN_STS_LEC_FORM 0x00000002 // Format Error 115 #define CAN_STS_LEC_ACK 0x00000003 // ACK Error 116 #define CAN_STS_LEC_BIT1 0x00000004 // Bit 1 Error 117 #define CAN_STS_LEC_BIT0 0x00000005 // Bit 0 Error 118 #define CAN_STS_LEC_CRC 0x00000006 // CRC Error 119 #define CAN_STS_LEC_NOEVENT 0x00000007 // No Event 120 121 //***************************************************************************** 122 // 123 // The following are defines for the bit fields in the CAN_O_ERR register. 124 // 125 //***************************************************************************** 126 #define CAN_ERR_RP 0x00008000 // Received Error Passive 127 #define CAN_ERR_REC_M 0x00007F00 // Receive Error Counter 128 #define CAN_ERR_TEC_M 0x000000FF // Transmit Error Counter 129 #define CAN_ERR_REC_S 8 130 #define CAN_ERR_TEC_S 0 131 132 //***************************************************************************** 133 // 134 // The following are defines for the bit fields in the CAN_O_BIT register. 135 // 136 //***************************************************************************** 137 #define CAN_BIT_TSEG2_M 0x00007000 // Time Segment after Sample Point 138 #define CAN_BIT_TSEG1_M 0x00000F00 // Time Segment Before Sample Point 139 #define CAN_BIT_SJW_M 0x000000C0 // (Re)Synchronization Jump Width 140 #define CAN_BIT_BRP_M 0x0000003F // Baud Rate Prescaler 141 #define CAN_BIT_TSEG2_S 12 142 #define CAN_BIT_TSEG1_S 8 143 #define CAN_BIT_SJW_S 6 144 #define CAN_BIT_BRP_S 0 145 146 //***************************************************************************** 147 // 148 // The following are defines for the bit fields in the CAN_O_INT register. 149 // 150 //***************************************************************************** 151 #define CAN_INT_INTID_M 0x0000FFFF // Interrupt Identifier 152 #define CAN_INT_INTID_NONE 0x00000000 // No interrupt pending 153 #define CAN_INT_INTID_STATUS 0x00008000 // Status Interrupt 154 155 //***************************************************************************** 156 // 157 // The following are defines for the bit fields in the CAN_O_TST register. 158 // 159 //***************************************************************************** 160 #define CAN_TST_RX 0x00000080 // Receive Observation 161 #define CAN_TST_TX_M 0x00000060 // Transmit Control 162 #define CAN_TST_TX_CANCTL 0x00000000 // CAN Module Control 163 #define CAN_TST_TX_SAMPLE 0x00000020 // Sample Point 164 #define CAN_TST_TX_DOMINANT 0x00000040 // Driven Low 165 #define CAN_TST_TX_RECESSIVE 0x00000060 // Driven High 166 #define CAN_TST_LBACK 0x00000010 // Loopback Mode 167 #define CAN_TST_SILENT 0x00000008 // Silent Mode 168 #define CAN_TST_BASIC 0x00000004 // Basic Mode 169 170 //***************************************************************************** 171 // 172 // The following are defines for the bit fields in the CAN_O_BRPE register. 173 // 174 //***************************************************************************** 175 #define CAN_BRPE_BRPE_M 0x0000000F // Baud Rate Prescaler Extension 176 #define CAN_BRPE_BRPE_S 0 177 178 //***************************************************************************** 179 // 180 // The following are defines for the bit fields in the CAN_O_IF1CRQ register. 181 // 182 //***************************************************************************** 183 #define CAN_IF1CRQ_BUSY 0x00008000 // Busy Flag 184 #define CAN_IF1CRQ_MNUM_M 0x0000003F // Message Number 185 #define CAN_IF1CRQ_MNUM_S 0 186 187 //***************************************************************************** 188 // 189 // The following are defines for the bit fields in the CAN_O_IF1CMSK register. 190 // 191 //***************************************************************************** 192 #define CAN_IF1CMSK_WRNRD 0x00000080 // Write, Not Read 193 #define CAN_IF1CMSK_MASK 0x00000040 // Access Mask Bits 194 #define CAN_IF1CMSK_ARB 0x00000020 // Access Arbitration Bits 195 #define CAN_IF1CMSK_CONTROL 0x00000010 // Access Control Bits 196 #define CAN_IF1CMSK_CLRINTPND 0x00000008 // Clear Interrupt Pending Bit 197 #define CAN_IF1CMSK_NEWDAT 0x00000004 // Access New Data 198 #define CAN_IF1CMSK_TXRQST 0x00000004 // Access Transmission Request 199 #define CAN_IF1CMSK_DATAA 0x00000002 // Access Data Byte 0 to 3 200 #define CAN_IF1CMSK_DATAB 0x00000001 // Access Data Byte 4 to 7 201 202 //***************************************************************************** 203 // 204 // The following are defines for the bit fields in the CAN_O_IF1MSK1 register. 205 // 206 //***************************************************************************** 207 #define CAN_IF1MSK1_IDMSK_M 0x0000FFFF // Identifier Mask 208 #define CAN_IF1MSK1_IDMSK_S 0 209 210 //***************************************************************************** 211 // 212 // The following are defines for the bit fields in the CAN_O_IF1MSK2 register. 213 // 214 //***************************************************************************** 215 #define CAN_IF1MSK2_MXTD 0x00008000 // Mask Extended Identifier 216 #define CAN_IF1MSK2_MDIR 0x00004000 // Mask Message Direction 217 #define CAN_IF1MSK2_IDMSK_M 0x00001FFF // Identifier Mask 218 #define CAN_IF1MSK2_IDMSK_S 0 219 220 //***************************************************************************** 221 // 222 // The following are defines for the bit fields in the CAN_O_IF1ARB1 register. 223 // 224 //***************************************************************************** 225 #define CAN_IF1ARB1_ID_M 0x0000FFFF // Message Identifier 226 #define CAN_IF1ARB1_ID_S 0 227 228 //***************************************************************************** 229 // 230 // The following are defines for the bit fields in the CAN_O_IF1ARB2 register. 231 // 232 //***************************************************************************** 233 #define CAN_IF1ARB2_MSGVAL 0x00008000 // Message Valid 234 #define CAN_IF1ARB2_XTD 0x00004000 // Extended Identifier 235 #define CAN_IF1ARB2_DIR 0x00002000 // Message Direction 236 #define CAN_IF1ARB2_ID_M 0x00001FFF // Message Identifier 237 #define CAN_IF1ARB2_ID_S 0 238 239 //***************************************************************************** 240 // 241 // The following are defines for the bit fields in the CAN_O_IF1MCTL register. 242 // 243 //***************************************************************************** 244 #define CAN_IF1MCTL_NEWDAT 0x00008000 // New Data 245 #define CAN_IF1MCTL_MSGLST 0x00004000 // Message Lost 246 #define CAN_IF1MCTL_INTPND 0x00002000 // Interrupt Pending 247 #define CAN_IF1MCTL_UMASK 0x00001000 // Use Acceptance Mask 248 #define CAN_IF1MCTL_TXIE 0x00000800 // Transmit Interrupt Enable 249 #define CAN_IF1MCTL_RXIE 0x00000400 // Receive Interrupt Enable 250 #define CAN_IF1MCTL_RMTEN 0x00000200 // Remote Enable 251 #define CAN_IF1MCTL_TXRQST 0x00000100 // Transmit Request 252 #define CAN_IF1MCTL_EOB 0x00000080 // End of Buffer 253 #define CAN_IF1MCTL_DLC_M 0x0000000F // Data Length Code 254 #define CAN_IF1MCTL_DLC_S 0 255 256 //***************************************************************************** 257 // 258 // The following are defines for the bit fields in the CAN_O_IF1DA1 register. 259 // 260 //***************************************************************************** 261 #define CAN_IF1DA1_DATA_M 0x0000FFFF // Data 262 #define CAN_IF1DA1_DATA_S 0 263 264 //***************************************************************************** 265 // 266 // The following are defines for the bit fields in the CAN_O_IF1DA2 register. 267 // 268 //***************************************************************************** 269 #define CAN_IF1DA2_DATA_M 0x0000FFFF // Data 270 #define CAN_IF1DA2_DATA_S 0 271 272 //***************************************************************************** 273 // 274 // The following are defines for the bit fields in the CAN_O_IF1DB1 register. 275 // 276 //***************************************************************************** 277 #define CAN_IF1DB1_DATA_M 0x0000FFFF // Data 278 #define CAN_IF1DB1_DATA_S 0 279 280 //***************************************************************************** 281 // 282 // The following are defines for the bit fields in the CAN_O_IF1DB2 register. 283 // 284 //***************************************************************************** 285 #define CAN_IF1DB2_DATA_M 0x0000FFFF // Data 286 #define CAN_IF1DB2_DATA_S 0 287 288 //***************************************************************************** 289 // 290 // The following are defines for the bit fields in the CAN_O_IF2CRQ register. 291 // 292 //***************************************************************************** 293 #define CAN_IF2CRQ_BUSY 0x00008000 // Busy Flag 294 #define CAN_IF2CRQ_MNUM_M 0x0000003F // Message Number 295 #define CAN_IF2CRQ_MNUM_S 0 296 297 //***************************************************************************** 298 // 299 // The following are defines for the bit fields in the CAN_O_IF2CMSK register. 300 // 301 //***************************************************************************** 302 #define CAN_IF2CMSK_WRNRD 0x00000080 // Write, Not Read 303 #define CAN_IF2CMSK_MASK 0x00000040 // Access Mask Bits 304 #define CAN_IF2CMSK_ARB 0x00000020 // Access Arbitration Bits 305 #define CAN_IF2CMSK_CONTROL 0x00000010 // Access Control Bits 306 #define CAN_IF2CMSK_CLRINTPND 0x00000008 // Clear Interrupt Pending Bit 307 #define CAN_IF2CMSK_NEWDAT 0x00000004 // Access New Data 308 #define CAN_IF2CMSK_TXRQST 0x00000004 // Access Transmission Request 309 #define CAN_IF2CMSK_DATAA 0x00000002 // Access Data Byte 0 to 3 310 #define CAN_IF2CMSK_DATAB 0x00000001 // Access Data Byte 4 to 7 311 312 //***************************************************************************** 313 // 314 // The following are defines for the bit fields in the CAN_O_IF2MSK1 register. 315 // 316 //***************************************************************************** 317 #define CAN_IF2MSK1_IDMSK_M 0x0000FFFF // Identifier Mask 318 #define CAN_IF2MSK1_IDMSK_S 0 319 320 //***************************************************************************** 321 // 322 // The following are defines for the bit fields in the CAN_O_IF2MSK2 register. 323 // 324 //***************************************************************************** 325 #define CAN_IF2MSK2_MXTD 0x00008000 // Mask Extended Identifier 326 #define CAN_IF2MSK2_MDIR 0x00004000 // Mask Message Direction 327 #define CAN_IF2MSK2_IDMSK_M 0x00001FFF // Identifier Mask 328 #define CAN_IF2MSK2_IDMSK_S 0 329 330 //***************************************************************************** 331 // 332 // The following are defines for the bit fields in the CAN_O_IF2ARB1 register. 333 // 334 //***************************************************************************** 335 #define CAN_IF2ARB1_ID_M 0x0000FFFF // Message Identifier 336 #define CAN_IF2ARB1_ID_S 0 337 338 //***************************************************************************** 339 // 340 // The following are defines for the bit fields in the CAN_O_IF2ARB2 register. 341 // 342 //***************************************************************************** 343 #define CAN_IF2ARB2_MSGVAL 0x00008000 // Message Valid 344 #define CAN_IF2ARB2_XTD 0x00004000 // Extended Identifier 345 #define CAN_IF2ARB2_DIR 0x00002000 // Message Direction 346 #define CAN_IF2ARB2_ID_M 0x00001FFF // Message Identifier 347 #define CAN_IF2ARB2_ID_S 0 348 349 //***************************************************************************** 350 // 351 // The following are defines for the bit fields in the CAN_O_IF2MCTL register. 352 // 353 //***************************************************************************** 354 #define CAN_IF2MCTL_NEWDAT 0x00008000 // New Data 355 #define CAN_IF2MCTL_MSGLST 0x00004000 // Message Lost 356 #define CAN_IF2MCTL_INTPND 0x00002000 // Interrupt Pending 357 #define CAN_IF2MCTL_UMASK 0x00001000 // Use Acceptance Mask 358 #define CAN_IF2MCTL_TXIE 0x00000800 // Transmit Interrupt Enable 359 #define CAN_IF2MCTL_RXIE 0x00000400 // Receive Interrupt Enable 360 #define CAN_IF2MCTL_RMTEN 0x00000200 // Remote Enable 361 #define CAN_IF2MCTL_TXRQST 0x00000100 // Transmit Request 362 #define CAN_IF2MCTL_EOB 0x00000080 // End of Buffer 363 #define CAN_IF2MCTL_DLC_M 0x0000000F // Data Length Code 364 #define CAN_IF2MCTL_DLC_S 0 365 366 //***************************************************************************** 367 // 368 // The following are defines for the bit fields in the CAN_O_IF2DA1 register. 369 // 370 //***************************************************************************** 371 #define CAN_IF2DA1_DATA_M 0x0000FFFF // Data 372 #define CAN_IF2DA1_DATA_S 0 373 374 //***************************************************************************** 375 // 376 // The following are defines for the bit fields in the CAN_O_IF2DA2 register. 377 // 378 //***************************************************************************** 379 #define CAN_IF2DA2_DATA_M 0x0000FFFF // Data 380 #define CAN_IF2DA2_DATA_S 0 381 382 //***************************************************************************** 383 // 384 // The following are defines for the bit fields in the CAN_O_IF2DB1 register. 385 // 386 //***************************************************************************** 387 #define CAN_IF2DB1_DATA_M 0x0000FFFF // Data 388 #define CAN_IF2DB1_DATA_S 0 389 390 //***************************************************************************** 391 // 392 // The following are defines for the bit fields in the CAN_O_IF2DB2 register. 393 // 394 //***************************************************************************** 395 #define CAN_IF2DB2_DATA_M 0x0000FFFF // Data 396 #define CAN_IF2DB2_DATA_S 0 397 398 //***************************************************************************** 399 // 400 // The following are defines for the bit fields in the CAN_O_TXRQ1 register. 401 // 402 //***************************************************************************** 403 #define CAN_TXRQ1_TXRQST_M 0x0000FFFF // Transmission Request Bits 404 #define CAN_TXRQ1_TXRQST_S 0 405 406 //***************************************************************************** 407 // 408 // The following are defines for the bit fields in the CAN_O_TXRQ2 register. 409 // 410 //***************************************************************************** 411 #define CAN_TXRQ2_TXRQST_M 0x0000FFFF // Transmission Request Bits 412 #define CAN_TXRQ2_TXRQST_S 0 413 414 //***************************************************************************** 415 // 416 // The following are defines for the bit fields in the CAN_O_NWDA1 register. 417 // 418 //***************************************************************************** 419 #define CAN_NWDA1_NEWDAT_M 0x0000FFFF // New Data Bits 420 #define CAN_NWDA1_NEWDAT_S 0 421 422 //***************************************************************************** 423 // 424 // The following are defines for the bit fields in the CAN_O_NWDA2 register. 425 // 426 //***************************************************************************** 427 #define CAN_NWDA2_NEWDAT_M 0x0000FFFF // New Data Bits 428 #define CAN_NWDA2_NEWDAT_S 0 429 430 //***************************************************************************** 431 // 432 // The following are defines for the bit fields in the CAN_O_MSG1INT register. 433 // 434 //***************************************************************************** 435 #define CAN_MSG1INT_INTPND_M 0x0000FFFF // Interrupt Pending Bits 436 #define CAN_MSG1INT_INTPND_S 0 437 438 //***************************************************************************** 439 // 440 // The following are defines for the bit fields in the CAN_O_MSG2INT register. 441 // 442 //***************************************************************************** 443 #define CAN_MSG2INT_INTPND_M 0x0000FFFF // Interrupt Pending Bits 444 #define CAN_MSG2INT_INTPND_S 0 445 446 //***************************************************************************** 447 // 448 // The following are defines for the bit fields in the CAN_O_MSG1VAL register. 449 // 450 //***************************************************************************** 451 #define CAN_MSG1VAL_MSGVAL_M 0x0000FFFF // Message Valid Bits 452 #define CAN_MSG1VAL_MSGVAL_S 0 453 454 //***************************************************************************** 455 // 456 // The following are defines for the bit fields in the CAN_O_MSG2VAL register. 457 // 458 //***************************************************************************** 459 #define CAN_MSG2VAL_MSGVAL_M 0x0000FFFF // Message Valid Bits 460 #define CAN_MSG2VAL_MSGVAL_S 0 461 462 #endif // __HW_CAN_H__ 463