1 //***************************************************************************** 2 // 3 // hw_eeprom.h - Macros used when accessing the EEPROM controller. 4 // 5 // Copyright (c) 2011-2017 Texas Instruments Incorporated. All rights reserved. 6 // Software License Agreement 7 // 8 // Redistribution and use in source and binary forms, with or without 9 // modification, are permitted provided that the following conditions 10 // are met: 11 // 12 // Redistributions of source code must retain the above copyright 13 // notice, this list of conditions and the following disclaimer. 14 // 15 // Redistributions in binary form must reproduce the above copyright 16 // notice, this list of conditions and the following disclaimer in the 17 // documentation and/or other materials provided with the 18 // distribution. 19 // 20 // Neither the name of Texas Instruments Incorporated nor the names of 21 // its contributors may be used to endorse or promote products derived 22 // from this software without specific prior written permission. 23 // 24 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 27 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 28 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 29 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 30 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 34 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 // 36 // This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. 37 // 38 //***************************************************************************** 39 40 #ifndef __HW_EEPROM_H__ 41 #define __HW_EEPROM_H__ 42 43 //***************************************************************************** 44 // 45 // The following are defines for the EEPROM register offsets. 46 // 47 //***************************************************************************** 48 #define EEPROM_EESIZE 0x400AF000 // EEPROM Size Information 49 #define EEPROM_EEBLOCK 0x400AF004 // EEPROM Current Block 50 #define EEPROM_EEOFFSET 0x400AF008 // EEPROM Current Offset 51 #define EEPROM_EERDWR 0x400AF010 // EEPROM Read-Write 52 #define EEPROM_EERDWRINC 0x400AF014 // EEPROM Read-Write with Increment 53 #define EEPROM_EEDONE 0x400AF018 // EEPROM Done Status 54 #define EEPROM_EESUPP 0x400AF01C // EEPROM Support Control and 55 // Status 56 #define EEPROM_EEUNLOCK 0x400AF020 // EEPROM Unlock 57 #define EEPROM_EEPROT 0x400AF030 // EEPROM Protection 58 #define EEPROM_EEPASS0 0x400AF034 // EEPROM Password 59 #define EEPROM_EEPASS1 0x400AF038 // EEPROM Password 60 #define EEPROM_EEPASS2 0x400AF03C // EEPROM Password 61 #define EEPROM_EEINT 0x400AF040 // EEPROM Interrupt 62 #define EEPROM_EEHIDE0 0x400AF050 // EEPROM Block Hide 0 63 #define EEPROM_EEHIDE 0x400AF050 // EEPROM Block Hide 64 #define EEPROM_EEHIDE1 0x400AF054 // EEPROM Block Hide 1 65 #define EEPROM_EEHIDE2 0x400AF058 // EEPROM Block Hide 2 66 #define EEPROM_EEDBGME 0x400AF080 // EEPROM Debug Mass Erase 67 #define EEPROM_PP 0x400AFFC0 // EEPROM Peripheral Properties 68 69 //***************************************************************************** 70 // 71 // The following are defines for the bit fields in the EEPROM_EESIZE register. 72 // 73 //***************************************************************************** 74 #define EEPROM_EESIZE_WORDCNT_M 0x0000FFFF // Number of 32-Bit Words 75 #define EEPROM_EESIZE_BLKCNT_M 0x07FF0000 // Number of 16-Word Blocks 76 #define EEPROM_EESIZE_WORDCNT_S 0 77 #define EEPROM_EESIZE_BLKCNT_S 16 78 79 //***************************************************************************** 80 // 81 // The following are defines for the bit fields in the EEPROM_EEBLOCK register. 82 // 83 //***************************************************************************** 84 #define EEPROM_EEBLOCK_BLOCK_M 0x0000FFFF // Current Block 85 #define EEPROM_EEBLOCK_BLOCK_S 0 86 87 //***************************************************************************** 88 // 89 // The following are defines for the bit fields in the EEPROM_EEOFFSET 90 // register. 91 // 92 //***************************************************************************** 93 #define EEPROM_EEOFFSET_OFFSET_M \ 94 0x0000000F // Current Address Offset 95 #define EEPROM_EEOFFSET_OFFSET_S \ 96 0 97 98 //***************************************************************************** 99 // 100 // The following are defines for the bit fields in the EEPROM_EERDWR register. 101 // 102 //***************************************************************************** 103 #define EEPROM_EERDWR_VALUE_M 0xFFFFFFFF // EEPROM Read or Write Data 104 #define EEPROM_EERDWR_VALUE_S 0 105 106 //***************************************************************************** 107 // 108 // The following are defines for the bit fields in the EEPROM_EERDWRINC 109 // register. 110 // 111 //***************************************************************************** 112 #define EEPROM_EERDWRINC_VALUE_M \ 113 0xFFFFFFFF // EEPROM Read or Write Data with 114 // Increment 115 #define EEPROM_EERDWRINC_VALUE_S \ 116 0 117 118 //***************************************************************************** 119 // 120 // The following are defines for the bit fields in the EEPROM_EEDONE register. 121 // 122 //***************************************************************************** 123 #define EEPROM_EEDONE_WORKING 0x00000001 // EEPROM Working 124 #define EEPROM_EEDONE_WKERASE 0x00000004 // Working on an Erase 125 #define EEPROM_EEDONE_WKCOPY 0x00000008 // Working on a Copy 126 #define EEPROM_EEDONE_NOPERM 0x00000010 // Write Without Permission 127 #define EEPROM_EEDONE_WRBUSY 0x00000020 // Write Busy 128 129 //***************************************************************************** 130 // 131 // The following are defines for the bit fields in the EEPROM_EESUPP register. 132 // 133 //***************************************************************************** 134 #define EEPROM_EESUPP_ERETRY 0x00000004 // Erase Must Be Retried 135 #define EEPROM_EESUPP_PRETRY 0x00000008 // Programming Must Be Retried 136 137 //***************************************************************************** 138 // 139 // The following are defines for the bit fields in the EEPROM_EEUNLOCK 140 // register. 141 // 142 //***************************************************************************** 143 #define EEPROM_EEUNLOCK_UNLOCK_M \ 144 0xFFFFFFFF // EEPROM Unlock 145 146 //***************************************************************************** 147 // 148 // The following are defines for the bit fields in the EEPROM_EEPROT register. 149 // 150 //***************************************************************************** 151 #define EEPROM_EEPROT_PROT_M 0x00000007 // Protection Control 152 #define EEPROM_EEPROT_PROT_RWNPW \ 153 0x00000000 // This setting is the default. If 154 // there is no password, the block 155 // is not protected and is readable 156 // and writable 157 #define EEPROM_EEPROT_PROT_RWPW 0x00000001 // If there is a password, the 158 // block is readable or writable 159 // only when unlocked 160 #define EEPROM_EEPROT_PROT_RONPW \ 161 0x00000002 // If there is no password, the 162 // block is readable, not writable 163 #define EEPROM_EEPROT_ACC 0x00000008 // Access Control 164 165 //***************************************************************************** 166 // 167 // The following are defines for the bit fields in the EEPROM_EEPASS0 register. 168 // 169 //***************************************************************************** 170 #define EEPROM_EEPASS0_PASS_M 0xFFFFFFFF // Password 171 #define EEPROM_EEPASS0_PASS_S 0 172 173 //***************************************************************************** 174 // 175 // The following are defines for the bit fields in the EEPROM_EEPASS1 register. 176 // 177 //***************************************************************************** 178 #define EEPROM_EEPASS1_PASS_M 0xFFFFFFFF // Password 179 #define EEPROM_EEPASS1_PASS_S 0 180 181 //***************************************************************************** 182 // 183 // The following are defines for the bit fields in the EEPROM_EEPASS2 register. 184 // 185 //***************************************************************************** 186 #define EEPROM_EEPASS2_PASS_M 0xFFFFFFFF // Password 187 #define EEPROM_EEPASS2_PASS_S 0 188 189 //***************************************************************************** 190 // 191 // The following are defines for the bit fields in the EEPROM_EEINT register. 192 // 193 //***************************************************************************** 194 #define EEPROM_EEINT_INT 0x00000001 // Interrupt Enable 195 196 //***************************************************************************** 197 // 198 // The following are defines for the bit fields in the EEPROM_EEHIDE0 register. 199 // 200 //***************************************************************************** 201 #define EEPROM_EEHIDE0_HN_M 0xFFFFFFFE // Hide Block 202 203 //***************************************************************************** 204 // 205 // The following are defines for the bit fields in the EEPROM_EEHIDE register. 206 // 207 //***************************************************************************** 208 #define EEPROM_EEHIDE_HN_M 0xFFFFFFFE // Hide Block 209 210 //***************************************************************************** 211 // 212 // The following are defines for the bit fields in the EEPROM_EEHIDE1 register. 213 // 214 //***************************************************************************** 215 #define EEPROM_EEHIDE1_HN_M 0xFFFFFFFF // Hide Block 216 217 //***************************************************************************** 218 // 219 // The following are defines for the bit fields in the EEPROM_EEHIDE2 register. 220 // 221 //***************************************************************************** 222 #define EEPROM_EEHIDE2_HN_M 0xFFFFFFFF // Hide Block 223 224 //***************************************************************************** 225 // 226 // The following are defines for the bit fields in the EEPROM_EEDBGME register. 227 // 228 //***************************************************************************** 229 #define EEPROM_EEDBGME_ME 0x00000001 // Mass Erase 230 #define EEPROM_EEDBGME_KEY_M 0xFFFF0000 // Erase Key 231 #define EEPROM_EEDBGME_KEY_S 16 232 233 //***************************************************************************** 234 // 235 // The following are defines for the bit fields in the EEPROM_PP register. 236 // 237 //***************************************************************************** 238 #define EEPROM_PP_SIZE_M 0x0000FFFF // EEPROM Size 239 #define EEPROM_PP_SIZE_64 0x00000000 // 64 bytes of EEPROM 240 #define EEPROM_PP_SIZE_128 0x00000001 // 128 bytes of EEPROM 241 #define EEPROM_PP_SIZE_256 0x00000003 // 256 bytes of EEPROM 242 #define EEPROM_PP_SIZE_512 0x00000007 // 512 bytes of EEPROM 243 #define EEPROM_PP_SIZE_1K 0x0000000F // 1 KB of EEPROM 244 #define EEPROM_PP_SIZE_2K 0x0000001F // 2 KB of EEPROM 245 #define EEPROM_PP_SIZE_3K 0x0000003F // 3 KB of EEPROM 246 #define EEPROM_PP_SIZE_4K 0x0000007F // 4 KB of EEPROM 247 #define EEPROM_PP_SIZE_5K 0x000000FF // 5 KB of EEPROM 248 #define EEPROM_PP_SIZE_6K 0x000001FF // 6 KB of EEPROM 249 #define EEPROM_PP_SIZE_S 0 250 251 #endif // __HW_EEPROM_H__ 252