1 //***************************************************************************** 2 // 3 // hw_epi.h - Macros for use in accessing the EPI registers. 4 // 5 // Copyright (c) 2008-2017 Texas Instruments Incorporated. All rights reserved. 6 // Software License Agreement 7 // 8 // Redistribution and use in source and binary forms, with or without 9 // modification, are permitted provided that the following conditions 10 // are met: 11 // 12 // Redistributions of source code must retain the above copyright 13 // notice, this list of conditions and the following disclaimer. 14 // 15 // Redistributions in binary form must reproduce the above copyright 16 // notice, this list of conditions and the following disclaimer in the 17 // documentation and/or other materials provided with the 18 // distribution. 19 // 20 // Neither the name of Texas Instruments Incorporated nor the names of 21 // its contributors may be used to endorse or promote products derived 22 // from this software without specific prior written permission. 23 // 24 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 27 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 28 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 29 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 30 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 34 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 // 36 // This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. 37 // 38 //***************************************************************************** 39 40 #ifndef __HW_EPI_H__ 41 #define __HW_EPI_H__ 42 43 //***************************************************************************** 44 // 45 // The following are defines for the External Peripheral Interface register 46 // offsets. 47 // 48 //***************************************************************************** 49 #define EPI_O_CFG 0x00000000 // EPI Configuration 50 #define EPI_O_BAUD 0x00000004 // EPI Main Baud Rate 51 #define EPI_O_BAUD2 0x00000008 // EPI Main Baud Rate 52 #define EPI_O_HB16CFG 0x00000010 // EPI Host-Bus 16 Configuration 53 #define EPI_O_GPCFG 0x00000010 // EPI General-Purpose 54 // Configuration 55 #define EPI_O_SDRAMCFG 0x00000010 // EPI SDRAM Configuration 56 #define EPI_O_HB8CFG 0x00000010 // EPI Host-Bus 8 Configuration 57 #define EPI_O_HB8CFG2 0x00000014 // EPI Host-Bus 8 Configuration 2 58 #define EPI_O_HB16CFG2 0x00000014 // EPI Host-Bus 16 Configuration 2 59 #define EPI_O_ADDRMAP 0x0000001C // EPI Address Map 60 #define EPI_O_RSIZE0 0x00000020 // EPI Read Size 0 61 #define EPI_O_RADDR0 0x00000024 // EPI Read Address 0 62 #define EPI_O_RPSTD0 0x00000028 // EPI Non-Blocking Read Data 0 63 #define EPI_O_RSIZE1 0x00000030 // EPI Read Size 1 64 #define EPI_O_RADDR1 0x00000034 // EPI Read Address 1 65 #define EPI_O_RPSTD1 0x00000038 // EPI Non-Blocking Read Data 1 66 #define EPI_O_STAT 0x00000060 // EPI Status 67 #define EPI_O_RFIFOCNT 0x0000006C // EPI Read FIFO Count 68 #define EPI_O_READFIFO0 0x00000070 // EPI Read FIFO 69 #define EPI_O_READFIFO1 0x00000074 // EPI Read FIFO Alias 1 70 #define EPI_O_READFIFO2 0x00000078 // EPI Read FIFO Alias 2 71 #define EPI_O_READFIFO3 0x0000007C // EPI Read FIFO Alias 3 72 #define EPI_O_READFIFO4 0x00000080 // EPI Read FIFO Alias 4 73 #define EPI_O_READFIFO5 0x00000084 // EPI Read FIFO Alias 5 74 #define EPI_O_READFIFO6 0x00000088 // EPI Read FIFO Alias 6 75 #define EPI_O_READFIFO7 0x0000008C // EPI Read FIFO Alias 7 76 #define EPI_O_FIFOLVL 0x00000200 // EPI FIFO Level Selects 77 #define EPI_O_WFIFOCNT 0x00000204 // EPI Write FIFO Count 78 #define EPI_O_DMATXCNT 0x00000208 // EPI DMA Transmit Count 79 #define EPI_O_IM 0x00000210 // EPI Interrupt Mask 80 #define EPI_O_RIS 0x00000214 // EPI Raw Interrupt Status 81 #define EPI_O_MIS 0x00000218 // EPI Masked Interrupt Status 82 #define EPI_O_EISC 0x0000021C // EPI Error and Interrupt Status 83 // and Clear 84 #define EPI_O_HB8CFG3 0x00000308 // EPI Host-Bus 8 Configuration 3 85 #define EPI_O_HB16CFG3 0x00000308 // EPI Host-Bus 16 Configuration 3 86 #define EPI_O_HB16CFG4 0x0000030C // EPI Host-Bus 16 Configuration 4 87 #define EPI_O_HB8CFG4 0x0000030C // EPI Host-Bus 8 Configuration 4 88 #define EPI_O_HB8TIME 0x00000310 // EPI Host-Bus 8 Timing Extension 89 #define EPI_O_HB16TIME 0x00000310 // EPI Host-Bus 16 Timing Extension 90 #define EPI_O_HB8TIME2 0x00000314 // EPI Host-Bus 8 Timing Extension 91 #define EPI_O_HB16TIME2 0x00000314 // EPI Host-Bus 16 Timing Extension 92 #define EPI_O_HB16TIME3 0x00000318 // EPI Host-Bus 16 Timing Extension 93 #define EPI_O_HB8TIME3 0x00000318 // EPI Host-Bus 8 Timing Extension 94 #define EPI_O_HB8TIME4 0x0000031C // EPI Host-Bus 8 Timing Extension 95 #define EPI_O_HB16TIME4 0x0000031C // EPI Host-Bus 16 Timing Extension 96 #define EPI_O_HBPSRAM 0x00000360 // EPI Host-Bus PSRAM 97 98 //***************************************************************************** 99 // 100 // The following are defines for the bit fields in the EPI_O_CFG register. 101 // 102 //***************************************************************************** 103 #define EPI_CFG_INTDIV 0x00000100 // Integer Clock Divider Enable 104 #define EPI_CFG_BLKEN 0x00000010 // Block Enable 105 #define EPI_CFG_MODE_M 0x0000000F // Mode Select 106 #define EPI_CFG_MODE_NONE 0x00000000 // General Purpose 107 #define EPI_CFG_MODE_SDRAM 0x00000001 // SDRAM 108 #define EPI_CFG_MODE_HB8 0x00000002 // 8-Bit Host-Bus (HB8) 109 #define EPI_CFG_MODE_HB16 0x00000003 // 16-Bit Host-Bus (HB16) 110 111 //***************************************************************************** 112 // 113 // The following are defines for the bit fields in the EPI_O_BAUD register. 114 // 115 //***************************************************************************** 116 #define EPI_BAUD_COUNT1_M 0xFFFF0000 // Baud Rate Counter 1 117 #define EPI_BAUD_COUNT0_M 0x0000FFFF // Baud Rate Counter 0 118 #define EPI_BAUD_COUNT1_S 16 119 #define EPI_BAUD_COUNT0_S 0 120 121 //***************************************************************************** 122 // 123 // The following are defines for the bit fields in the EPI_O_BAUD2 register. 124 // 125 //***************************************************************************** 126 #define EPI_BAUD2_COUNT1_M 0xFFFF0000 // CS3n Baud Rate Counter 1 127 #define EPI_BAUD2_COUNT0_M 0x0000FFFF // CS2n Baud Rate Counter 0 128 #define EPI_BAUD2_COUNT1_S 16 129 #define EPI_BAUD2_COUNT0_S 0 130 131 //***************************************************************************** 132 // 133 // The following are defines for the bit fields in the EPI_O_HB16CFG register. 134 // 135 //***************************************************************************** 136 #define EPI_HB16CFG_CLKGATE 0x80000000 // Clock Gated 137 #define EPI_HB16CFG_CLKGATEI 0x40000000 // Clock Gated Idle 138 #define EPI_HB16CFG_CLKINV 0x20000000 // Invert Output Clock Enable 139 #define EPI_HB16CFG_RDYEN 0x10000000 // Input Ready Enable 140 #define EPI_HB16CFG_IRDYINV 0x08000000 // Input Ready Invert 141 #define EPI_HB16CFG_XFFEN 0x00800000 // External FIFO FULL Enable 142 #define EPI_HB16CFG_XFEEN 0x00400000 // External FIFO EMPTY Enable 143 #define EPI_HB16CFG_WRHIGH 0x00200000 // WRITE Strobe Polarity 144 #define EPI_HB16CFG_RDHIGH 0x00100000 // READ Strobe Polarity 145 #define EPI_HB16CFG_ALEHIGH 0x00080000 // ALE Strobe Polarity 146 #define EPI_HB16CFG_WRCRE 0x00040000 // PSRAM Configuration Register 147 // Write 148 #define EPI_HB16CFG_RDCRE 0x00020000 // PSRAM Configuration Register 149 // Read 150 #define EPI_HB16CFG_BURST 0x00010000 // Burst Mode 151 #define EPI_HB16CFG_MAXWAIT_M 0x0000FF00 // Maximum Wait 152 #define EPI_HB16CFG_WRWS_M 0x000000C0 // Write Wait States 153 #define EPI_HB16CFG_WRWS_2 0x00000000 // Active WRn is 2 EPI clocks 154 #define EPI_HB16CFG_WRWS_4 0x00000040 // Active WRn is 4 EPI clocks 155 #define EPI_HB16CFG_WRWS_6 0x00000080 // Active WRn is 6 EPI clocks 156 #define EPI_HB16CFG_WRWS_8 0x000000C0 // Active WRn is 8 EPI clocks 157 #define EPI_HB16CFG_RDWS_M 0x00000030 // Read Wait States 158 #define EPI_HB16CFG_RDWS_2 0x00000000 // Active RDn is 2 EPI clocks 159 #define EPI_HB16CFG_RDWS_4 0x00000010 // Active RDn is 4 EPI clocks 160 #define EPI_HB16CFG_RDWS_6 0x00000020 // Active RDn is 6 EPI clocks 161 #define EPI_HB16CFG_RDWS_8 0x00000030 // Active RDn is 8 EPI clocks 162 #define EPI_HB16CFG_BSEL 0x00000004 // Byte Select Configuration 163 #define EPI_HB16CFG_MODE_M 0x00000003 // Host Bus Sub-Mode 164 #define EPI_HB16CFG_MODE_ADMUX 0x00000000 // ADMUX - AD[15:0] 165 #define EPI_HB16CFG_MODE_ADNMUX 0x00000001 // ADNONMUX - D[15:0] 166 #define EPI_HB16CFG_MODE_SRAM 0x00000002 // Continuous Read - D[15:0] 167 #define EPI_HB16CFG_MODE_XFIFO 0x00000003 // XFIFO - D[15:0] 168 #define EPI_HB16CFG_MAXWAIT_S 8 169 170 //***************************************************************************** 171 // 172 // The following are defines for the bit fields in the EPI_O_GPCFG register. 173 // 174 //***************************************************************************** 175 #define EPI_GPCFG_CLKPIN 0x80000000 // Clock Pin 176 #define EPI_GPCFG_CLKGATE 0x40000000 // Clock Gated 177 #define EPI_GPCFG_FRM50 0x04000000 // 50/50 Frame 178 #define EPI_GPCFG_FRMCNT_M 0x03C00000 // Frame Count 179 #define EPI_GPCFG_WR2CYC 0x00080000 // 2-Cycle Writes 180 #define EPI_GPCFG_ASIZE_M 0x00000030 // Address Bus Size 181 #define EPI_GPCFG_ASIZE_NONE 0x00000000 // No address 182 #define EPI_GPCFG_ASIZE_4BIT 0x00000010 // Up to 4 bits wide 183 #define EPI_GPCFG_ASIZE_12BIT 0x00000020 // Up to 12 bits wide. This size 184 // cannot be used with 24-bit data 185 #define EPI_GPCFG_ASIZE_20BIT 0x00000030 // Up to 20 bits wide. This size 186 // cannot be used with data sizes 187 // other than 8 188 #define EPI_GPCFG_DSIZE_M 0x00000003 // Size of Data Bus 189 #define EPI_GPCFG_DSIZE_4BIT 0x00000000 // 8 Bits Wide (EPI0S0 to EPI0S7) 190 #define EPI_GPCFG_DSIZE_16BIT 0x00000001 // 16 Bits Wide (EPI0S0 to EPI0S15) 191 #define EPI_GPCFG_DSIZE_24BIT 0x00000002 // 24 Bits Wide (EPI0S0 to EPI0S23) 192 #define EPI_GPCFG_DSIZE_32BIT 0x00000003 // 32 Bits Wide (EPI0S0 to EPI0S31) 193 #define EPI_GPCFG_FRMCNT_S 22 194 195 //***************************************************************************** 196 // 197 // The following are defines for the bit fields in the EPI_O_SDRAMCFG register. 198 // 199 //***************************************************************************** 200 #define EPI_SDRAMCFG_FREQ_M 0xC0000000 // EPI Frequency Range 201 #define EPI_SDRAMCFG_FREQ_NONE 0x00000000 // 0 - 15 MHz 202 #define EPI_SDRAMCFG_FREQ_15MHZ 0x40000000 // 15 - 30 MHz 203 #define EPI_SDRAMCFG_FREQ_30MHZ 0x80000000 // 30 - 50 MHz 204 #define EPI_SDRAMCFG_RFSH_M 0x07FF0000 // Refresh Counter 205 #define EPI_SDRAMCFG_SLEEP 0x00000200 // Sleep Mode 206 #define EPI_SDRAMCFG_SIZE_M 0x00000003 // Size of SDRAM 207 #define EPI_SDRAMCFG_SIZE_8MB 0x00000000 // 64 megabits (8MB) 208 #define EPI_SDRAMCFG_SIZE_16MB 0x00000001 // 128 megabits (16MB) 209 #define EPI_SDRAMCFG_SIZE_32MB 0x00000002 // 256 megabits (32MB) 210 #define EPI_SDRAMCFG_SIZE_64MB 0x00000003 // 512 megabits (64MB) 211 #define EPI_SDRAMCFG_RFSH_S 16 212 213 //***************************************************************************** 214 // 215 // The following are defines for the bit fields in the EPI_O_HB8CFG register. 216 // 217 //***************************************************************************** 218 #define EPI_HB8CFG_CLKGATE 0x80000000 // Clock Gated 219 #define EPI_HB8CFG_CLKGATEI 0x40000000 // Clock Gated when Idle 220 #define EPI_HB8CFG_CLKINV 0x20000000 // Invert Output Clock Enable 221 #define EPI_HB8CFG_RDYEN 0x10000000 // Input Ready Enable 222 #define EPI_HB8CFG_IRDYINV 0x08000000 // Input Ready Invert 223 #define EPI_HB8CFG_XFFEN 0x00800000 // External FIFO FULL Enable 224 #define EPI_HB8CFG_XFEEN 0x00400000 // External FIFO EMPTY Enable 225 #define EPI_HB8CFG_WRHIGH 0x00200000 // WRITE Strobe Polarity 226 #define EPI_HB8CFG_RDHIGH 0x00100000 // READ Strobe Polarity 227 #define EPI_HB8CFG_ALEHIGH 0x00080000 // ALE Strobe Polarity 228 #define EPI_HB8CFG_MAXWAIT_M 0x0000FF00 // Maximum Wait 229 #define EPI_HB8CFG_WRWS_M 0x000000C0 // Write Wait States 230 #define EPI_HB8CFG_WRWS_2 0x00000000 // Active WRn is 2 EPI clocks 231 #define EPI_HB8CFG_WRWS_4 0x00000040 // Active WRn is 4 EPI clocks 232 #define EPI_HB8CFG_WRWS_6 0x00000080 // Active WRn is 6 EPI clocks 233 #define EPI_HB8CFG_WRWS_8 0x000000C0 // Active WRn is 8 EPI clocks 234 #define EPI_HB8CFG_RDWS_M 0x00000030 // Read Wait States 235 #define EPI_HB8CFG_RDWS_2 0x00000000 // Active RDn is 2 EPI clocks 236 #define EPI_HB8CFG_RDWS_4 0x00000010 // Active RDn is 4 EPI clocks 237 #define EPI_HB8CFG_RDWS_6 0x00000020 // Active RDn is 6 EPI clocks 238 #define EPI_HB8CFG_RDWS_8 0x00000030 // Active RDn is 8 EPI clocks 239 #define EPI_HB8CFG_MODE_M 0x00000003 // Host Bus Sub-Mode 240 #define EPI_HB8CFG_MODE_MUX 0x00000000 // ADMUX - AD[7:0] 241 #define EPI_HB8CFG_MODE_NMUX 0x00000001 // ADNONMUX - D[7:0] 242 #define EPI_HB8CFG_MODE_SRAM 0x00000002 // Continuous Read - D[7:0] 243 #define EPI_HB8CFG_MODE_FIFO 0x00000003 // XFIFO - D[7:0] 244 #define EPI_HB8CFG_MAXWAIT_S 8 245 246 //***************************************************************************** 247 // 248 // The following are defines for the bit fields in the EPI_O_HB8CFG2 register. 249 // 250 //***************************************************************************** 251 #define EPI_HB8CFG2_CSCFGEXT 0x08000000 // Chip Select Extended 252 // Configuration 253 #define EPI_HB8CFG2_CSBAUD 0x04000000 // Chip Select Baud Rate and 254 // Multiple Sub-Mode Configuration 255 // enable 256 #define EPI_HB8CFG2_CSCFG_M 0x03000000 // Chip Select Configuration 257 #define EPI_HB8CFG2_CSCFG_ALE 0x00000000 // ALE Configuration 258 #define EPI_HB8CFG2_CSCFG_CS 0x01000000 // CSn Configuration 259 #define EPI_HB8CFG2_CSCFG_DCS 0x02000000 // Dual CSn Configuration 260 #define EPI_HB8CFG2_CSCFG_ADCS 0x03000000 // ALE with Dual CSn Configuration 261 #define EPI_HB8CFG2_WRHIGH 0x00200000 // CS1n WRITE Strobe Polarity 262 #define EPI_HB8CFG2_RDHIGH 0x00100000 // CS1n READ Strobe Polarity 263 #define EPI_HB8CFG2_ALEHIGH 0x00080000 // CS1n ALE Strobe Polarity 264 #define EPI_HB8CFG2_WRWS_M 0x000000C0 // CS1n Write Wait States 265 #define EPI_HB8CFG2_WRWS_2 0x00000000 // Active WRn is 2 EPI clocks 266 #define EPI_HB8CFG2_WRWS_4 0x00000040 // Active WRn is 4 EPI clocks 267 #define EPI_HB8CFG2_WRWS_6 0x00000080 // Active WRn is 6 EPI clocks 268 #define EPI_HB8CFG2_WRWS_8 0x000000C0 // Active WRn is 8 EPI clocks 269 #define EPI_HB8CFG2_RDWS_M 0x00000030 // CS1n Read Wait States 270 #define EPI_HB8CFG2_RDWS_2 0x00000000 // Active RDn is 2 EPI clocks 271 #define EPI_HB8CFG2_RDWS_4 0x00000010 // Active RDn is 4 EPI clocks 272 #define EPI_HB8CFG2_RDWS_6 0x00000020 // Active RDn is 6 EPI clocks 273 #define EPI_HB8CFG2_RDWS_8 0x00000030 // Active RDn is 8 EPI clocks 274 #define EPI_HB8CFG2_MODE_M 0x00000003 // CS1n Host Bus Sub-Mode 275 #define EPI_HB8CFG2_MODE_ADMUX 0x00000000 // ADMUX - AD[7:0] 276 #define EPI_HB8CFG2_MODE_AD 0x00000001 // ADNONMUX - D[7:0] 277 278 //***************************************************************************** 279 // 280 // The following are defines for the bit fields in the EPI_O_HB16CFG2 register. 281 // 282 //***************************************************************************** 283 #define EPI_HB16CFG2_CSCFGEXT 0x08000000 // Chip Select Extended 284 // Configuration 285 #define EPI_HB16CFG2_CSBAUD 0x04000000 // Chip Select Baud Rate and 286 // Multiple Sub-Mode Configuration 287 // enable 288 #define EPI_HB16CFG2_CSCFG_M 0x03000000 // Chip Select Configuration 289 #define EPI_HB16CFG2_CSCFG_ALE 0x00000000 // ALE Configuration 290 #define EPI_HB16CFG2_CSCFG_CS 0x01000000 // CSn Configuration 291 #define EPI_HB16CFG2_CSCFG_DCS 0x02000000 // Dual CSn Configuration 292 #define EPI_HB16CFG2_CSCFG_ADCS 0x03000000 // ALE with Dual CSn Configuration 293 #define EPI_HB16CFG2_WRHIGH 0x00200000 // CS1n WRITE Strobe Polarity 294 #define EPI_HB16CFG2_RDHIGH 0x00100000 // CS1n READ Strobe Polarity 295 #define EPI_HB16CFG2_ALEHIGH 0x00080000 // CS1n ALE Strobe Polarity 296 #define EPI_HB16CFG2_WRCRE 0x00040000 // CS1n PSRAM Configuration 297 // Register Write 298 #define EPI_HB16CFG2_RDCRE 0x00020000 // CS1n PSRAM Configuration 299 // Register Read 300 #define EPI_HB16CFG2_BURST 0x00010000 // CS1n Burst Mode 301 #define EPI_HB16CFG2_WRWS_M 0x000000C0 // CS1n Write Wait States 302 #define EPI_HB16CFG2_WRWS_2 0x00000000 // Active WRn is 2 EPI clocks 303 #define EPI_HB16CFG2_WRWS_4 0x00000040 // Active WRn is 4 EPI clocks 304 #define EPI_HB16CFG2_WRWS_6 0x00000080 // Active WRn is 6 EPI clocks 305 #define EPI_HB16CFG2_WRWS_8 0x000000C0 // Active WRn is 8 EPI clocks 306 #define EPI_HB16CFG2_RDWS_M 0x00000030 // CS1n Read Wait States 307 #define EPI_HB16CFG2_RDWS_2 0x00000000 // Active RDn is 2 EPI clocks 308 #define EPI_HB16CFG2_RDWS_4 0x00000010 // Active RDn is 4 EPI clocks 309 #define EPI_HB16CFG2_RDWS_6 0x00000020 // Active RDn is 6 EPI clocks 310 #define EPI_HB16CFG2_RDWS_8 0x00000030 // Active RDn is 8 EPI clocks 311 #define EPI_HB16CFG2_MODE_M 0x00000003 // CS1n Host Bus Sub-Mode 312 #define EPI_HB16CFG2_MODE_ADMUX 0x00000000 // ADMUX - AD[15:0] 313 #define EPI_HB16CFG2_MODE_AD 0x00000001 // ADNONMUX - D[15:0] 314 315 //***************************************************************************** 316 // 317 // The following are defines for the bit fields in the EPI_O_ADDRMAP register. 318 // 319 //***************************************************************************** 320 #define EPI_ADDRMAP_ECSZ_M 0x00000C00 // External Code Size 321 #define EPI_ADDRMAP_ECSZ_256B 0x00000000 // 256 bytes; lower address range: 322 // 0x00 to 0xFF 323 #define EPI_ADDRMAP_ECSZ_64KB 0x00000400 // 64 KB; lower address range: 324 // 0x0000 to 0xFFFF 325 #define EPI_ADDRMAP_ECSZ_16MB 0x00000800 // 16 MB; lower address range: 326 // 0x00.0000 to 0xFF.FFFF 327 #define EPI_ADDRMAP_ECSZ_256MB 0x00000C00 // 256MB; lower address range: 328 // 0x000.0000 to 0x0FFF.FFFF 329 #define EPI_ADDRMAP_ECADR_M 0x00000300 // External Code Address 330 #define EPI_ADDRMAP_ECADR_NONE 0x00000000 // Not mapped 331 #define EPI_ADDRMAP_ECADR_1000 0x00000100 // At 0x1000.0000 332 #define EPI_ADDRMAP_EPSZ_M 0x000000C0 // External Peripheral Size 333 #define EPI_ADDRMAP_EPSZ_256B 0x00000000 // 256 bytes; lower address range: 334 // 0x00 to 0xFF 335 #define EPI_ADDRMAP_EPSZ_64KB 0x00000040 // 64 KB; lower address range: 336 // 0x0000 to 0xFFFF 337 #define EPI_ADDRMAP_EPSZ_16MB 0x00000080 // 16 MB; lower address range: 338 // 0x00.0000 to 0xFF.FFFF 339 #define EPI_ADDRMAP_EPSZ_256MB 0x000000C0 // 256 MB; lower address range: 340 // 0x000.0000 to 0xFFF.FFFF 341 #define EPI_ADDRMAP_EPADR_M 0x00000030 // External Peripheral Address 342 #define EPI_ADDRMAP_EPADR_NONE 0x00000000 // Not mapped 343 #define EPI_ADDRMAP_EPADR_A000 0x00000010 // At 0xA000.0000 344 #define EPI_ADDRMAP_EPADR_C000 0x00000020 // At 0xC000.0000 345 #define EPI_ADDRMAP_EPADR_HBQS 0x00000030 // Only to be used with Host Bus 346 // quad chip select. In quad chip 347 // select mode, CS2n maps to 348 // 0xA000.0000 and CS3n maps to 349 // 0xC000.0000 350 #define EPI_ADDRMAP_ERSZ_M 0x0000000C // External RAM Size 351 #define EPI_ADDRMAP_ERSZ_256B 0x00000000 // 256 bytes; lower address range: 352 // 0x00 to 0xFF 353 #define EPI_ADDRMAP_ERSZ_64KB 0x00000004 // 64 KB; lower address range: 354 // 0x0000 to 0xFFFF 355 #define EPI_ADDRMAP_ERSZ_16MB 0x00000008 // 16 MB; lower address range: 356 // 0x00.0000 to 0xFF.FFFF 357 #define EPI_ADDRMAP_ERSZ_256MB 0x0000000C // 256 MB; lower address range: 358 // 0x000.0000 to 0xFFF.FFFF 359 #define EPI_ADDRMAP_ERADR_M 0x00000003 // External RAM Address 360 #define EPI_ADDRMAP_ERADR_NONE 0x00000000 // Not mapped 361 #define EPI_ADDRMAP_ERADR_6000 0x00000001 // At 0x6000.0000 362 #define EPI_ADDRMAP_ERADR_8000 0x00000002 // At 0x8000.0000 363 #define EPI_ADDRMAP_ERADR_HBQS 0x00000003 // Only to be used with Host Bus 364 // quad chip select. In quad chip 365 // select mode, CS0n maps to 366 // 0x6000.0000 and CS1n maps to 367 // 0x8000.0000 368 369 //***************************************************************************** 370 // 371 // The following are defines for the bit fields in the EPI_O_RSIZE0 register. 372 // 373 //***************************************************************************** 374 #define EPI_RSIZE0_SIZE_M 0x00000003 // Current Size 375 #define EPI_RSIZE0_SIZE_8BIT 0x00000001 // Byte (8 bits) 376 #define EPI_RSIZE0_SIZE_16BIT 0x00000002 // Half-word (16 bits) 377 #define EPI_RSIZE0_SIZE_32BIT 0x00000003 // Word (32 bits) 378 379 //***************************************************************************** 380 // 381 // The following are defines for the bit fields in the EPI_O_RADDR0 register. 382 // 383 //***************************************************************************** 384 #define EPI_RADDR0_ADDR_M 0xFFFFFFFF // Current Address 385 #define EPI_RADDR0_ADDR_S 0 386 387 //***************************************************************************** 388 // 389 // The following are defines for the bit fields in the EPI_O_RPSTD0 register. 390 // 391 //***************************************************************************** 392 #define EPI_RPSTD0_POSTCNT_M 0x00001FFF // Post Count 393 #define EPI_RPSTD0_POSTCNT_S 0 394 395 //***************************************************************************** 396 // 397 // The following are defines for the bit fields in the EPI_O_RSIZE1 register. 398 // 399 //***************************************************************************** 400 #define EPI_RSIZE1_SIZE_M 0x00000003 // Current Size 401 #define EPI_RSIZE1_SIZE_8BIT 0x00000001 // Byte (8 bits) 402 #define EPI_RSIZE1_SIZE_16BIT 0x00000002 // Half-word (16 bits) 403 #define EPI_RSIZE1_SIZE_32BIT 0x00000003 // Word (32 bits) 404 405 //***************************************************************************** 406 // 407 // The following are defines for the bit fields in the EPI_O_RADDR1 register. 408 // 409 //***************************************************************************** 410 #define EPI_RADDR1_ADDR_M 0xFFFFFFFF // Current Address 411 #define EPI_RADDR1_ADDR_S 0 412 413 //***************************************************************************** 414 // 415 // The following are defines for the bit fields in the EPI_O_RPSTD1 register. 416 // 417 //***************************************************************************** 418 #define EPI_RPSTD1_POSTCNT_M 0x00001FFF // Post Count 419 #define EPI_RPSTD1_POSTCNT_S 0 420 421 //***************************************************************************** 422 // 423 // The following are defines for the bit fields in the EPI_O_STAT register. 424 // 425 //***************************************************************************** 426 #define EPI_STAT_XFFULL 0x00000100 // External FIFO Full 427 #define EPI_STAT_XFEMPTY 0x00000080 // External FIFO Empty 428 #define EPI_STAT_INITSEQ 0x00000040 // Initialization Sequence 429 #define EPI_STAT_WBUSY 0x00000020 // Write Busy 430 #define EPI_STAT_NBRBUSY 0x00000010 // Non-Blocking Read Busy 431 #define EPI_STAT_ACTIVE 0x00000001 // Register Active 432 433 //***************************************************************************** 434 // 435 // The following are defines for the bit fields in the EPI_O_RFIFOCNT register. 436 // 437 //***************************************************************************** 438 #define EPI_RFIFOCNT_COUNT_M 0x0000000F // FIFO Count 439 #define EPI_RFIFOCNT_COUNT_S 0 440 441 //***************************************************************************** 442 // 443 // The following are defines for the bit fields in the EPI_O_READFIFO0 444 // register. 445 // 446 //***************************************************************************** 447 #define EPI_READFIFO0_DATA_M 0xFFFFFFFF // Reads Data 448 #define EPI_READFIFO0_DATA_S 0 449 450 //***************************************************************************** 451 // 452 // The following are defines for the bit fields in the EPI_O_READFIFO1 453 // register. 454 // 455 //***************************************************************************** 456 #define EPI_READFIFO1_DATA_M 0xFFFFFFFF // Reads Data 457 #define EPI_READFIFO1_DATA_S 0 458 459 //***************************************************************************** 460 // 461 // The following are defines for the bit fields in the EPI_O_READFIFO2 462 // register. 463 // 464 //***************************************************************************** 465 #define EPI_READFIFO2_DATA_M 0xFFFFFFFF // Reads Data 466 #define EPI_READFIFO2_DATA_S 0 467 468 //***************************************************************************** 469 // 470 // The following are defines for the bit fields in the EPI_O_READFIFO3 471 // register. 472 // 473 //***************************************************************************** 474 #define EPI_READFIFO3_DATA_M 0xFFFFFFFF // Reads Data 475 #define EPI_READFIFO3_DATA_S 0 476 477 //***************************************************************************** 478 // 479 // The following are defines for the bit fields in the EPI_O_READFIFO4 480 // register. 481 // 482 //***************************************************************************** 483 #define EPI_READFIFO4_DATA_M 0xFFFFFFFF // Reads Data 484 #define EPI_READFIFO4_DATA_S 0 485 486 //***************************************************************************** 487 // 488 // The following are defines for the bit fields in the EPI_O_READFIFO5 489 // register. 490 // 491 //***************************************************************************** 492 #define EPI_READFIFO5_DATA_M 0xFFFFFFFF // Reads Data 493 #define EPI_READFIFO5_DATA_S 0 494 495 //***************************************************************************** 496 // 497 // The following are defines for the bit fields in the EPI_O_READFIFO6 498 // register. 499 // 500 //***************************************************************************** 501 #define EPI_READFIFO6_DATA_M 0xFFFFFFFF // Reads Data 502 #define EPI_READFIFO6_DATA_S 0 503 504 //***************************************************************************** 505 // 506 // The following are defines for the bit fields in the EPI_O_READFIFO7 507 // register. 508 // 509 //***************************************************************************** 510 #define EPI_READFIFO7_DATA_M 0xFFFFFFFF // Reads Data 511 #define EPI_READFIFO7_DATA_S 0 512 513 //***************************************************************************** 514 // 515 // The following are defines for the bit fields in the EPI_O_FIFOLVL register. 516 // 517 //***************************************************************************** 518 #define EPI_FIFOLVL_WFERR 0x00020000 // Write Full Error 519 #define EPI_FIFOLVL_RSERR 0x00010000 // Read Stall Error 520 #define EPI_FIFOLVL_WRFIFO_M 0x00000070 // Write FIFO 521 #define EPI_FIFOLVL_WRFIFO_EMPT 0x00000000 // Interrupt is triggered while 522 // WRFIFO is empty. 523 #define EPI_FIFOLVL_WRFIFO_2 0x00000020 // Interrupt is triggered until 524 // there are only two slots 525 // available. Thus, trigger is 526 // deasserted when there are two 527 // WRFIFO entries present. This 528 // configuration is optimized for 529 // bursts of 2 530 #define EPI_FIFOLVL_WRFIFO_1 0x00000030 // Interrupt is triggered until 531 // there is one WRFIFO entry 532 // available. This configuration 533 // expects only single writes 534 #define EPI_FIFOLVL_WRFIFO_NFULL \ 535 0x00000040 // Trigger interrupt when WRFIFO is 536 // not full, meaning trigger will 537 // continue to assert until there 538 // are four entries in the WRFIFO 539 #define EPI_FIFOLVL_RDFIFO_M 0x00000007 // Read FIFO 540 #define EPI_FIFOLVL_RDFIFO_EMPT 0x00000000 // Empty 541 #define EPI_FIFOLVL_RDFIFO_1 0x00000001 // Trigger when there are 1 or more 542 // entries in the NBRFIFO 543 #define EPI_FIFOLVL_RDFIFO_2 0x00000002 // Trigger when there are 2 or more 544 // entries in the NBRFIFO 545 #define EPI_FIFOLVL_RDFIFO_4 0x00000003 // Trigger when there are 4 or more 546 // entries in the NBRFIFO 547 #define EPI_FIFOLVL_RDFIFO_6 0x00000004 // Trigger when there are 6 or more 548 // entries in the NBRFIFO 549 #define EPI_FIFOLVL_RDFIFO_7 0x00000005 // Trigger when there are 7 or more 550 // entries in the NBRFIFO 551 #define EPI_FIFOLVL_RDFIFO_8 0x00000006 // Trigger when there are 8 entries 552 // in the NBRFIFO 553 554 //***************************************************************************** 555 // 556 // The following are defines for the bit fields in the EPI_O_WFIFOCNT register. 557 // 558 //***************************************************************************** 559 #define EPI_WFIFOCNT_WTAV_M 0x00000007 // Available Write Transactions 560 #define EPI_WFIFOCNT_WTAV_S 0 561 562 //***************************************************************************** 563 // 564 // The following are defines for the bit fields in the EPI_O_DMATXCNT register. 565 // 566 //***************************************************************************** 567 #define EPI_DMATXCNT_TXCNT_M 0x0000FFFF // DMA Count 568 #define EPI_DMATXCNT_TXCNT_S 0 569 570 //***************************************************************************** 571 // 572 // The following are defines for the bit fields in the EPI_O_IM register. 573 // 574 //***************************************************************************** 575 #define EPI_IM_DMAWRIM 0x00000010 // Write uDMA Interrupt Mask 576 #define EPI_IM_DMARDIM 0x00000008 // Read uDMA Interrupt Mask 577 #define EPI_IM_WRIM 0x00000004 // Write FIFO Empty Interrupt Mask 578 #define EPI_IM_RDIM 0x00000002 // Read FIFO Full Interrupt Mask 579 #define EPI_IM_ERRIM 0x00000001 // Error Interrupt Mask 580 581 //***************************************************************************** 582 // 583 // The following are defines for the bit fields in the EPI_O_RIS register. 584 // 585 //***************************************************************************** 586 #define EPI_RIS_DMAWRRIS 0x00000010 // Write uDMA Raw Interrupt Status 587 #define EPI_RIS_DMARDRIS 0x00000008 // Read uDMA Raw Interrupt Status 588 #define EPI_RIS_WRRIS 0x00000004 // Write Raw Interrupt Status 589 #define EPI_RIS_RDRIS 0x00000002 // Read Raw Interrupt Status 590 #define EPI_RIS_ERRRIS 0x00000001 // Error Raw Interrupt Status 591 592 //***************************************************************************** 593 // 594 // The following are defines for the bit fields in the EPI_O_MIS register. 595 // 596 //***************************************************************************** 597 #define EPI_MIS_DMAWRMIS 0x00000010 // Write uDMA Masked Interrupt 598 // Status 599 #define EPI_MIS_DMARDMIS 0x00000008 // Read uDMA Masked Interrupt 600 // Status 601 #define EPI_MIS_WRMIS 0x00000004 // Write Masked Interrupt Status 602 #define EPI_MIS_RDMIS 0x00000002 // Read Masked Interrupt Status 603 #define EPI_MIS_ERRMIS 0x00000001 // Error Masked Interrupt Status 604 605 //***************************************************************************** 606 // 607 // The following are defines for the bit fields in the EPI_O_EISC register. 608 // 609 //***************************************************************************** 610 #define EPI_EISC_DMAWRIC 0x00000010 // Write uDMA Interrupt Clear 611 #define EPI_EISC_DMARDIC 0x00000008 // Read uDMA Interrupt Clear 612 #define EPI_EISC_WTFULL 0x00000004 // Write FIFO Full Error 613 #define EPI_EISC_RSTALL 0x00000002 // Read Stalled Error 614 #define EPI_EISC_TOUT 0x00000001 // Timeout Error 615 616 //***************************************************************************** 617 // 618 // The following are defines for the bit fields in the EPI_O_HB8CFG3 register. 619 // 620 //***************************************************************************** 621 #define EPI_HB8CFG3_WRHIGH 0x00200000 // CS2n WRITE Strobe Polarity 622 #define EPI_HB8CFG3_RDHIGH 0x00100000 // CS2n READ Strobe Polarity 623 #define EPI_HB8CFG3_ALEHIGH 0x00080000 // CS2n ALE Strobe Polarity 624 #define EPI_HB8CFG3_WRWS_M 0x000000C0 // CS2n Write Wait States 625 #define EPI_HB8CFG3_WRWS_2 0x00000000 // Active WRn is 2 EPI clocks 626 #define EPI_HB8CFG3_WRWS_4 0x00000040 // Active WRn is 4 EPI clocks 627 #define EPI_HB8CFG3_WRWS_6 0x00000080 // Active WRn is 6 EPI clocks 628 #define EPI_HB8CFG3_WRWS_8 0x000000C0 // Active WRn is 8 EPI clocks 629 #define EPI_HB8CFG3_RDWS_M 0x00000030 // CS2n Read Wait States 630 #define EPI_HB8CFG3_RDWS_2 0x00000000 // Active RDn is 2 EPI clocks 631 #define EPI_HB8CFG3_RDWS_4 0x00000010 // Active RDn is 4 EPI clocks 632 #define EPI_HB8CFG3_RDWS_6 0x00000020 // Active RDn is 6 EPI clocks 633 #define EPI_HB8CFG3_RDWS_8 0x00000030 // Active RDn is 8 EPI clocks 634 #define EPI_HB8CFG3_MODE_M 0x00000003 // CS2n Host Bus Sub-Mode 635 #define EPI_HB8CFG3_MODE_ADMUX 0x00000000 // ADMUX - AD[7:0] 636 #define EPI_HB8CFG3_MODE_AD 0x00000001 // ADNONMUX - D[7:0] 637 638 //***************************************************************************** 639 // 640 // The following are defines for the bit fields in the EPI_O_HB16CFG3 register. 641 // 642 //***************************************************************************** 643 #define EPI_HB16CFG3_WRHIGH 0x00200000 // CS2n WRITE Strobe Polarity 644 #define EPI_HB16CFG3_RDHIGH 0x00100000 // CS2n READ Strobe Polarity 645 #define EPI_HB16CFG3_ALEHIGH 0x00080000 // CS2n ALE Strobe Polarity 646 #define EPI_HB16CFG3_WRCRE 0x00040000 // CS2n PSRAM Configuration 647 // Register Write 648 #define EPI_HB16CFG3_RDCRE 0x00020000 // CS2n PSRAM Configuration 649 // Register Read 650 #define EPI_HB16CFG3_BURST 0x00010000 // CS2n Burst Mode 651 #define EPI_HB16CFG3_WRWS_M 0x000000C0 // CS2n Write Wait States 652 #define EPI_HB16CFG3_WRWS_2 0x00000000 // Active WRn is 2 EPI clocks 653 #define EPI_HB16CFG3_WRWS_4 0x00000040 // Active WRn is 4 EPI clocks 654 #define EPI_HB16CFG3_WRWS_6 0x00000080 // Active WRn is 6 EPI clocks 655 #define EPI_HB16CFG3_WRWS_8 0x000000C0 // Active WRn is 8 EPI clocks 656 #define EPI_HB16CFG3_RDWS_M 0x00000030 // CS2n Read Wait States 657 #define EPI_HB16CFG3_RDWS_2 0x00000000 // Active RDn is 2 EPI clocks 658 #define EPI_HB16CFG3_RDWS_4 0x00000010 // Active RDn is 4 EPI clocks 659 #define EPI_HB16CFG3_RDWS_6 0x00000020 // Active RDn is 6 EPI clocks 660 #define EPI_HB16CFG3_RDWS_8 0x00000030 // Active RDn is 8 EPI clocks 661 #define EPI_HB16CFG3_MODE_M 0x00000003 // CS2n Host Bus Sub-Mode 662 #define EPI_HB16CFG3_MODE_ADMUX 0x00000000 // ADMUX - AD[15:0] 663 #define EPI_HB16CFG3_MODE_AD 0x00000001 // ADNONMUX - D[15:0] 664 665 //***************************************************************************** 666 // 667 // The following are defines for the bit fields in the EPI_O_HB16CFG4 register. 668 // 669 //***************************************************************************** 670 #define EPI_HB16CFG4_WRHIGH 0x00200000 // CS3n WRITE Strobe Polarity 671 #define EPI_HB16CFG4_RDHIGH 0x00100000 // CS3n READ Strobe Polarity 672 #define EPI_HB16CFG4_ALEHIGH 0x00080000 // CS3n ALE Strobe Polarity 673 #define EPI_HB16CFG4_WRCRE 0x00040000 // CS3n PSRAM Configuration 674 // Register Write 675 #define EPI_HB16CFG4_RDCRE 0x00020000 // CS3n PSRAM Configuration 676 // Register Read 677 #define EPI_HB16CFG4_BURST 0x00010000 // CS3n Burst Mode 678 #define EPI_HB16CFG4_WRWS_M 0x000000C0 // CS3n Write Wait States 679 #define EPI_HB16CFG4_WRWS_2 0x00000000 // Active WRn is 2 EPI clocks 680 #define EPI_HB16CFG4_WRWS_4 0x00000040 // Active WRn is 4 EPI clocks 681 #define EPI_HB16CFG4_WRWS_6 0x00000080 // Active WRn is 6 EPI clocks 682 #define EPI_HB16CFG4_WRWS_8 0x000000C0 // Active WRn is 8 EPI clocks 683 #define EPI_HB16CFG4_RDWS_M 0x00000030 // CS3n Read Wait States 684 #define EPI_HB16CFG4_RDWS_2 0x00000000 // Active RDn is 2 EPI clocks 685 #define EPI_HB16CFG4_RDWS_4 0x00000010 // Active RDn is 4 EPI clocks 686 #define EPI_HB16CFG4_RDWS_6 0x00000020 // Active RDn is 6 EPI clocks 687 #define EPI_HB16CFG4_RDWS_8 0x00000030 // Active RDn is 8 EPI clocks 688 #define EPI_HB16CFG4_MODE_M 0x00000003 // CS3n Host Bus Sub-Mode 689 #define EPI_HB16CFG4_MODE_ADMUX 0x00000000 // ADMUX - AD[15:0] 690 #define EPI_HB16CFG4_MODE_AD 0x00000001 // ADNONMUX - D[15:0] 691 692 //***************************************************************************** 693 // 694 // The following are defines for the bit fields in the EPI_O_HB8CFG4 register. 695 // 696 //***************************************************************************** 697 #define EPI_HB8CFG4_WRHIGH 0x00200000 // CS3n WRITE Strobe Polarity 698 #define EPI_HB8CFG4_RDHIGH 0x00100000 // CS2n READ Strobe Polarity 699 #define EPI_HB8CFG4_ALEHIGH 0x00080000 // CS3n ALE Strobe Polarity 700 #define EPI_HB8CFG4_WRWS_M 0x000000C0 // CS3n Write Wait States 701 #define EPI_HB8CFG4_WRWS_2 0x00000000 // Active WRn is 2 EPI clocks 702 #define EPI_HB8CFG4_WRWS_4 0x00000040 // Active WRn is 4 EPI clocks 703 #define EPI_HB8CFG4_WRWS_6 0x00000080 // Active WRn is 6 EPI clocks 704 #define EPI_HB8CFG4_WRWS_8 0x000000C0 // Active WRn is 8 EPI clocks 705 #define EPI_HB8CFG4_RDWS_M 0x00000030 // CS3n Read Wait States 706 #define EPI_HB8CFG4_RDWS_2 0x00000000 // Active RDn is 2 EPI clocks 707 #define EPI_HB8CFG4_RDWS_4 0x00000010 // Active RDn is 4 EPI clocks 708 #define EPI_HB8CFG4_RDWS_6 0x00000020 // Active RDn is 6 EPI clocks 709 #define EPI_HB8CFG4_RDWS_8 0x00000030 // Active RDn is 8 EPI clocks 710 #define EPI_HB8CFG4_MODE_M 0x00000003 // CS3n Host Bus Sub-Mode 711 #define EPI_HB8CFG4_MODE_ADMUX 0x00000000 // ADMUX - AD[7:0] 712 #define EPI_HB8CFG4_MODE_AD 0x00000001 // ADNONMUX - D[7:0] 713 714 //***************************************************************************** 715 // 716 // The following are defines for the bit fields in the EPI_O_HB8TIME register. 717 // 718 //***************************************************************************** 719 #define EPI_HB8TIME_IRDYDLY_M 0x03000000 // CS0n Input Ready Delay 720 #define EPI_HB8TIME_CAPWIDTH_M 0x00003000 // CS0n Inter-transfer Capture 721 // Width 722 #define EPI_HB8TIME_WRWSM 0x00000010 // Write Wait State Minus One 723 #define EPI_HB8TIME_RDWSM 0x00000001 // Read Wait State Minus One 724 #define EPI_HB8TIME_IRDYDLY_S 24 725 #define EPI_HB8TIME_CAPWIDTH_S 12 726 727 //***************************************************************************** 728 // 729 // The following are defines for the bit fields in the EPI_O_HB16TIME register. 730 // 731 //***************************************************************************** 732 #define EPI_HB16TIME_IRDYDLY_M 0x03000000 // CS0n Input Ready Delay 733 #define EPI_HB16TIME_PSRAMSZ_M 0x00070000 // PSRAM Row Size 734 #define EPI_HB16TIME_PSRAMSZ_0 0x00000000 // No row size limitation 735 #define EPI_HB16TIME_PSRAMSZ_128B \ 736 0x00010000 // 128 B 737 #define EPI_HB16TIME_PSRAMSZ_256B \ 738 0x00020000 // 256 B 739 #define EPI_HB16TIME_PSRAMSZ_512B \ 740 0x00030000 // 512 B 741 #define EPI_HB16TIME_PSRAMSZ_1KB \ 742 0x00040000 // 1024 B 743 #define EPI_HB16TIME_PSRAMSZ_2KB \ 744 0x00050000 // 2048 B 745 #define EPI_HB16TIME_PSRAMSZ_4KB \ 746 0x00060000 // 4096 B 747 #define EPI_HB16TIME_PSRAMSZ_8KB \ 748 0x00070000 // 8192 B 749 #define EPI_HB16TIME_CAPWIDTH_M 0x00003000 // CS0n Inter-transfer Capture 750 // Width 751 #define EPI_HB16TIME_WRWSM 0x00000010 // Write Wait State Minus One 752 #define EPI_HB16TIME_RDWSM 0x00000001 // Read Wait State Minus One 753 #define EPI_HB16TIME_IRDYDLY_S 24 754 #define EPI_HB16TIME_CAPWIDTH_S 12 755 756 //***************************************************************************** 757 // 758 // The following are defines for the bit fields in the EPI_O_HB8TIME2 register. 759 // 760 //***************************************************************************** 761 #define EPI_HB8TIME2_IRDYDLY_M 0x03000000 // CS1n Input Ready Delay 762 #define EPI_HB8TIME2_CAPWIDTH_M 0x00003000 // CS1n Inter-transfer Capture 763 // Width 764 #define EPI_HB8TIME2_WRWSM 0x00000010 // CS1n Write Wait State Minus One 765 #define EPI_HB8TIME2_RDWSM 0x00000001 // CS1n Read Wait State Minus One 766 #define EPI_HB8TIME2_IRDYDLY_S 24 767 #define EPI_HB8TIME2_CAPWIDTH_S 12 768 769 //***************************************************************************** 770 // 771 // The following are defines for the bit fields in the EPI_O_HB16TIME2 772 // register. 773 // 774 //***************************************************************************** 775 #define EPI_HB16TIME2_IRDYDLY_M 0x03000000 // CS1n Input Ready Delay 776 #define EPI_HB16TIME2_PSRAMSZ_M 0x00070000 // PSRAM Row Size 777 #define EPI_HB16TIME2_PSRAMSZ_0 0x00000000 // No row size limitation 778 #define EPI_HB16TIME2_PSRAMSZ_128B \ 779 0x00010000 // 128 B 780 #define EPI_HB16TIME2_PSRAMSZ_256B \ 781 0x00020000 // 256 B 782 #define EPI_HB16TIME2_PSRAMSZ_512B \ 783 0x00030000 // 512 B 784 #define EPI_HB16TIME2_PSRAMSZ_1KB \ 785 0x00040000 // 1024 B 786 #define EPI_HB16TIME2_PSRAMSZ_2KB \ 787 0x00050000 // 2048 B 788 #define EPI_HB16TIME2_PSRAMSZ_4KB \ 789 0x00060000 // 4096 B 790 #define EPI_HB16TIME2_PSRAMSZ_8KB \ 791 0x00070000 // 8192 B 792 #define EPI_HB16TIME2_CAPWIDTH_M \ 793 0x00003000 // CS1n Inter-transfer Capture 794 // Width 795 #define EPI_HB16TIME2_WRWSM 0x00000010 // CS1n Write Wait State Minus One 796 #define EPI_HB16TIME2_RDWSM 0x00000001 // CS1n Read Wait State Minus One 797 #define EPI_HB16TIME2_IRDYDLY_S 24 798 #define EPI_HB16TIME2_CAPWIDTH_S \ 799 12 800 801 //***************************************************************************** 802 // 803 // The following are defines for the bit fields in the EPI_O_HB16TIME3 804 // register. 805 // 806 //***************************************************************************** 807 #define EPI_HB16TIME3_IRDYDLY_M 0x03000000 // CS2n Input Ready Delay 808 #define EPI_HB16TIME3_PSRAMSZ_M 0x00070000 // PSRAM Row Size 809 #define EPI_HB16TIME3_PSRAMSZ_0 0x00000000 // No row size limitation 810 #define EPI_HB16TIME3_PSRAMSZ_128B \ 811 0x00010000 // 128 B 812 #define EPI_HB16TIME3_PSRAMSZ_256B \ 813 0x00020000 // 256 B 814 #define EPI_HB16TIME3_PSRAMSZ_512B \ 815 0x00030000 // 512 B 816 #define EPI_HB16TIME3_PSRAMSZ_1KB \ 817 0x00040000 // 1024 B 818 #define EPI_HB16TIME3_PSRAMSZ_2KB \ 819 0x00050000 // 2048 B 820 #define EPI_HB16TIME3_PSRAMSZ_4KB \ 821 0x00060000 // 4096 B 822 #define EPI_HB16TIME3_PSRAMSZ_8KB \ 823 0x00070000 // 8192 B 824 #define EPI_HB16TIME3_CAPWIDTH_M \ 825 0x00003000 // CS2n Inter-transfer Capture 826 // Width 827 #define EPI_HB16TIME3_WRWSM 0x00000010 // CS2n Write Wait State Minus One 828 #define EPI_HB16TIME3_RDWSM 0x00000001 // CS2n Read Wait State Minus One 829 #define EPI_HB16TIME3_IRDYDLY_S 24 830 #define EPI_HB16TIME3_CAPWIDTH_S \ 831 12 832 833 //***************************************************************************** 834 // 835 // The following are defines for the bit fields in the EPI_O_HB8TIME3 register. 836 // 837 //***************************************************************************** 838 #define EPI_HB8TIME3_IRDYDLY_M 0x03000000 // CS2n Input Ready Delay 839 #define EPI_HB8TIME3_CAPWIDTH_M 0x00003000 // CS2n Inter-transfer Capture 840 // Width 841 #define EPI_HB8TIME3_WRWSM 0x00000010 // CS2n Write Wait State Minus One 842 #define EPI_HB8TIME3_RDWSM 0x00000001 // CS2n Read Wait State Minus One 843 #define EPI_HB8TIME3_IRDYDLY_S 24 844 #define EPI_HB8TIME3_CAPWIDTH_S 12 845 846 //***************************************************************************** 847 // 848 // The following are defines for the bit fields in the EPI_O_HB8TIME4 register. 849 // 850 //***************************************************************************** 851 #define EPI_HB8TIME4_IRDYDLY_M 0x03000000 // CS3n Input Ready Delay 852 #define EPI_HB8TIME4_CAPWIDTH_M 0x00003000 // CS3n Inter-transfer Capture 853 // Width 854 #define EPI_HB8TIME4_WRWSM 0x00000010 // CS3n Write Wait State Minus One 855 #define EPI_HB8TIME4_RDWSM 0x00000001 // CS3n Read Wait State Minus One 856 #define EPI_HB8TIME4_IRDYDLY_S 24 857 #define EPI_HB8TIME4_CAPWIDTH_S 12 858 859 //***************************************************************************** 860 // 861 // The following are defines for the bit fields in the EPI_O_HB16TIME4 862 // register. 863 // 864 //***************************************************************************** 865 #define EPI_HB16TIME4_IRDYDLY_M 0x03000000 // CS3n Input Ready Delay 866 #define EPI_HB16TIME4_PSRAMSZ_M 0x00070000 // PSRAM Row Size 867 #define EPI_HB16TIME4_PSRAMSZ_0 0x00000000 // No row size limitation 868 #define EPI_HB16TIME4_PSRAMSZ_128B \ 869 0x00010000 // 128 B 870 #define EPI_HB16TIME4_PSRAMSZ_256B \ 871 0x00020000 // 256 B 872 #define EPI_HB16TIME4_PSRAMSZ_512B \ 873 0x00030000 // 512 B 874 #define EPI_HB16TIME4_PSRAMSZ_1KB \ 875 0x00040000 // 1024 B 876 #define EPI_HB16TIME4_PSRAMSZ_2KB \ 877 0x00050000 // 2048 B 878 #define EPI_HB16TIME4_PSRAMSZ_4KB \ 879 0x00060000 // 4096 B 880 #define EPI_HB16TIME4_PSRAMSZ_8KB \ 881 0x00070000 // 8192 B 882 #define EPI_HB16TIME4_CAPWIDTH_M \ 883 0x00003000 // CS3n Inter-transfer Capture 884 // Width 885 #define EPI_HB16TIME4_WRWSM 0x00000010 // CS3n Write Wait State Minus One 886 #define EPI_HB16TIME4_RDWSM 0x00000001 // CS3n Read Wait State Minus One 887 #define EPI_HB16TIME4_IRDYDLY_S 24 888 #define EPI_HB16TIME4_CAPWIDTH_S \ 889 12 890 891 //***************************************************************************** 892 // 893 // The following are defines for the bit fields in the EPI_O_HBPSRAM register. 894 // 895 //***************************************************************************** 896 #define EPI_HBPSRAM_CR_M 0x001FFFFF // PSRAM Config Register 897 #define EPI_HBPSRAM_CR_S 0 898 899 //***************************************************************************** 900 // 901 // The following definitions are deprecated. 902 // 903 //***************************************************************************** 904 #ifndef DEPRECATED 905 906 //***************************************************************************** 907 // 908 // The following are deprecated defines for the bit fields in the EPI_O_FIFOLVL 909 // register. 910 // 911 //***************************************************************************** 912 #define EPI_FIFOLVL_WRFIFO_1_4 0x00000020 // Trigger when there are up to 3 913 // spaces available in the WFIFO 914 #define EPI_FIFOLVL_WRFIFO_1_2 0x00000030 // Trigger when there are up to 2 915 // spaces available in the WFIFO 916 #define EPI_FIFOLVL_WRFIFO_3_4 0x00000040 // Trigger when there is 1 space 917 // available in the WFIFO 918 #define EPI_FIFOLVL_RDFIFO_1_8 0x00000001 // Trigger when there are 1 or more 919 // entries in the NBRFIFO 920 #define EPI_FIFOLVL_RDFIFO_1_4 0x00000002 // Trigger when there are 2 or more 921 // entries in the NBRFIFO 922 #define EPI_FIFOLVL_RDFIFO_1_2 0x00000003 // Trigger when there are 4 or more 923 // entries in the NBRFIFO 924 #define EPI_FIFOLVL_RDFIFO_3_4 0x00000004 // Trigger when there are 6 or more 925 // entries in the NBRFIFO 926 #define EPI_FIFOLVL_RDFIFO_7_8 0x00000005 // Trigger when there are 7 or more 927 // entries in the NBRFIFO 928 #define EPI_FIFOLVL_RDFIFO_FULL 0x00000006 // Trigger when there are 8 entries 929 // in the NBRFIFO 930 931 #endif 932 933 #endif // __HW_EPI_H__ 934