1 //***************************************************************************** 2 // 3 // hw_hibernate.h - Defines and Macros for the Hibernation module. 4 // 5 // Copyright (c) 2007-2017 Texas Instruments Incorporated. All rights reserved. 6 // Software License Agreement 7 // 8 // Redistribution and use in source and binary forms, with or without 9 // modification, are permitted provided that the following conditions 10 // are met: 11 // 12 // Redistributions of source code must retain the above copyright 13 // notice, this list of conditions and the following disclaimer. 14 // 15 // Redistributions in binary form must reproduce the above copyright 16 // notice, this list of conditions and the following disclaimer in the 17 // documentation and/or other materials provided with the 18 // distribution. 19 // 20 // Neither the name of Texas Instruments Incorporated nor the names of 21 // its contributors may be used to endorse or promote products derived 22 // from this software without specific prior written permission. 23 // 24 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 27 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 28 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 29 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 30 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 34 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 // 36 // This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. 37 // 38 //***************************************************************************** 39 40 #ifndef __HW_HIBERNATE_H__ 41 #define __HW_HIBERNATE_H__ 42 43 //***************************************************************************** 44 // 45 // The following are defines for the Hibernation module register addresses. 46 // 47 //***************************************************************************** 48 #define HIB_RTCC 0x400FC000 // Hibernation RTC Counter 49 #define HIB_RTCM0 0x400FC004 // Hibernation RTC Match 0 50 #define HIB_RTCLD 0x400FC00C // Hibernation RTC Load 51 #define HIB_CTL 0x400FC010 // Hibernation Control 52 #define HIB_IM 0x400FC014 // Hibernation Interrupt Mask 53 #define HIB_RIS 0x400FC018 // Hibernation Raw Interrupt Status 54 #define HIB_MIS 0x400FC01C // Hibernation Masked Interrupt 55 // Status 56 #define HIB_IC 0x400FC020 // Hibernation Interrupt Clear 57 #define HIB_RTCT 0x400FC024 // Hibernation RTC Trim 58 #define HIB_RTCSS 0x400FC028 // Hibernation RTC Sub Seconds 59 #define HIB_IO 0x400FC02C // Hibernation IO Configuration 60 #define HIB_DATA 0x400FC030 // Hibernation Data 61 #define HIB_CALCTL 0x400FC300 // Hibernation Calendar Control 62 #define HIB_CAL0 0x400FC310 // Hibernation Calendar 0 63 #define HIB_CAL1 0x400FC314 // Hibernation Calendar 1 64 #define HIB_CALLD0 0x400FC320 // Hibernation Calendar Load 0 65 #define HIB_CALLD1 0x400FC324 // Hibernation Calendar Load 66 #define HIB_CALM0 0x400FC330 // Hibernation Calendar Match 0 67 #define HIB_CALM1 0x400FC334 // Hibernation Calendar Match 1 68 #define HIB_LOCK 0x400FC360 // Hibernation Lock 69 #define HIB_TPCTL 0x400FC400 // HIB Tamper Control 70 #define HIB_TPSTAT 0x400FC404 // HIB Tamper Status 71 #define HIB_TPIO 0x400FC410 // HIB Tamper I/O Control 72 #define HIB_TPLOG0 0x400FC4E0 // HIB Tamper Log 0 73 #define HIB_TPLOG1 0x400FC4E4 // HIB Tamper Log 1 74 #define HIB_TPLOG2 0x400FC4E8 // HIB Tamper Log 2 75 #define HIB_TPLOG3 0x400FC4EC // HIB Tamper Log 3 76 #define HIB_TPLOG4 0x400FC4F0 // HIB Tamper Log 4 77 #define HIB_TPLOG5 0x400FC4F4 // HIB Tamper Log 5 78 #define HIB_TPLOG6 0x400FC4F8 // HIB Tamper Log 6 79 #define HIB_TPLOG7 0x400FC4FC // HIB Tamper Log 7 80 #define HIB_PP 0x400FCFC0 // Hibernation Peripheral 81 // Properties 82 #define HIB_CC 0x400FCFC8 // Hibernation Clock Control 83 84 //***************************************************************************** 85 // 86 // The following are defines for the bit fields in the HIB_RTCC register. 87 // 88 //***************************************************************************** 89 #define HIB_RTCC_M 0xFFFFFFFF // RTC Counter 90 #define HIB_RTCC_S 0 91 92 //***************************************************************************** 93 // 94 // The following are defines for the bit fields in the HIB_RTCM0 register. 95 // 96 //***************************************************************************** 97 #define HIB_RTCM0_M 0xFFFFFFFF // RTC Match 0 98 #define HIB_RTCM0_S 0 99 100 //***************************************************************************** 101 // 102 // The following are defines for the bit fields in the HIB_RTCLD register. 103 // 104 //***************************************************************************** 105 #define HIB_RTCLD_M 0xFFFFFFFF // RTC Load 106 #define HIB_RTCLD_S 0 107 108 //***************************************************************************** 109 // 110 // The following are defines for the bit fields in the HIB_CTL register. 111 // 112 //***************************************************************************** 113 #define HIB_CTL_WRC 0x80000000 // Write Complete/Capable 114 #define HIB_CTL_RETCLR 0x40000000 // GPIO Retention/Clear 115 #define HIB_CTL_OSCSEL 0x00080000 // Oscillator Select 116 #define HIB_CTL_OSCDRV 0x00020000 // Oscillator Drive Capability 117 #define HIB_CTL_OSCBYP 0x00010000 // Oscillator Bypass 118 #define HIB_CTL_VBATSEL_M 0x00006000 // Select for Low-Battery 119 // Comparator 120 #define HIB_CTL_VBATSEL_1_9V 0x00000000 // 1.9 Volts 121 #define HIB_CTL_VBATSEL_2_1V 0x00002000 // 2.1 Volts (default) 122 #define HIB_CTL_VBATSEL_2_3V 0x00004000 // 2.3 Volts 123 #define HIB_CTL_VBATSEL_2_5V 0x00006000 // 2.5 Volts 124 #define HIB_CTL_BATCHK 0x00000400 // Check Battery Status 125 #define HIB_CTL_BATWKEN 0x00000200 // Wake on Low Battery 126 #define HIB_CTL_VDD3ON 0x00000100 // VDD Powered 127 #define HIB_CTL_VABORT 0x00000080 // Power Cut Abort Enable 128 #define HIB_CTL_CLK32EN 0x00000040 // Clocking Enable 129 #define HIB_CTL_PINWEN 0x00000010 // External Wake Pin Enable 130 #define HIB_CTL_RTCWEN 0x00000008 // RTC Wake-up Enable 131 #define HIB_CTL_HIBREQ 0x00000002 // Hibernation Request 132 #define HIB_CTL_RTCEN 0x00000001 // RTC Timer Enable 133 134 //***************************************************************************** 135 // 136 // The following are defines for the bit fields in the HIB_IM register. 137 // 138 //***************************************************************************** 139 #define HIB_IM_VDDFAIL 0x00000080 // VDD Fail Interrupt Mask 140 #define HIB_IM_RSTWK 0x00000040 // Reset Pad I/O Wake-Up Interrupt 141 // Mask 142 #define HIB_IM_PADIOWK 0x00000020 // Pad I/O Wake-Up Interrupt Mask 143 #define HIB_IM_WC 0x00000010 // External Write Complete/Capable 144 // Interrupt Mask 145 #define HIB_IM_EXTW 0x00000008 // External Wake-Up Interrupt Mask 146 #define HIB_IM_LOWBAT 0x00000004 // Low Battery Voltage Interrupt 147 // Mask 148 #define HIB_IM_RTCALT0 0x00000001 // RTC Alert 0 Interrupt Mask 149 150 //***************************************************************************** 151 // 152 // The following are defines for the bit fields in the HIB_RIS register. 153 // 154 //***************************************************************************** 155 #define HIB_RIS_VDDFAIL 0x00000080 // VDD Fail Raw Interrupt Status 156 #define HIB_RIS_RSTWK 0x00000040 // Reset Pad I/O Wake-Up Raw 157 // Interrupt Status 158 #define HIB_RIS_PADIOWK 0x00000020 // Pad I/O Wake-Up Raw Interrupt 159 // Status 160 #define HIB_RIS_WC 0x00000010 // Write Complete/Capable Raw 161 // Interrupt Status 162 #define HIB_RIS_EXTW 0x00000008 // External Wake-Up Raw Interrupt 163 // Status 164 #define HIB_RIS_LOWBAT 0x00000004 // Low Battery Voltage Raw 165 // Interrupt Status 166 #define HIB_RIS_RTCALT0 0x00000001 // RTC Alert 0 Raw Interrupt Status 167 168 //***************************************************************************** 169 // 170 // The following are defines for the bit fields in the HIB_MIS register. 171 // 172 //***************************************************************************** 173 #define HIB_MIS_VDDFAIL 0x00000080 // VDD Fail Interrupt Mask 174 #define HIB_MIS_RSTWK 0x00000040 // Reset Pad I/O Wake-Up Interrupt 175 // Mask 176 #define HIB_MIS_PADIOWK 0x00000020 // Pad I/O Wake-Up Interrupt Mask 177 #define HIB_MIS_WC 0x00000010 // Write Complete/Capable Masked 178 // Interrupt Status 179 #define HIB_MIS_EXTW 0x00000008 // External Wake-Up Masked 180 // Interrupt Status 181 #define HIB_MIS_LOWBAT 0x00000004 // Low Battery Voltage Masked 182 // Interrupt Status 183 #define HIB_MIS_RTCALT0 0x00000001 // RTC Alert 0 Masked Interrupt 184 // Status 185 186 //***************************************************************************** 187 // 188 // The following are defines for the bit fields in the HIB_IC register. 189 // 190 //***************************************************************************** 191 #define HIB_IC_VDDFAIL 0x00000080 // VDD Fail Interrupt Clear 192 #define HIB_IC_RSTWK 0x00000040 // Reset Pad I/O Wake-Up Interrupt 193 // Clear 194 #define HIB_IC_PADIOWK 0x00000020 // Pad I/O Wake-Up Interrupt Clear 195 #define HIB_IC_WC 0x00000010 // Write Complete/Capable Interrupt 196 // Clear 197 #define HIB_IC_EXTW 0x00000008 // External Wake-Up Interrupt Clear 198 #define HIB_IC_LOWBAT 0x00000004 // Low Battery Voltage Interrupt 199 // Clear 200 #define HIB_IC_RTCALT0 0x00000001 // RTC Alert0 Masked Interrupt 201 // Clear 202 203 //***************************************************************************** 204 // 205 // The following are defines for the bit fields in the HIB_RTCT register. 206 // 207 //***************************************************************************** 208 #define HIB_RTCT_TRIM_M 0x0000FFFF // RTC Trim Value 209 #define HIB_RTCT_TRIM_S 0 210 211 //***************************************************************************** 212 // 213 // The following are defines for the bit fields in the HIB_RTCSS register. 214 // 215 //***************************************************************************** 216 #define HIB_RTCSS_RTCSSM_M 0x7FFF0000 // RTC Sub Seconds Match 217 #define HIB_RTCSS_RTCSSC_M 0x00007FFF // RTC Sub Seconds Count 218 #define HIB_RTCSS_RTCSSM_S 16 219 #define HIB_RTCSS_RTCSSC_S 0 220 221 //***************************************************************************** 222 // 223 // The following are defines for the bit fields in the HIB_IO register. 224 // 225 //***************************************************************************** 226 #define HIB_IO_IOWRC 0x80000000 // I/O Write Complete 227 #define HIB_IO_WURSTEN 0x00000010 // Reset Wake Source Enable 228 #define HIB_IO_WUUNLK 0x00000001 // I/O Wake Pad Configuration 229 // Enable 230 231 //***************************************************************************** 232 // 233 // The following are defines for the bit fields in the HIB_DATA register. 234 // 235 //***************************************************************************** 236 #define HIB_DATA_RTD_M 0xFFFFFFFF // Hibernation Module NV Data 237 #define HIB_DATA_RTD_S 0 238 239 //***************************************************************************** 240 // 241 // The following are defines for the bit fields in the HIB_CALCTL register. 242 // 243 //***************************************************************************** 244 #define HIB_CALCTL_CAL24 0x00000004 // Calendar Mode 245 #define HIB_CALCTL_CALEN 0x00000001 // RTC Calendar/Counter Mode Select 246 247 //***************************************************************************** 248 // 249 // The following are defines for the bit fields in the HIB_CAL0 register. 250 // 251 //***************************************************************************** 252 #define HIB_CAL0_VALID 0x80000000 // Valid Calendar Load 253 #define HIB_CAL0_AMPM 0x00400000 // AM/PM Designation 254 #define HIB_CAL0_HR_M 0x001F0000 // Hours 255 #define HIB_CAL0_MIN_M 0x00003F00 // Minutes 256 #define HIB_CAL0_SEC_M 0x0000003F // Seconds 257 #define HIB_CAL0_HR_S 16 258 #define HIB_CAL0_MIN_S 8 259 #define HIB_CAL0_SEC_S 0 260 261 //***************************************************************************** 262 // 263 // The following are defines for the bit fields in the HIB_CAL1 register. 264 // 265 //***************************************************************************** 266 #define HIB_CAL1_VALID 0x80000000 // Valid Calendar Load 267 #define HIB_CAL1_DOW_M 0x07000000 // Day of Week 268 #define HIB_CAL1_YEAR_M 0x007F0000 // Year Value 269 #define HIB_CAL1_MON_M 0x00000F00 // Month 270 #define HIB_CAL1_DOM_M 0x0000001F // Day of Month 271 #define HIB_CAL1_DOW_S 24 272 #define HIB_CAL1_YEAR_S 16 273 #define HIB_CAL1_MON_S 8 274 #define HIB_CAL1_DOM_S 0 275 276 //***************************************************************************** 277 // 278 // The following are defines for the bit fields in the HIB_CALLD0 register. 279 // 280 //***************************************************************************** 281 #define HIB_CALLD0_AMPM 0x00400000 // AM/PM Designation 282 #define HIB_CALLD0_HR_M 0x001F0000 // Hours 283 #define HIB_CALLD0_MIN_M 0x00003F00 // Minutes 284 #define HIB_CALLD0_SEC_M 0x0000003F // Seconds 285 #define HIB_CALLD0_HR_S 16 286 #define HIB_CALLD0_MIN_S 8 287 #define HIB_CALLD0_SEC_S 0 288 289 //***************************************************************************** 290 // 291 // The following are defines for the bit fields in the HIB_CALLD1 register. 292 // 293 //***************************************************************************** 294 #define HIB_CALLD1_DOW_M 0x07000000 // Day of Week 295 #define HIB_CALLD1_YEAR_M 0x007F0000 // Year Value 296 #define HIB_CALLD1_MON_M 0x00000F00 // Month 297 #define HIB_CALLD1_DOM_M 0x0000001F // Day of Month 298 #define HIB_CALLD1_DOW_S 24 299 #define HIB_CALLD1_YEAR_S 16 300 #define HIB_CALLD1_MON_S 8 301 #define HIB_CALLD1_DOM_S 0 302 303 //***************************************************************************** 304 // 305 // The following are defines for the bit fields in the HIB_CALM0 register. 306 // 307 //***************************************************************************** 308 #define HIB_CALM0_AMPM 0x00400000 // AM/PM Designation 309 #define HIB_CALM0_HR_M 0x001F0000 // Hours 310 #define HIB_CALM0_MIN_M 0x00003F00 // Minutes 311 #define HIB_CALM0_SEC_M 0x0000003F // Seconds 312 #define HIB_CALM0_HR_S 16 313 #define HIB_CALM0_MIN_S 8 314 #define HIB_CALM0_SEC_S 0 315 316 //***************************************************************************** 317 // 318 // The following are defines for the bit fields in the HIB_CALM1 register. 319 // 320 //***************************************************************************** 321 #define HIB_CALM1_DOM_M 0x0000001F // Day of Month 322 #define HIB_CALM1_DOM_S 0 323 324 //***************************************************************************** 325 // 326 // The following are defines for the bit fields in the HIB_LOCK register. 327 // 328 //***************************************************************************** 329 #define HIB_LOCK_HIBLOCK_M 0xFFFFFFFF // HIbernate Lock 330 #define HIB_LOCK_HIBLOCK_KEY 0xA3359554 // Hibernate Lock Key 331 #define HIB_LOCK_HIBLOCK_S 0 332 333 //***************************************************************************** 334 // 335 // The following are defines for the bit fields in the HIB_TPCTL register. 336 // 337 //***************************************************************************** 338 #define HIB_TPCTL_WAKE 0x00000800 // Wake from Hibernate on a Tamper 339 // Event 340 #define HIB_TPCTL_MEMCLR_M 0x00000300 // HIB Memory Clear on Tamper Event 341 #define HIB_TPCTL_MEMCLR_NONE 0x00000000 // Do not Clear HIB memory on 342 // tamper event 343 #define HIB_TPCTL_MEMCLR_LOW32 0x00000100 // Clear Lower 32 Bytes of HIB 344 // memory on tamper event 345 #define HIB_TPCTL_MEMCLR_HIGH32 0x00000200 // Clear upper 32 Bytes of HIB 346 // memory on tamper event 347 #define HIB_TPCTL_MEMCLR_ALL 0x00000300 // Clear all HIB memory on tamper 348 // event 349 #define HIB_TPCTL_TPCLR 0x00000010 // Tamper Event Clear 350 #define HIB_TPCTL_TPEN 0x00000001 // Tamper Module Enable 351 352 //***************************************************************************** 353 // 354 // The following are defines for the bit fields in the HIB_TPSTAT register. 355 // 356 //***************************************************************************** 357 #define HIB_TPSTAT_STATE_M 0x0000000C // Tamper Module Status 358 #define HIB_TPSTAT_STATE_DISABLED \ 359 0x00000000 // Tamper disabled 360 #define HIB_TPSTAT_STATE_CONFIGED \ 361 0x00000004 // Tamper configured 362 #define HIB_TPSTAT_STATE_ERROR 0x00000008 // Tamper pin event occurred 363 #define HIB_TPSTAT_XOSCST 0x00000002 // External Oscillator Status 364 #define HIB_TPSTAT_XOSCFAIL 0x00000001 // External Oscillator Failure 365 366 //***************************************************************************** 367 // 368 // The following are defines for the bit fields in the HIB_TPIO register. 369 // 370 //***************************************************************************** 371 #define HIB_TPIO_GFLTR3 0x08000000 // TMPR3 Glitch Filtering 372 #define HIB_TPIO_PUEN3 0x04000000 // TMPR3 Internal Weak Pull-up 373 // Enable 374 #define HIB_TPIO_LEV3 0x02000000 // TMPR3 Trigger Level 375 #define HIB_TPIO_EN3 0x01000000 // TMPR3 Enable 376 #define HIB_TPIO_GFLTR2 0x00080000 // TMPR2 Glitch Filtering 377 #define HIB_TPIO_PUEN2 0x00040000 // TMPR2 Internal Weak Pull-up 378 // Enable 379 #define HIB_TPIO_LEV2 0x00020000 // TMPR2 Trigger Level 380 #define HIB_TPIO_EN2 0x00010000 // TMPR2 Enable 381 #define HIB_TPIO_GFLTR1 0x00000800 // TMPR1 Glitch Filtering 382 #define HIB_TPIO_PUEN1 0x00000400 // TMPR1 Internal Weak Pull-up 383 // Enable 384 #define HIB_TPIO_LEV1 0x00000200 // TMPR1 Trigger Level 385 #define HIB_TPIO_EN1 0x00000100 // TMPR1Enable 386 #define HIB_TPIO_GFLTR0 0x00000008 // TMPR0 Glitch Filtering 387 #define HIB_TPIO_PUEN0 0x00000004 // TMPR0 Internal Weak Pull-up 388 // Enable 389 #define HIB_TPIO_LEV0 0x00000002 // TMPR0 Trigger Level 390 #define HIB_TPIO_EN0 0x00000001 // TMPR0 Enable 391 392 //***************************************************************************** 393 // 394 // The following are defines for the bit fields in the HIB_TPLOG0 register. 395 // 396 //***************************************************************************** 397 #define HIB_TPLOG0_TIME_M 0xFFFFFFFF // Tamper Log Calendar Information 398 #define HIB_TPLOG0_TIME_S 0 399 400 //***************************************************************************** 401 // 402 // The following are defines for the bit fields in the HIB_TPLOG1 register. 403 // 404 //***************************************************************************** 405 #define HIB_TPLOG1_XOSC 0x00010000 // Status of external 32 406 #define HIB_TPLOG1_TRIG3 0x00000008 // Status of TMPR[3] Trigger 407 #define HIB_TPLOG1_TRIG2 0x00000004 // Status of TMPR[2] Trigger 408 #define HIB_TPLOG1_TRIG1 0x00000002 // Status of TMPR[1] Trigger 409 #define HIB_TPLOG1_TRIG0 0x00000001 // Status of TMPR[0] Trigger 410 411 //***************************************************************************** 412 // 413 // The following are defines for the bit fields in the HIB_TPLOG2 register. 414 // 415 //***************************************************************************** 416 #define HIB_TPLOG2_TIME_M 0xFFFFFFFF // Tamper Log Calendar Information 417 #define HIB_TPLOG2_TIME_S 0 418 419 //***************************************************************************** 420 // 421 // The following are defines for the bit fields in the HIB_TPLOG3 register. 422 // 423 //***************************************************************************** 424 #define HIB_TPLOG3_XOSC 0x00010000 // Status of external 32 425 #define HIB_TPLOG3_TRIG3 0x00000008 // Status of TMPR[3] Trigger 426 #define HIB_TPLOG3_TRIG2 0x00000004 // Status of TMPR[2] Trigger 427 #define HIB_TPLOG3_TRIG1 0x00000002 // Status of TMPR[1] Trigger 428 #define HIB_TPLOG3_TRIG0 0x00000001 // Status of TMPR[0] Trigger 429 430 //***************************************************************************** 431 // 432 // The following are defines for the bit fields in the HIB_TPLOG4 register. 433 // 434 //***************************************************************************** 435 #define HIB_TPLOG4_TIME_M 0xFFFFFFFF // Tamper Log Calendar Information 436 #define HIB_TPLOG4_TIME_S 0 437 438 //***************************************************************************** 439 // 440 // The following are defines for the bit fields in the HIB_TPLOG5 register. 441 // 442 //***************************************************************************** 443 #define HIB_TPLOG5_XOSC 0x00010000 // Status of external 32 444 #define HIB_TPLOG5_TRIG3 0x00000008 // Status of TMPR[3] Trigger 445 #define HIB_TPLOG5_TRIG2 0x00000004 // Status of TMPR[2] Trigger 446 #define HIB_TPLOG5_TRIG1 0x00000002 // Status of TMPR[1] Trigger 447 #define HIB_TPLOG5_TRIG0 0x00000001 // Status of TMPR[0] Trigger 448 449 //***************************************************************************** 450 // 451 // The following are defines for the bit fields in the HIB_TPLOG6 register. 452 // 453 //***************************************************************************** 454 #define HIB_TPLOG6_TIME_M 0xFFFFFFFF // Tamper Log Calendar Information 455 #define HIB_TPLOG6_TIME_S 0 456 457 //***************************************************************************** 458 // 459 // The following are defines for the bit fields in the HIB_TPLOG7 register. 460 // 461 //***************************************************************************** 462 #define HIB_TPLOG7_XOSC 0x00010000 // Status of external 32 463 #define HIB_TPLOG7_TRIG3 0x00000008 // Status of TMPR[3] Trigger 464 #define HIB_TPLOG7_TRIG2 0x00000004 // Status of TMPR[2] Trigger 465 #define HIB_TPLOG7_TRIG1 0x00000002 // Status of TMPR[1] Trigger 466 #define HIB_TPLOG7_TRIG0 0x00000001 // Status of TMPR[0] Trigger 467 468 //***************************************************************************** 469 // 470 // The following are defines for the bit fields in the HIB_PP register. 471 // 472 //***************************************************************************** 473 #define HIB_PP_TAMPER 0x00000002 // Tamper Pin Presence 474 #define HIB_PP_WAKENC 0x00000001 // Wake Pin Presence 475 476 //***************************************************************************** 477 // 478 // The following are defines for the bit fields in the HIB_CC register. 479 // 480 //***************************************************************************** 481 #define HIB_CC_SYSCLKEN 0x00000001 // RTCOSC to System Clock Enable 482 483 #endif // __HW_HIBERNATE_H__ 484