1 //***************************************************************************** 2 // 3 // hw_i2c.h - Macros used when accessing the I2C master and slave hardware. 4 // 5 // Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. 6 // Software License Agreement 7 // 8 // Redistribution and use in source and binary forms, with or without 9 // modification, are permitted provided that the following conditions 10 // are met: 11 // 12 // Redistributions of source code must retain the above copyright 13 // notice, this list of conditions and the following disclaimer. 14 // 15 // Redistributions in binary form must reproduce the above copyright 16 // notice, this list of conditions and the following disclaimer in the 17 // documentation and/or other materials provided with the 18 // distribution. 19 // 20 // Neither the name of Texas Instruments Incorporated nor the names of 21 // its contributors may be used to endorse or promote products derived 22 // from this software without specific prior written permission. 23 // 24 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 27 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 28 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 29 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 30 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 34 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 // 36 // This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. 37 // 38 //***************************************************************************** 39 40 #ifndef __HW_I2C_H__ 41 #define __HW_I2C_H__ 42 43 //***************************************************************************** 44 // 45 // The following are defines for the I2C register offsets. 46 // 47 //***************************************************************************** 48 #define I2C_O_MSA 0x00000000 // I2C Master Slave Address 49 #define I2C_O_MCS 0x00000004 // I2C Master Control/Status 50 #define I2C_O_MDR 0x00000008 // I2C Master Data 51 #define I2C_O_MTPR 0x0000000C // I2C Master Timer Period 52 #define I2C_O_MIMR 0x00000010 // I2C Master Interrupt Mask 53 #define I2C_O_MRIS 0x00000014 // I2C Master Raw Interrupt Status 54 #define I2C_O_MMIS 0x00000018 // I2C Master Masked Interrupt 55 // Status 56 #define I2C_O_MICR 0x0000001C // I2C Master Interrupt Clear 57 #define I2C_O_MCR 0x00000020 // I2C Master Configuration 58 #define I2C_O_MCLKOCNT 0x00000024 // I2C Master Clock Low Timeout 59 // Count 60 #define I2C_O_MBMON 0x0000002C // I2C Master Bus Monitor 61 #define I2C_O_MBLEN 0x00000030 // I2C Master Burst Length 62 #define I2C_O_MBCNT 0x00000034 // I2C Master Burst Count 63 #define I2C_O_MCR2 0x00000038 // I2C Master Configuration 2 64 #define I2C_O_SOAR 0x00000800 // I2C Slave Own Address 65 #define I2C_O_SCSR 0x00000804 // I2C Slave Control/Status 66 #define I2C_O_SDR 0x00000808 // I2C Slave Data 67 #define I2C_O_SIMR 0x0000080C // I2C Slave Interrupt Mask 68 #define I2C_O_SRIS 0x00000810 // I2C Slave Raw Interrupt Status 69 #define I2C_O_SMIS 0x00000814 // I2C Slave Masked Interrupt 70 // Status 71 #define I2C_O_SICR 0x00000818 // I2C Slave Interrupt Clear 72 #define I2C_O_SOAR2 0x0000081C // I2C Slave Own Address 2 73 #define I2C_O_SACKCTL 0x00000820 // I2C Slave ACK Control 74 #define I2C_O_FIFODATA 0x00000F00 // I2C FIFO Data 75 #define I2C_O_FIFOCTL 0x00000F04 // I2C FIFO Control 76 #define I2C_O_FIFOSTATUS 0x00000F08 // I2C FIFO Status 77 #define I2C_O_PP 0x00000FC0 // I2C Peripheral Properties 78 #define I2C_O_PC 0x00000FC4 // I2C Peripheral Configuration 79 80 //***************************************************************************** 81 // 82 // The following are defines for the bit fields in the I2C_O_MSA register. 83 // 84 //***************************************************************************** 85 #define I2C_MSA_SA_M 0x000000FE // I2C Slave Address 86 #define I2C_MSA_RS 0x00000001 // Receive not send 87 #define I2C_MSA_SA_S 1 88 89 //***************************************************************************** 90 // 91 // The following are defines for the bit fields in the I2C_O_MCS register. 92 // 93 //***************************************************************************** 94 #define I2C_MCS_ACTDMARX 0x80000000 // DMA RX Active Status 95 #define I2C_MCS_ACTDMATX 0x40000000 // DMA TX Active Status 96 #define I2C_MCS_CLKTO 0x00000080 // Clock Timeout Error 97 #define I2C_MCS_BURST 0x00000040 // Burst Enable 98 #define I2C_MCS_BUSBSY 0x00000040 // Bus Busy 99 #define I2C_MCS_IDLE 0x00000020 // I2C Idle 100 #define I2C_MCS_QCMD 0x00000020 // Quick Command 101 #define I2C_MCS_ARBLST 0x00000010 // Arbitration Lost 102 #define I2C_MCS_HS 0x00000010 // High-Speed Enable 103 #define I2C_MCS_ACK 0x00000008 // Data Acknowledge Enable 104 #define I2C_MCS_DATACK 0x00000008 // Acknowledge Data 105 #define I2C_MCS_ADRACK 0x00000004 // Acknowledge Address 106 #define I2C_MCS_STOP 0x00000004 // Generate STOP 107 #define I2C_MCS_ERROR 0x00000002 // Error 108 #define I2C_MCS_START 0x00000002 // Generate START 109 #define I2C_MCS_RUN 0x00000001 // I2C Master Enable 110 #define I2C_MCS_BUSY 0x00000001 // I2C Busy 111 112 //***************************************************************************** 113 // 114 // The following are defines for the bit fields in the I2C_O_MDR register. 115 // 116 //***************************************************************************** 117 #define I2C_MDR_DATA_M 0x000000FF // This byte contains the data 118 // transferred during a transaction 119 #define I2C_MDR_DATA_S 0 120 121 //***************************************************************************** 122 // 123 // The following are defines for the bit fields in the I2C_O_MTPR register. 124 // 125 //***************************************************************************** 126 #define I2C_MTPR_PULSEL_M 0x00070000 // Glitch Suppression Pulse Width 127 #define I2C_MTPR_PULSEL_BYPASS 0x00000000 // Bypass 128 #define I2C_MTPR_PULSEL_1 0x00010000 // 1 clock 129 #define I2C_MTPR_PULSEL_2 0x00020000 // 2 clocks 130 #define I2C_MTPR_PULSEL_3 0x00030000 // 3 clocks 131 #define I2C_MTPR_PULSEL_4 0x00040000 // 4 clocks 132 #define I2C_MTPR_PULSEL_8 0x00050000 // 8 clocks 133 #define I2C_MTPR_PULSEL_16 0x00060000 // 16 clocks 134 #define I2C_MTPR_PULSEL_31 0x00070000 // 31 clocks 135 #define I2C_MTPR_HS 0x00000080 // High-Speed Enable 136 #define I2C_MTPR_TPR_M 0x0000007F // Timer Period 137 #define I2C_MTPR_TPR_S 0 138 139 //***************************************************************************** 140 // 141 // The following are defines for the bit fields in the I2C_O_MIMR register. 142 // 143 //***************************************************************************** 144 #define I2C_MIMR_RXFFIM 0x00000800 // Receive FIFO Full Interrupt Mask 145 #define I2C_MIMR_TXFEIM 0x00000400 // Transmit FIFO Empty Interrupt 146 // Mask 147 #define I2C_MIMR_RXIM 0x00000200 // Receive FIFO Request Interrupt 148 // Mask 149 #define I2C_MIMR_TXIM 0x00000100 // Transmit FIFO Request Interrupt 150 // Mask 151 #define I2C_MIMR_ARBLOSTIM 0x00000080 // Arbitration Lost Interrupt Mask 152 #define I2C_MIMR_STOPIM 0x00000040 // STOP Detection Interrupt Mask 153 #define I2C_MIMR_STARTIM 0x00000020 // START Detection Interrupt Mask 154 #define I2C_MIMR_NACKIM 0x00000010 // Address/Data NACK Interrupt Mask 155 #define I2C_MIMR_DMATXIM 0x00000008 // Transmit DMA Interrupt Mask 156 #define I2C_MIMR_DMARXIM 0x00000004 // Receive DMA Interrupt Mask 157 #define I2C_MIMR_CLKIM 0x00000002 // Clock Timeout Interrupt Mask 158 #define I2C_MIMR_IM 0x00000001 // Master Interrupt Mask 159 160 //***************************************************************************** 161 // 162 // The following are defines for the bit fields in the I2C_O_MRIS register. 163 // 164 //***************************************************************************** 165 #define I2C_MRIS_RXFFRIS 0x00000800 // Receive FIFO Full Raw Interrupt 166 // Status 167 #define I2C_MRIS_TXFERIS 0x00000400 // Transmit FIFO Empty Raw 168 // Interrupt Status 169 #define I2C_MRIS_RXRIS 0x00000200 // Receive FIFO Request Raw 170 // Interrupt Status 171 #define I2C_MRIS_TXRIS 0x00000100 // Transmit Request Raw Interrupt 172 // Status 173 #define I2C_MRIS_ARBLOSTRIS 0x00000080 // Arbitration Lost Raw Interrupt 174 // Status 175 #define I2C_MRIS_STOPRIS 0x00000040 // STOP Detection Raw Interrupt 176 // Status 177 #define I2C_MRIS_STARTRIS 0x00000020 // START Detection Raw Interrupt 178 // Status 179 #define I2C_MRIS_NACKRIS 0x00000010 // Address/Data NACK Raw Interrupt 180 // Status 181 #define I2C_MRIS_DMATXRIS 0x00000008 // Transmit DMA Raw Interrupt 182 // Status 183 #define I2C_MRIS_DMARXRIS 0x00000004 // Receive DMA Raw Interrupt Status 184 #define I2C_MRIS_CLKRIS 0x00000002 // Clock Timeout Raw Interrupt 185 // Status 186 #define I2C_MRIS_RIS 0x00000001 // Master Raw Interrupt Status 187 188 //***************************************************************************** 189 // 190 // The following are defines for the bit fields in the I2C_O_MMIS register. 191 // 192 //***************************************************************************** 193 #define I2C_MMIS_RXFFMIS 0x00000800 // Receive FIFO Full Interrupt Mask 194 #define I2C_MMIS_TXFEMIS 0x00000400 // Transmit FIFO Empty Interrupt 195 // Mask 196 #define I2C_MMIS_RXMIS 0x00000200 // Receive FIFO Request Interrupt 197 // Mask 198 #define I2C_MMIS_TXMIS 0x00000100 // Transmit Request Interrupt Mask 199 #define I2C_MMIS_ARBLOSTMIS 0x00000080 // Arbitration Lost Interrupt Mask 200 #define I2C_MMIS_STOPMIS 0x00000040 // STOP Detection Interrupt Mask 201 #define I2C_MMIS_STARTMIS 0x00000020 // START Detection Interrupt Mask 202 #define I2C_MMIS_NACKMIS 0x00000010 // Address/Data NACK Interrupt Mask 203 #define I2C_MMIS_DMATXMIS 0x00000008 // Transmit DMA Interrupt Status 204 #define I2C_MMIS_DMARXMIS 0x00000004 // Receive DMA Interrupt Status 205 #define I2C_MMIS_CLKMIS 0x00000002 // Clock Timeout Masked Interrupt 206 // Status 207 #define I2C_MMIS_MIS 0x00000001 // Masked Interrupt Status 208 209 //***************************************************************************** 210 // 211 // The following are defines for the bit fields in the I2C_O_MICR register. 212 // 213 //***************************************************************************** 214 #define I2C_MICR_RXFFIC 0x00000800 // Receive FIFO Full Interrupt 215 // Clear 216 #define I2C_MICR_TXFEIC 0x00000400 // Transmit FIFO Empty Interrupt 217 // Clear 218 #define I2C_MICR_RXIC 0x00000200 // Receive FIFO Request Interrupt 219 // Clear 220 #define I2C_MICR_TXIC 0x00000100 // Transmit FIFO Request Interrupt 221 // Clear 222 #define I2C_MICR_ARBLOSTIC 0x00000080 // Arbitration Lost Interrupt Clear 223 #define I2C_MICR_STOPIC 0x00000040 // STOP Detection Interrupt Clear 224 #define I2C_MICR_STARTIC 0x00000020 // START Detection Interrupt Clear 225 #define I2C_MICR_NACKIC 0x00000010 // Address/Data NACK Interrupt 226 // Clear 227 #define I2C_MICR_DMATXIC 0x00000008 // Transmit DMA Interrupt Clear 228 #define I2C_MICR_DMARXIC 0x00000004 // Receive DMA Interrupt Clear 229 #define I2C_MICR_CLKIC 0x00000002 // Clock Timeout Interrupt Clear 230 #define I2C_MICR_IC 0x00000001 // Master Interrupt Clear 231 232 //***************************************************************************** 233 // 234 // The following are defines for the bit fields in the I2C_O_MCR register. 235 // 236 //***************************************************************************** 237 #define I2C_MCR_GFE 0x00000040 // I2C Glitch Filter Enable 238 #define I2C_MCR_SFE 0x00000020 // I2C Slave Function Enable 239 #define I2C_MCR_MFE 0x00000010 // I2C Master Function Enable 240 #define I2C_MCR_LPBK 0x00000001 // I2C Loopback 241 242 //***************************************************************************** 243 // 244 // The following are defines for the bit fields in the I2C_O_MCLKOCNT register. 245 // 246 //***************************************************************************** 247 #define I2C_MCLKOCNT_CNTL_M 0x000000FF // I2C Master Count 248 #define I2C_MCLKOCNT_CNTL_S 0 249 250 //***************************************************************************** 251 // 252 // The following are defines for the bit fields in the I2C_O_MBMON register. 253 // 254 //***************************************************************************** 255 #define I2C_MBMON_SDA 0x00000002 // I2C SDA Status 256 #define I2C_MBMON_SCL 0x00000001 // I2C SCL Status 257 258 //***************************************************************************** 259 // 260 // The following are defines for the bit fields in the I2C_O_MBLEN register. 261 // 262 //***************************************************************************** 263 #define I2C_MBLEN_CNTL_M 0x000000FF // I2C Burst Length 264 #define I2C_MBLEN_CNTL_S 0 265 266 //***************************************************************************** 267 // 268 // The following are defines for the bit fields in the I2C_O_MBCNT register. 269 // 270 //***************************************************************************** 271 #define I2C_MBCNT_CNTL_M 0x000000FF // I2C Master Burst Count 272 #define I2C_MBCNT_CNTL_S 0 273 274 //***************************************************************************** 275 // 276 // The following are defines for the bit fields in the I2C_O_MCR2 register. 277 // 278 //***************************************************************************** 279 #define I2C_MCR2_GFPW_M 0x00000070 // I2C Glitch Filter Pulse Width 280 #define I2C_MCR2_GFPW_BYPASS 0x00000000 // Bypass 281 #define I2C_MCR2_GFPW_1 0x00000010 // 1 clock 282 #define I2C_MCR2_GFPW_2 0x00000020 // 2 clocks 283 #define I2C_MCR2_GFPW_3 0x00000030 // 3 clocks 284 #define I2C_MCR2_GFPW_4 0x00000040 // 4 clocks 285 #define I2C_MCR2_GFPW_8 0x00000050 // 8 clocks 286 #define I2C_MCR2_GFPW_16 0x00000060 // 16 clocks 287 #define I2C_MCR2_GFPW_31 0x00000070 // 31 clocks 288 289 //***************************************************************************** 290 // 291 // The following are defines for the bit fields in the I2C_O_SOAR register. 292 // 293 //***************************************************************************** 294 #define I2C_SOAR_OAR_M 0x0000007F // I2C Slave Own Address 295 #define I2C_SOAR_OAR_S 0 296 297 //***************************************************************************** 298 // 299 // The following are defines for the bit fields in the I2C_O_SCSR register. 300 // 301 //***************************************************************************** 302 #define I2C_SCSR_ACTDMARX 0x80000000 // DMA RX Active Status 303 #define I2C_SCSR_ACTDMATX 0x40000000 // DMA TX Active Status 304 #define I2C_SCSR_QCMDRW 0x00000020 // Quick Command Read / Write 305 #define I2C_SCSR_QCMDST 0x00000010 // Quick Command Status 306 #define I2C_SCSR_OAR2SEL 0x00000008 // OAR2 Address Matched 307 #define I2C_SCSR_FBR 0x00000004 // First Byte Received 308 #define I2C_SCSR_RXFIFO 0x00000004 // RX FIFO Enable 309 #define I2C_SCSR_TXFIFO 0x00000002 // TX FIFO Enable 310 #define I2C_SCSR_TREQ 0x00000002 // Transmit Request 311 #define I2C_SCSR_DA 0x00000001 // Device Active 312 #define I2C_SCSR_RREQ 0x00000001 // Receive Request 313 314 //***************************************************************************** 315 // 316 // The following are defines for the bit fields in the I2C_O_SDR register. 317 // 318 //***************************************************************************** 319 #define I2C_SDR_DATA_M 0x000000FF // Data for Transfer 320 #define I2C_SDR_DATA_S 0 321 322 //***************************************************************************** 323 // 324 // The following are defines for the bit fields in the I2C_O_SIMR register. 325 // 326 //***************************************************************************** 327 #define I2C_SIMR_RXFFIM 0x00000100 // Receive FIFO Full Interrupt Mask 328 #define I2C_SIMR_TXFEIM 0x00000080 // Transmit FIFO Empty Interrupt 329 // Mask 330 #define I2C_SIMR_RXIM 0x00000040 // Receive FIFO Request Interrupt 331 // Mask 332 #define I2C_SIMR_TXIM 0x00000020 // Transmit FIFO Request Interrupt 333 // Mask 334 #define I2C_SIMR_DMATXIM 0x00000010 // Transmit DMA Interrupt Mask 335 #define I2C_SIMR_DMARXIM 0x00000008 // Receive DMA Interrupt Mask 336 #define I2C_SIMR_STOPIM 0x00000004 // Stop Condition Interrupt Mask 337 #define I2C_SIMR_STARTIM 0x00000002 // Start Condition Interrupt Mask 338 #define I2C_SIMR_DATAIM 0x00000001 // Data Interrupt Mask 339 340 //***************************************************************************** 341 // 342 // The following are defines for the bit fields in the I2C_O_SRIS register. 343 // 344 //***************************************************************************** 345 #define I2C_SRIS_RXFFRIS 0x00000100 // Receive FIFO Full Raw Interrupt 346 // Status 347 #define I2C_SRIS_TXFERIS 0x00000080 // Transmit FIFO Empty Raw 348 // Interrupt Status 349 #define I2C_SRIS_RXRIS 0x00000040 // Receive FIFO Request Raw 350 // Interrupt Status 351 #define I2C_SRIS_TXRIS 0x00000020 // Transmit Request Raw Interrupt 352 // Status 353 #define I2C_SRIS_DMATXRIS 0x00000010 // Transmit DMA Raw Interrupt 354 // Status 355 #define I2C_SRIS_DMARXRIS 0x00000008 // Receive DMA Raw Interrupt Status 356 #define I2C_SRIS_STOPRIS 0x00000004 // Stop Condition Raw Interrupt 357 // Status 358 #define I2C_SRIS_STARTRIS 0x00000002 // Start Condition Raw Interrupt 359 // Status 360 #define I2C_SRIS_DATARIS 0x00000001 // Data Raw Interrupt Status 361 362 //***************************************************************************** 363 // 364 // The following are defines for the bit fields in the I2C_O_SMIS register. 365 // 366 //***************************************************************************** 367 #define I2C_SMIS_RXFFMIS 0x00000100 // Receive FIFO Full Interrupt Mask 368 #define I2C_SMIS_TXFEMIS 0x00000080 // Transmit FIFO Empty Interrupt 369 // Mask 370 #define I2C_SMIS_RXMIS 0x00000040 // Receive FIFO Request Interrupt 371 // Mask 372 #define I2C_SMIS_TXMIS 0x00000020 // Transmit FIFO Request Interrupt 373 // Mask 374 #define I2C_SMIS_DMATXMIS 0x00000010 // Transmit DMA Masked Interrupt 375 // Status 376 #define I2C_SMIS_DMARXMIS 0x00000008 // Receive DMA Masked Interrupt 377 // Status 378 #define I2C_SMIS_STOPMIS 0x00000004 // Stop Condition Masked Interrupt 379 // Status 380 #define I2C_SMIS_STARTMIS 0x00000002 // Start Condition Masked Interrupt 381 // Status 382 #define I2C_SMIS_DATAMIS 0x00000001 // Data Masked Interrupt Status 383 384 //***************************************************************************** 385 // 386 // The following are defines for the bit fields in the I2C_O_SICR register. 387 // 388 //***************************************************************************** 389 #define I2C_SICR_RXFFIC 0x00000100 // Receive FIFO Full Interrupt Mask 390 #define I2C_SICR_TXFEIC 0x00000080 // Transmit FIFO Empty Interrupt 391 // Mask 392 #define I2C_SICR_RXIC 0x00000040 // Receive Request Interrupt Mask 393 #define I2C_SICR_TXIC 0x00000020 // Transmit Request Interrupt Mask 394 #define I2C_SICR_DMATXIC 0x00000010 // Transmit DMA Interrupt Clear 395 #define I2C_SICR_DMARXIC 0x00000008 // Receive DMA Interrupt Clear 396 #define I2C_SICR_STOPIC 0x00000004 // Stop Condition Interrupt Clear 397 #define I2C_SICR_STARTIC 0x00000002 // Start Condition Interrupt Clear 398 #define I2C_SICR_DATAIC 0x00000001 // Data Interrupt Clear 399 400 //***************************************************************************** 401 // 402 // The following are defines for the bit fields in the I2C_O_SOAR2 register. 403 // 404 //***************************************************************************** 405 #define I2C_SOAR2_OAR2EN 0x00000080 // I2C Slave Own Address 2 Enable 406 #define I2C_SOAR2_OAR2_M 0x0000007F // I2C Slave Own Address 2 407 #define I2C_SOAR2_OAR2_S 0 408 409 //***************************************************************************** 410 // 411 // The following are defines for the bit fields in the I2C_O_SACKCTL register. 412 // 413 //***************************************************************************** 414 #define I2C_SACKCTL_ACKOVAL 0x00000002 // I2C Slave ACK Override Value 415 #define I2C_SACKCTL_ACKOEN 0x00000001 // I2C Slave ACK Override Enable 416 417 //***************************************************************************** 418 // 419 // The following are defines for the bit fields in the I2C_O_FIFODATA register. 420 // 421 //***************************************************************************** 422 #define I2C_FIFODATA_DATA_M 0x000000FF // I2C TX FIFO Write Data Byte 423 #define I2C_FIFODATA_DATA_S 0 424 425 //***************************************************************************** 426 // 427 // The following are defines for the bit fields in the I2C_O_FIFOCTL register. 428 // 429 //***************************************************************************** 430 #define I2C_FIFOCTL_RXASGNMT 0x80000000 // RX Control Assignment 431 #define I2C_FIFOCTL_RXFLUSH 0x40000000 // RX FIFO Flush 432 #define I2C_FIFOCTL_DMARXENA 0x20000000 // DMA RX Channel Enable 433 #define I2C_FIFOCTL_RXTRIG_M 0x00070000 // RX FIFO Trigger 434 #define I2C_FIFOCTL_TXASGNMT 0x00008000 // TX Control Assignment 435 #define I2C_FIFOCTL_TXFLUSH 0x00004000 // TX FIFO Flush 436 #define I2C_FIFOCTL_DMATXENA 0x00002000 // DMA TX Channel Enable 437 #define I2C_FIFOCTL_TXTRIG_M 0x00000007 // TX FIFO Trigger 438 #define I2C_FIFOCTL_RXTRIG_S 16 439 #define I2C_FIFOCTL_TXTRIG_S 0 440 441 //***************************************************************************** 442 // 443 // The following are defines for the bit fields in the I2C_O_FIFOSTATUS 444 // register. 445 // 446 //***************************************************************************** 447 #define I2C_FIFOSTATUS_RXABVTRIG \ 448 0x00040000 // RX FIFO Above Trigger Level 449 #define I2C_FIFOSTATUS_RXFF 0x00020000 // RX FIFO Full 450 #define I2C_FIFOSTATUS_RXFE 0x00010000 // RX FIFO Empty 451 #define I2C_FIFOSTATUS_TXBLWTRIG \ 452 0x00000004 // TX FIFO Below Trigger Level 453 #define I2C_FIFOSTATUS_TXFF 0x00000002 // TX FIFO Full 454 #define I2C_FIFOSTATUS_TXFE 0x00000001 // TX FIFO Empty 455 456 //***************************************************************************** 457 // 458 // The following are defines for the bit fields in the I2C_O_PP register. 459 // 460 //***************************************************************************** 461 #define I2C_PP_HS 0x00000001 // High-Speed Capable 462 463 //***************************************************************************** 464 // 465 // The following are defines for the bit fields in the I2C_O_PC register. 466 // 467 //***************************************************************************** 468 #define I2C_PC_HS 0x00000001 // High-Speed Capable 469 470 #endif // __HW_I2C_H__ 471