1 //***************************************************************************** 2 // 3 // hw_ints.h - Macros that define the interrupt assignment on Tiva C Series 4 // MCUs. 5 // 6 // Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. 7 // Software License Agreement 8 // 9 // Redistribution and use in source and binary forms, with or without 10 // modification, are permitted provided that the following conditions 11 // are met: 12 // 13 // Redistributions of source code must retain the above copyright 14 // notice, this list of conditions and the following disclaimer. 15 // 16 // Redistributions in binary form must reproduce the above copyright 17 // notice, this list of conditions and the following disclaimer in the 18 // documentation and/or other materials provided with the 19 // distribution. 20 // 21 // Neither the name of Texas Instruments Incorporated nor the names of 22 // its contributors may be used to endorse or promote products derived 23 // from this software without specific prior written permission. 24 // 25 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 // 37 // This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. 38 // 39 //***************************************************************************** 40 41 #ifndef __HW_INTS_H__ 42 #define __HW_INTS_H__ 43 44 //***************************************************************************** 45 // 46 // The following are defines for the fault assignments. 47 // 48 //***************************************************************************** 49 #define FAULT_NMI 2 // NMI fault 50 #define FAULT_HARD 3 // Hard fault 51 #define FAULT_MPU 4 // MPU fault 52 #define FAULT_BUS 5 // Bus fault 53 #define FAULT_USAGE 6 // Usage fault 54 #define FAULT_SVCALL 11 // SVCall 55 #define FAULT_DEBUG 12 // Debug monitor 56 #define FAULT_PENDSV 14 // PendSV 57 #define FAULT_SYSTICK 15 // System Tick 58 59 //***************************************************************************** 60 // 61 // TM4C123 Class Interrupts 62 // 63 //***************************************************************************** 64 #define INT_GPIOA_TM4C123 16 // GPIO Port A 65 #define INT_GPIOB_TM4C123 17 // GPIO Port B 66 #define INT_GPIOC_TM4C123 18 // GPIO Port C 67 #define INT_GPIOD_TM4C123 19 // GPIO Port D 68 #define INT_GPIOE_TM4C123 20 // GPIO Port E 69 #define INT_UART0_TM4C123 21 // UART0 70 #define INT_UART1_TM4C123 22 // UART1 71 #define INT_SSI0_TM4C123 23 // SSI0 72 #define INT_I2C0_TM4C123 24 // I2C0 73 #define INT_PWM0_FAULT_TM4C123 25 // PWM0 Fault 74 #define INT_PWM0_0_TM4C123 26 // PWM0 Generator 0 75 #define INT_PWM0_1_TM4C123 27 // PWM0 Generator 1 76 #define INT_PWM0_2_TM4C123 28 // PWM0 Generator 2 77 #define INT_QEI0_TM4C123 29 // QEI0 78 #define INT_ADC0SS0_TM4C123 30 // ADC0 Sequence 0 79 #define INT_ADC0SS1_TM4C123 31 // ADC0 Sequence 1 80 #define INT_ADC0SS2_TM4C123 32 // ADC0 Sequence 2 81 #define INT_ADC0SS3_TM4C123 33 // ADC0 Sequence 3 82 #define INT_WATCHDOG_TM4C123 34 // Watchdog Timers 0 and 1 83 #define INT_TIMER0A_TM4C123 35 // 16/32-Bit Timer 0A 84 #define INT_TIMER0B_TM4C123 36 // 16/32-Bit Timer 0B 85 #define INT_TIMER1A_TM4C123 37 // 16/32-Bit Timer 1A 86 #define INT_TIMER1B_TM4C123 38 // 16/32-Bit Timer 1B 87 #define INT_TIMER2A_TM4C123 39 // 16/32-Bit Timer 2A 88 #define INT_TIMER2B_TM4C123 40 // 16/32-Bit Timer 2B 89 #define INT_COMP0_TM4C123 41 // Analog Comparator 0 90 #define INT_COMP1_TM4C123 42 // Analog Comparator 1 91 #define INT_COMP2_TM4C123 43 // Analog Comparator 2 92 #define INT_SYSCTL_TM4C123 44 // System Control 93 #define INT_FLASH_TM4C123 45 // Flash Memory Control and EEPROM 94 // Control 95 #define INT_GPIOF_TM4C123 46 // GPIO Port F 96 #define INT_GPIOG_TM4C123 47 // GPIO Port G 97 #define INT_GPIOH_TM4C123 48 // GPIO Port H 98 #define INT_UART2_TM4C123 49 // UART2 99 #define INT_SSI1_TM4C123 50 // SSI1 100 #define INT_TIMER3A_TM4C123 51 // 16/32-Bit Timer 3A 101 #define INT_TIMER3B_TM4C123 52 // Timer 3B 102 #define INT_I2C1_TM4C123 53 // I2C1 103 #define INT_QEI1_TM4C123 54 // QEI1 104 #define INT_CAN0_TM4C123 55 // CAN0 105 #define INT_CAN1_TM4C123 56 // CAN1 106 #define INT_HIBERNATE_TM4C123 59 // Hibernation Module 107 #define INT_USB0_TM4C123 60 // USB 108 #define INT_PWM0_3_TM4C123 61 // PWM Generator 3 109 #define INT_UDMA_TM4C123 62 // uDMA Software 110 #define INT_UDMAERR_TM4C123 63 // uDMA Error 111 #define INT_ADC1SS0_TM4C123 64 // ADC1 Sequence 0 112 #define INT_ADC1SS1_TM4C123 65 // ADC1 Sequence 1 113 #define INT_ADC1SS2_TM4C123 66 // ADC1 Sequence 2 114 #define INT_ADC1SS3_TM4C123 67 // ADC1 Sequence 3 115 #define INT_GPIOJ_TM4C123 70 // GPIO Port J 116 #define INT_GPIOK_TM4C123 71 // GPIO Port K 117 #define INT_GPIOL_TM4C123 72 // GPIO Port L 118 #define INT_SSI2_TM4C123 73 // SSI2 119 #define INT_SSI3_TM4C123 74 // SSI3 120 #define INT_UART3_TM4C123 75 // UART3 121 #define INT_UART4_TM4C123 76 // UART4 122 #define INT_UART5_TM4C123 77 // UART5 123 #define INT_UART6_TM4C123 78 // UART6 124 #define INT_UART7_TM4C123 79 // UART7 125 #define INT_I2C2_TM4C123 84 // I2C2 126 #define INT_I2C3_TM4C123 85 // I2C3 127 #define INT_TIMER4A_TM4C123 86 // 16/32-Bit Timer 4A 128 #define INT_TIMER4B_TM4C123 87 // 16/32-Bit Timer 4B 129 #define INT_TIMER5A_TM4C123 108 // 16/32-Bit Timer 5A 130 #define INT_TIMER5B_TM4C123 109 // 16/32-Bit Timer 5B 131 #define INT_WTIMER0A_TM4C123 110 // 32/64-Bit Timer 0A 132 #define INT_WTIMER0B_TM4C123 111 // 32/64-Bit Timer 0B 133 #define INT_WTIMER1A_TM4C123 112 // 32/64-Bit Timer 1A 134 #define INT_WTIMER1B_TM4C123 113 // 32/64-Bit Timer 1B 135 #define INT_WTIMER2A_TM4C123 114 // 32/64-Bit Timer 2A 136 #define INT_WTIMER2B_TM4C123 115 // 32/64-Bit Timer 2B 137 #define INT_WTIMER3A_TM4C123 116 // 32/64-Bit Timer 3A 138 #define INT_WTIMER3B_TM4C123 117 // 32/64-Bit Timer 3B 139 #define INT_WTIMER4A_TM4C123 118 // 32/64-Bit Timer 4A 140 #define INT_WTIMER4B_TM4C123 119 // 32/64-Bit Timer 4B 141 #define INT_WTIMER5A_TM4C123 120 // 32/64-Bit Timer 5A 142 #define INT_WTIMER5B_TM4C123 121 // 32/64-Bit Timer 5B 143 #define INT_SYSEXC_TM4C123 122 // System Exception (imprecise) 144 #define INT_I2C4_TM4C123 125 // I2C4 145 #define INT_I2C5_TM4C123 126 // I2C5 146 #define INT_GPIOM_TM4C123 127 // GPIO Port M 147 #define INT_GPION_TM4C123 128 // GPIO Port N 148 #define INT_GPIOP0_TM4C123 132 // GPIO Port P (Summary or P0) 149 #define INT_GPIOP1_TM4C123 133 // GPIO Port P1 150 #define INT_GPIOP2_TM4C123 134 // GPIO Port P2 151 #define INT_GPIOP3_TM4C123 135 // GPIO Port P3 152 #define INT_GPIOP4_TM4C123 136 // GPIO Port P4 153 #define INT_GPIOP5_TM4C123 137 // GPIO Port P5 154 #define INT_GPIOP6_TM4C123 138 // GPIO Port P6 155 #define INT_GPIOP7_TM4C123 139 // GPIO Port P7 156 #define INT_GPIOQ0_TM4C123 140 // GPIO Port Q (Summary or Q0) 157 #define INT_GPIOQ1_TM4C123 141 // GPIO Port Q1 158 #define INT_GPIOQ2_TM4C123 142 // GPIO Port Q2 159 #define INT_GPIOQ3_TM4C123 143 // GPIO Port Q3 160 #define INT_GPIOQ4_TM4C123 144 // GPIO Port Q4 161 #define INT_GPIOQ5_TM4C123 145 // GPIO Port Q5 162 #define INT_GPIOQ6_TM4C123 146 // GPIO Port Q6 163 #define INT_GPIOQ7_TM4C123 147 // GPIO Port Q7 164 #define INT_PWM1_0_TM4C123 150 // PWM1 Generator 0 165 #define INT_PWM1_1_TM4C123 151 // PWM1 Generator 1 166 #define INT_PWM1_2_TM4C123 152 // PWM1 Generator 2 167 #define INT_PWM1_3_TM4C123 153 // PWM1 Generator 3 168 #define INT_PWM1_FAULT_TM4C123 154 // PWM1 Fault 169 #define NUM_INTERRUPTS_TM4C123 155 170 171 //***************************************************************************** 172 // 173 // TM4C129 Class Interrupts 174 // 175 //***************************************************************************** 176 #define INT_GPIOA_TM4C129 16 // GPIO Port A 177 #define INT_GPIOB_TM4C129 17 // GPIO Port B 178 #define INT_GPIOC_TM4C129 18 // GPIO Port C 179 #define INT_GPIOD_TM4C129 19 // GPIO Port D 180 #define INT_GPIOE_TM4C129 20 // GPIO Port E 181 #define INT_UART0_TM4C129 21 // UART0 182 #define INT_UART1_TM4C129 22 // UART1 183 #define INT_SSI0_TM4C129 23 // SSI0 184 #define INT_I2C0_TM4C129 24 // I2C0 185 #define INT_PWM0_FAULT_TM4C129 25 // PWM Fault 186 #define INT_PWM0_0_TM4C129 26 // PWM Generator 0 187 #define INT_PWM0_1_TM4C129 27 // PWM Generator 1 188 #define INT_PWM0_2_TM4C129 28 // PWM Generator 2 189 #define INT_QEI0_TM4C129 29 // QEI0 190 #define INT_ADC0SS0_TM4C129 30 // ADC0 Sequence 0 191 #define INT_ADC0SS1_TM4C129 31 // ADC0 Sequence 1 192 #define INT_ADC0SS2_TM4C129 32 // ADC0 Sequence 2 193 #define INT_ADC0SS3_TM4C129 33 // ADC0 Sequence 3 194 #define INT_WATCHDOG_TM4C129 34 // Watchdog Timers 0 and 1 195 #define INT_TIMER0A_TM4C129 35 // 16/32-Bit Timer 0A 196 #define INT_TIMER0B_TM4C129 36 // 16/32-Bit Timer 0B 197 #define INT_TIMER1A_TM4C129 37 // 16/32-Bit Timer 1A 198 #define INT_TIMER1B_TM4C129 38 // 16/32-Bit Timer 1B 199 #define INT_TIMER2A_TM4C129 39 // 16/32-Bit Timer 2A 200 #define INT_TIMER2B_TM4C129 40 // 16/32-Bit Timer 2B 201 #define INT_COMP0_TM4C129 41 // Analog Comparator 0 202 #define INT_COMP1_TM4C129 42 // Analog Comparator 1 203 #define INT_COMP2_TM4C129 43 // Analog Comparator 2 204 #define INT_SYSCTL_TM4C129 44 // System Control 205 #define INT_FLASH_TM4C129 45 // Flash Memory Control 206 #define INT_GPIOF_TM4C129 46 // GPIO Port F 207 #define INT_GPIOG_TM4C129 47 // GPIO Port G 208 #define INT_GPIOH_TM4C129 48 // GPIO Port H 209 #define INT_UART2_TM4C129 49 // UART2 210 #define INT_SSI1_TM4C129 50 // SSI1 211 #define INT_TIMER3A_TM4C129 51 // 16/32-Bit Timer 3A 212 #define INT_TIMER3B_TM4C129 52 // 16/32-Bit Timer 3B 213 #define INT_I2C1_TM4C129 53 // I2C1 214 #define INT_CAN0_TM4C129 54 // CAN 0 215 #define INT_CAN1_TM4C129 55 // CAN1 216 #define INT_EMAC0_TM4C129 56 // Ethernet MAC 217 #define INT_HIBERNATE_TM4C129 57 // HIB 218 #define INT_USB0_TM4C129 58 // USB MAC 219 #define INT_PWM0_3_TM4C129 59 // PWM Generator 3 220 #define INT_UDMA_TM4C129 60 // uDMA 0 Software 221 #define INT_UDMAERR_TM4C129 61 // uDMA 0 Error 222 #define INT_ADC1SS0_TM4C129 62 // ADC1 Sequence 0 223 #define INT_ADC1SS1_TM4C129 63 // ADC1 Sequence 1 224 #define INT_ADC1SS2_TM4C129 64 // ADC1 Sequence 2 225 #define INT_ADC1SS3_TM4C129 65 // ADC1 Sequence 3 226 #define INT_EPI0_TM4C129 66 // EPI 0 227 #define INT_GPIOJ_TM4C129 67 // GPIO Port J 228 #define INT_GPIOK_TM4C129 68 // GPIO Port K 229 #define INT_GPIOL_TM4C129 69 // GPIO Port L 230 #define INT_SSI2_TM4C129 70 // SSI 2 231 #define INT_SSI3_TM4C129 71 // SSI 3 232 #define INT_UART3_TM4C129 72 // UART 3 233 #define INT_UART4_TM4C129 73 // UART 4 234 #define INT_UART5_TM4C129 74 // UART 5 235 #define INT_UART6_TM4C129 75 // UART 6 236 #define INT_UART7_TM4C129 76 // UART 7 237 #define INT_I2C2_TM4C129 77 // I2C 2 238 #define INT_I2C3_TM4C129 78 // I2C 3 239 #define INT_TIMER4A_TM4C129 79 // Timer 4A 240 #define INT_TIMER4B_TM4C129 80 // Timer 4B 241 #define INT_TIMER5A_TM4C129 81 // Timer 5A 242 #define INT_TIMER5B_TM4C129 82 // Timer 5B 243 #define INT_SYSEXC_TM4C129 83 // Floating-Point Exception 244 // (imprecise) 245 #define INT_I2C4_TM4C129 86 // I2C 4 246 #define INT_I2C5_TM4C129 87 // I2C 5 247 #define INT_GPIOM_TM4C129 88 // GPIO Port M 248 #define INT_GPION_TM4C129 89 // GPIO Port N 249 #define INT_TAMPER0_TM4C129 91 // Tamper 250 #define INT_GPIOP0_TM4C129 92 // GPIO Port P (Summary or P0) 251 #define INT_GPIOP1_TM4C129 93 // GPIO Port P1 252 #define INT_GPIOP2_TM4C129 94 // GPIO Port P2 253 #define INT_GPIOP3_TM4C129 95 // GPIO Port P3 254 #define INT_GPIOP4_TM4C129 96 // GPIO Port P4 255 #define INT_GPIOP5_TM4C129 97 // GPIO Port P5 256 #define INT_GPIOP6_TM4C129 98 // GPIO Port P6 257 #define INT_GPIOP7_TM4C129 99 // GPIO Port P7 258 #define INT_GPIOQ0_TM4C129 100 // GPIO Port Q (Summary or Q0) 259 #define INT_GPIOQ1_TM4C129 101 // GPIO Port Q1 260 #define INT_GPIOQ2_TM4C129 102 // GPIO Port Q2 261 #define INT_GPIOQ3_TM4C129 103 // GPIO Port Q3 262 #define INT_GPIOQ4_TM4C129 104 // GPIO Port Q4 263 #define INT_GPIOQ5_TM4C129 105 // GPIO Port Q5 264 #define INT_GPIOQ6_TM4C129 106 // GPIO Port Q6 265 #define INT_GPIOQ7_TM4C129 107 // GPIO Port Q7 266 #define INT_GPIOR_TM4C129 108 // GPIO Port R 267 #define INT_GPIOS_TM4C129 109 // GPIO Port S 268 #define INT_SHA0_TM4C129 110 // SHA/MD5 269 #define INT_AES0_TM4C129 111 // AES 270 #define INT_DES0_TM4C129 112 // DES 271 #define INT_LCD0_TM4C129 113 // LCD 272 #define INT_TIMER6A_TM4C129 114 // 16/32-Bit Timer 6A 273 #define INT_TIMER6B_TM4C129 115 // 16/32-Bit Timer 6B 274 #define INT_TIMER7A_TM4C129 116 // 16/32-Bit Timer 7A 275 #define INT_TIMER7B_TM4C129 117 // 16/32-Bit Timer 7B 276 #define INT_I2C6_TM4C129 118 // I2C 6 277 #define INT_I2C7_TM4C129 119 // I2C 7 278 #define INT_ONEWIRE0_TM4C129 121 // 1-Wire 279 #define INT_I2C8_TM4C129 125 // I2C 8 280 #define INT_I2C9_TM4C129 126 // I2C 9 281 #define INT_GPIOT_TM4C129 127 // GPIO T 282 #define NUM_INTERRUPTS_TM4C129 129 283 284 //***************************************************************************** 285 // 286 // TM4C123 Interrupt Class Definition 287 // 288 //***************************************************************************** 289 #if defined(TARGET_IS_TM4C123_RA1) || defined(TARGET_IS_TM4C123_RA2) || \ 290 defined(TARGET_IS_TM4C123_RA3) || defined(TARGET_IS_TM4C123_RB0) || \ 291 defined(TARGET_IS_TM4C123_RB1) || defined(PART_TM4C1230C3PM) || \ 292 defined(PART_TM4C1230D5PM) || defined(PART_TM4C1230E6PM) || \ 293 defined(PART_TM4C1230H6PM) || defined(PART_TM4C1231C3PM) || \ 294 defined(PART_TM4C1231D5PM) || defined(PART_TM4C1231D5PZ) || \ 295 defined(PART_TM4C1231E6PM) || defined(PART_TM4C1231E6PZ) || \ 296 defined(PART_TM4C1231H6PM) || defined(PART_TM4C1231H6PZ) || \ 297 defined(PART_TM4C1232C3PM) || defined(PART_TM4C1232D5PM) || \ 298 defined(PART_TM4C1232E6PM) || defined(PART_TM4C1232H6PM) || \ 299 defined(PART_TM4C1233C3PM) || defined(PART_TM4C1233D5PM) || \ 300 defined(PART_TM4C1233D5PZ) || defined(PART_TM4C1233E6PM) || \ 301 defined(PART_TM4C1233E6PZ) || defined(PART_TM4C1233H6PM) || \ 302 defined(PART_TM4C1233H6PZ) || defined(PART_TM4C1236D5PM) || \ 303 defined(PART_TM4C1236E6PM) || defined(PART_TM4C1236H6PM) || \ 304 defined(PART_TM4C1237D5PM) || defined(PART_TM4C1237D5PZ) || \ 305 defined(PART_TM4C1237E6PM) || defined(PART_TM4C1237E6PZ) || \ 306 defined(PART_TM4C1237H6PM) || defined(PART_TM4C1237H6PZ) || \ 307 defined(PART_TM4C123AE6PM) || defined(PART_TM4C123AH6PM) || \ 308 defined(PART_TM4C123BE6PM) || defined(PART_TM4C123BE6PZ) || \ 309 defined(PART_TM4C123BH6PM) || defined(PART_TM4C123BH6PZ) || \ 310 defined(PART_TM4C123FE6PM) || defined(PART_TM4C123FH6PM) || \ 311 defined(PART_TM4C123GE6PM) || defined(PART_TM4C123GE6PZ) || \ 312 defined(PART_TM4C123GH6PM) || defined(PART_TM4C123GH6PZ) || \ 313 defined(PART_TM4C1231H6PGE) || defined(PART_TM4C1233H6PGE) || \ 314 defined(PART_TM4C1237H6PGE) || defined(PART_TM4C123BH6PGE) || \ 315 defined(PART_TM4C123BH6ZRB) || defined(PART_TM4C123GH6PGE) || \ 316 defined(PART_TM4C123GH6ZRB) || defined(PART_TM4C123GH6ZXR) 317 #define INT_RESOLVE(intname, class) intname##TM4C123 318 319 //***************************************************************************** 320 // 321 // TM4C129 Interrupt Class Definition 322 // 323 //***************************************************************************** 324 #elif defined(TARGET_IS_TM4C129_RA0) || defined(PART_TM4C1290NCPDT) || \ 325 defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT) || \ 326 defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || \ 327 defined(PART_TM4C1294NCPDT) || defined(PART_TM4C1294NCZAD) || \ 328 defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD) || \ 329 defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || \ 330 defined(PART_TM4C129CNCZAD) || defined(PART_TM4C129DNCPDT) || \ 331 defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT) || \ 332 defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || \ 333 defined(PART_TM4C129LNCZAD) || defined(PART_TM4C129XKCZAD) || \ 334 defined(PART_TM4C129XNCZAD) 335 #define INT_RESOLVE(intname, class) intname##TM4C129 336 #else 337 #define INT_DEVICE_CLASS "UNKNOWN" 338 #endif 339 340 //***************************************************************************** 341 // 342 // Macros to resolve the INT_PERIPH_CLASS name to a common INT_PERIPH name. 343 // 344 //***************************************************************************** 345 #define INT_CONCAT(intname, class) INT_RESOLVE(intname, class) 346 347 //***************************************************************************** 348 // 349 // The following are defines for the interrupt assignments. 350 // 351 //***************************************************************************** 352 #define INT_ADC0SS0 INT_CONCAT(INT_ADC0SS0_, INT_DEVICE_CLASS) 353 #define INT_ADC0SS1 INT_CONCAT(INT_ADC0SS1_, INT_DEVICE_CLASS) 354 #define INT_ADC0SS2 INT_CONCAT(INT_ADC0SS2_, INT_DEVICE_CLASS) 355 #define INT_ADC0SS3 INT_CONCAT(INT_ADC0SS3_, INT_DEVICE_CLASS) 356 #define INT_ADC1SS0 INT_CONCAT(INT_ADC1SS0_, INT_DEVICE_CLASS) 357 #define INT_ADC1SS1 INT_CONCAT(INT_ADC1SS1_, INT_DEVICE_CLASS) 358 #define INT_ADC1SS2 INT_CONCAT(INT_ADC1SS2_, INT_DEVICE_CLASS) 359 #define INT_ADC1SS3 INT_CONCAT(INT_ADC1SS3_, INT_DEVICE_CLASS) 360 #define INT_AES0 INT_CONCAT(INT_AES0_, INT_DEVICE_CLASS) 361 #define INT_CAN0 INT_CONCAT(INT_CAN0_, INT_DEVICE_CLASS) 362 #define INT_CAN1 INT_CONCAT(INT_CAN1_, INT_DEVICE_CLASS) 363 #define INT_COMP0 INT_CONCAT(INT_COMP0_, INT_DEVICE_CLASS) 364 #define INT_COMP1 INT_CONCAT(INT_COMP1_, INT_DEVICE_CLASS) 365 #define INT_COMP2 INT_CONCAT(INT_COMP2_, INT_DEVICE_CLASS) 366 #define INT_DES0 INT_CONCAT(INT_DES0_, INT_DEVICE_CLASS) 367 #define INT_EMAC0 INT_CONCAT(INT_EMAC0_, INT_DEVICE_CLASS) 368 #define INT_EPI0 INT_CONCAT(INT_EPI0_, INT_DEVICE_CLASS) 369 #define INT_FLASH INT_CONCAT(INT_FLASH_, INT_DEVICE_CLASS) 370 #define INT_GPIOA INT_CONCAT(INT_GPIOA_, INT_DEVICE_CLASS) 371 #define INT_GPIOB INT_CONCAT(INT_GPIOB_, INT_DEVICE_CLASS) 372 #define INT_GPIOC INT_CONCAT(INT_GPIOC_, INT_DEVICE_CLASS) 373 #define INT_GPIOD INT_CONCAT(INT_GPIOD_, INT_DEVICE_CLASS) 374 #define INT_GPIOE INT_CONCAT(INT_GPIOE_, INT_DEVICE_CLASS) 375 #define INT_GPIOF INT_CONCAT(INT_GPIOF_, INT_DEVICE_CLASS) 376 #define INT_GPIOG INT_CONCAT(INT_GPIOG_, INT_DEVICE_CLASS) 377 #define INT_GPIOH INT_CONCAT(INT_GPIOH_, INT_DEVICE_CLASS) 378 #define INT_GPIOJ INT_CONCAT(INT_GPIOJ_, INT_DEVICE_CLASS) 379 #define INT_GPIOK INT_CONCAT(INT_GPIOK_, INT_DEVICE_CLASS) 380 #define INT_GPIOL INT_CONCAT(INT_GPIOL_, INT_DEVICE_CLASS) 381 #define INT_GPIOM INT_CONCAT(INT_GPIOM_, INT_DEVICE_CLASS) 382 #define INT_GPION INT_CONCAT(INT_GPION_, INT_DEVICE_CLASS) 383 #define INT_GPIOP0 INT_CONCAT(INT_GPIOP0_, INT_DEVICE_CLASS) 384 #define INT_GPIOP1 INT_CONCAT(INT_GPIOP1_, INT_DEVICE_CLASS) 385 #define INT_GPIOP2 INT_CONCAT(INT_GPIOP2_, INT_DEVICE_CLASS) 386 #define INT_GPIOP3 INT_CONCAT(INT_GPIOP3_, INT_DEVICE_CLASS) 387 #define INT_GPIOP4 INT_CONCAT(INT_GPIOP4_, INT_DEVICE_CLASS) 388 #define INT_GPIOP5 INT_CONCAT(INT_GPIOP5_, INT_DEVICE_CLASS) 389 #define INT_GPIOP6 INT_CONCAT(INT_GPIOP6_, INT_DEVICE_CLASS) 390 #define INT_GPIOP7 INT_CONCAT(INT_GPIOP7_, INT_DEVICE_CLASS) 391 #define INT_GPIOQ0 INT_CONCAT(INT_GPIOQ0_, INT_DEVICE_CLASS) 392 #define INT_GPIOQ1 INT_CONCAT(INT_GPIOQ1_, INT_DEVICE_CLASS) 393 #define INT_GPIOQ2 INT_CONCAT(INT_GPIOQ2_, INT_DEVICE_CLASS) 394 #define INT_GPIOQ3 INT_CONCAT(INT_GPIOQ3_, INT_DEVICE_CLASS) 395 #define INT_GPIOQ4 INT_CONCAT(INT_GPIOQ4_, INT_DEVICE_CLASS) 396 #define INT_GPIOQ5 INT_CONCAT(INT_GPIOQ5_, INT_DEVICE_CLASS) 397 #define INT_GPIOQ6 INT_CONCAT(INT_GPIOQ6_, INT_DEVICE_CLASS) 398 #define INT_GPIOQ7 INT_CONCAT(INT_GPIOQ7_, INT_DEVICE_CLASS) 399 #define INT_GPIOR INT_CONCAT(INT_GPIOR_, INT_DEVICE_CLASS) 400 #define INT_GPIOS INT_CONCAT(INT_GPIOS_, INT_DEVICE_CLASS) 401 #define INT_GPIOT INT_CONCAT(INT_GPIOT_, INT_DEVICE_CLASS) 402 #define INT_HIBERNATE INT_CONCAT(INT_HIBERNATE_, INT_DEVICE_CLASS) 403 #define INT_I2C0 INT_CONCAT(INT_I2C0_, INT_DEVICE_CLASS) 404 #define INT_I2C1 INT_CONCAT(INT_I2C1_, INT_DEVICE_CLASS) 405 #define INT_I2C2 INT_CONCAT(INT_I2C2_, INT_DEVICE_CLASS) 406 #define INT_I2C3 INT_CONCAT(INT_I2C3_, INT_DEVICE_CLASS) 407 #define INT_I2C4 INT_CONCAT(INT_I2C4_, INT_DEVICE_CLASS) 408 #define INT_I2C5 INT_CONCAT(INT_I2C5_, INT_DEVICE_CLASS) 409 #define INT_I2C6 INT_CONCAT(INT_I2C6_, INT_DEVICE_CLASS) 410 #define INT_I2C7 INT_CONCAT(INT_I2C7_, INT_DEVICE_CLASS) 411 #define INT_I2C8 INT_CONCAT(INT_I2C8_, INT_DEVICE_CLASS) 412 #define INT_I2C9 INT_CONCAT(INT_I2C9_, INT_DEVICE_CLASS) 413 #define INT_LCD0 INT_CONCAT(INT_LCD0_, INT_DEVICE_CLASS) 414 #define INT_ONEWIRE0 INT_CONCAT(INT_ONEWIRE0_, INT_DEVICE_CLASS) 415 #define INT_PWM0_0 INT_CONCAT(INT_PWM0_0_, INT_DEVICE_CLASS) 416 #define INT_PWM0_1 INT_CONCAT(INT_PWM0_1_, INT_DEVICE_CLASS) 417 #define INT_PWM0_2 INT_CONCAT(INT_PWM0_2_, INT_DEVICE_CLASS) 418 #define INT_PWM0_3 INT_CONCAT(INT_PWM0_3_, INT_DEVICE_CLASS) 419 #define INT_PWM0_FAULT INT_CONCAT(INT_PWM0_FAULT_, INT_DEVICE_CLASS) 420 #define INT_PWM1_0 INT_CONCAT(INT_PWM1_0_, INT_DEVICE_CLASS) 421 #define INT_PWM1_1 INT_CONCAT(INT_PWM1_1_, INT_DEVICE_CLASS) 422 #define INT_PWM1_2 INT_CONCAT(INT_PWM1_2_, INT_DEVICE_CLASS) 423 #define INT_PWM1_3 INT_CONCAT(INT_PWM1_3_, INT_DEVICE_CLASS) 424 #define INT_PWM1_FAULT INT_CONCAT(INT_PWM1_FAULT_, INT_DEVICE_CLASS) 425 #define INT_QEI0 INT_CONCAT(INT_QEI0_, INT_DEVICE_CLASS) 426 #define INT_QEI1 INT_CONCAT(INT_QEI1_, INT_DEVICE_CLASS) 427 #define INT_SHA0 INT_CONCAT(INT_SHA0_, INT_DEVICE_CLASS) 428 #define INT_SSI0 INT_CONCAT(INT_SSI0_, INT_DEVICE_CLASS) 429 #define INT_SSI1 INT_CONCAT(INT_SSI1_, INT_DEVICE_CLASS) 430 #define INT_SSI2 INT_CONCAT(INT_SSI2_, INT_DEVICE_CLASS) 431 #define INT_SSI3 INT_CONCAT(INT_SSI3_, INT_DEVICE_CLASS) 432 #define INT_SYSCTL INT_CONCAT(INT_SYSCTL_, INT_DEVICE_CLASS) 433 #define INT_SYSEXC INT_CONCAT(INT_SYSEXC_, INT_DEVICE_CLASS) 434 #define INT_TAMPER0 INT_CONCAT(INT_TAMPER0_, INT_DEVICE_CLASS) 435 #define INT_TIMER0A INT_CONCAT(INT_TIMER0A_, INT_DEVICE_CLASS) 436 #define INT_TIMER0B INT_CONCAT(INT_TIMER0B_, INT_DEVICE_CLASS) 437 #define INT_TIMER1A INT_CONCAT(INT_TIMER1A_, INT_DEVICE_CLASS) 438 #define INT_TIMER1B INT_CONCAT(INT_TIMER1B_, INT_DEVICE_CLASS) 439 #define INT_TIMER2A INT_CONCAT(INT_TIMER2A_, INT_DEVICE_CLASS) 440 #define INT_TIMER2B INT_CONCAT(INT_TIMER2B_, INT_DEVICE_CLASS) 441 #define INT_TIMER3A INT_CONCAT(INT_TIMER3A_, INT_DEVICE_CLASS) 442 #define INT_TIMER3B INT_CONCAT(INT_TIMER3B_, INT_DEVICE_CLASS) 443 #define INT_TIMER4A INT_CONCAT(INT_TIMER4A_, INT_DEVICE_CLASS) 444 #define INT_TIMER4B INT_CONCAT(INT_TIMER4B_, INT_DEVICE_CLASS) 445 #define INT_TIMER5A INT_CONCAT(INT_TIMER5A_, INT_DEVICE_CLASS) 446 #define INT_TIMER5B INT_CONCAT(INT_TIMER5B_, INT_DEVICE_CLASS) 447 #define INT_TIMER6A INT_CONCAT(INT_TIMER6A_, INT_DEVICE_CLASS) 448 #define INT_TIMER6B INT_CONCAT(INT_TIMER6B_, INT_DEVICE_CLASS) 449 #define INT_TIMER7A INT_CONCAT(INT_TIMER7A_, INT_DEVICE_CLASS) 450 #define INT_TIMER7B INT_CONCAT(INT_TIMER7B_, INT_DEVICE_CLASS) 451 #define INT_UART0 INT_CONCAT(INT_UART0_, INT_DEVICE_CLASS) 452 #define INT_UART1 INT_CONCAT(INT_UART1_, INT_DEVICE_CLASS) 453 #define INT_UART2 INT_CONCAT(INT_UART2_, INT_DEVICE_CLASS) 454 #define INT_UART3 INT_CONCAT(INT_UART3_, INT_DEVICE_CLASS) 455 #define INT_UART4 INT_CONCAT(INT_UART4_, INT_DEVICE_CLASS) 456 #define INT_UART5 INT_CONCAT(INT_UART5_, INT_DEVICE_CLASS) 457 #define INT_UART6 INT_CONCAT(INT_UART6_, INT_DEVICE_CLASS) 458 #define INT_UART7 INT_CONCAT(INT_UART7_, INT_DEVICE_CLASS) 459 #define INT_UDMA INT_CONCAT(INT_UDMA_, INT_DEVICE_CLASS) 460 #define INT_UDMAERR INT_CONCAT(INT_UDMAERR_, INT_DEVICE_CLASS) 461 #define INT_USB0 INT_CONCAT(INT_USB0_, INT_DEVICE_CLASS) 462 #define INT_WATCHDOG INT_CONCAT(INT_WATCHDOG_, INT_DEVICE_CLASS) 463 #define INT_WTIMER0A INT_CONCAT(INT_WTIMER0A_, INT_DEVICE_CLASS) 464 #define INT_WTIMER0B INT_CONCAT(INT_WTIMER0B_, INT_DEVICE_CLASS) 465 #define INT_WTIMER1A INT_CONCAT(INT_WTIMER1A_, INT_DEVICE_CLASS) 466 #define INT_WTIMER1B INT_CONCAT(INT_WTIMER1B_, INT_DEVICE_CLASS) 467 #define INT_WTIMER2A INT_CONCAT(INT_WTIMER2A_, INT_DEVICE_CLASS) 468 #define INT_WTIMER2B INT_CONCAT(INT_WTIMER2B_, INT_DEVICE_CLASS) 469 #define INT_WTIMER3A INT_CONCAT(INT_WTIMER3A_, INT_DEVICE_CLASS) 470 #define INT_WTIMER3B INT_CONCAT(INT_WTIMER3B_, INT_DEVICE_CLASS) 471 #define INT_WTIMER4A INT_CONCAT(INT_WTIMER4A_, INT_DEVICE_CLASS) 472 #define INT_WTIMER4B INT_CONCAT(INT_WTIMER4B_, INT_DEVICE_CLASS) 473 #define INT_WTIMER5A INT_CONCAT(INT_WTIMER5A_, INT_DEVICE_CLASS) 474 #define INT_WTIMER5B INT_CONCAT(INT_WTIMER5B_, INT_DEVICE_CLASS) 475 476 //***************************************************************************** 477 // 478 // The following are defines for the total number of interrupts. 479 // 480 //***************************************************************************** 481 #define NUM_INTERRUPTS INT_CONCAT(NUM_INTERRUPTS_, INT_DEVICE_CLASS) 482 483 //***************************************************************************** 484 // 485 // The following are defines for the total number of priority levels. 486 // 487 //***************************************************************************** 488 #define NUM_PRIORITY 8 489 #define NUM_PRIORITY_BITS 3 490 491 #endif // __HW_INTS_H__ 492