1 //***************************************************************************** 2 // 3 // hw_lcd.h - Defines and macros used when accessing the LCD controller. 4 // 5 // Copyright (c) 2011-2017 Texas Instruments Incorporated. All rights reserved. 6 // Software License Agreement 7 // 8 // Redistribution and use in source and binary forms, with or without 9 // modification, are permitted provided that the following conditions 10 // are met: 11 // 12 // Redistributions of source code must retain the above copyright 13 // notice, this list of conditions and the following disclaimer. 14 // 15 // Redistributions in binary form must reproduce the above copyright 16 // notice, this list of conditions and the following disclaimer in the 17 // documentation and/or other materials provided with the 18 // distribution. 19 // 20 // Neither the name of Texas Instruments Incorporated nor the names of 21 // its contributors may be used to endorse or promote products derived 22 // from this software without specific prior written permission. 23 // 24 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 27 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 28 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 29 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 30 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 34 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 // 36 // This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. 37 // 38 //***************************************************************************** 39 40 #ifndef __HW_LCD_H__ 41 #define __HW_LCD_H__ 42 43 //***************************************************************************** 44 // 45 // The following are defines for the LCD register offsets. 46 // 47 //***************************************************************************** 48 #define LCD_O_PID 0x00000000 // LCD PID Register Format 49 #define LCD_O_CTL 0x00000004 // LCD Control 50 #define LCD_O_LIDDCTL 0x0000000C // LCD LIDD Control 51 #define LCD_O_LIDDCS0CFG 0x00000010 // LCD LIDD CS0 Configuration 52 #define LCD_O_LIDDCS0ADDR 0x00000014 // LIDD CS0 Read/Write Address 53 #define LCD_O_LIDDCS0DATA 0x00000018 // LIDD CS0 Data Read/Write 54 // Initiation 55 #define LCD_O_LIDDCS1CFG 0x0000001C // LIDD CS1 Configuration 56 #define LCD_O_LIDDCS1ADDR 0x00000020 // LIDD CS1 Address Read/Write 57 // Initiation 58 #define LCD_O_LIDDCS1DATA 0x00000024 // LIDD CS1 Data Read/Write 59 // Initiation 60 #define LCD_O_RASTRCTL 0x00000028 // LCD Raster Control 61 #define LCD_O_RASTRTIM0 0x0000002C // LCD Raster Timing 0 62 #define LCD_O_RASTRTIM1 0x00000030 // LCD Raster Timing 1 63 #define LCD_O_RASTRTIM2 0x00000034 // LCD Raster Timing 2 64 #define LCD_O_RASTRSUBP1 0x00000038 // LCD Raster Subpanel Display 1 65 #define LCD_O_RASTRSUBP2 0x0000003C // LCD Raster Subpanel Display 2 66 #define LCD_O_DMACTL 0x00000040 // LCD DMA Control 67 #define LCD_O_DMABAFB0 0x00000044 // LCD DMA Frame Buffer 0 Base 68 // Address 69 #define LCD_O_DMACAFB0 0x00000048 // LCD DMA Frame Buffer 0 Ceiling 70 // Address 71 #define LCD_O_DMABAFB1 0x0000004C // LCD DMA Frame Buffer 1 Base 72 // Address 73 #define LCD_O_DMACAFB1 0x00000050 // LCD DMA Frame Buffer 1 Ceiling 74 // Address 75 #define LCD_O_SYSCFG 0x00000054 // LCD System Configuration 76 // Register 77 #define LCD_O_RISSET 0x00000058 // LCD Interrupt Raw Status and Set 78 // Register 79 #define LCD_O_MISCLR 0x0000005C // LCD Interrupt Status and Clear 80 #define LCD_O_IM 0x00000060 // LCD Interrupt Mask 81 #define LCD_O_IENC 0x00000064 // LCD Interrupt Enable Clear 82 #define LCD_O_CLKEN 0x0000006C // LCD Clock Enable 83 #define LCD_O_CLKRESET 0x00000070 // LCD Clock Resets 84 85 //***************************************************************************** 86 // 87 // The following are defines for the bit fields in the LCD_O_PID register. 88 // 89 //***************************************************************************** 90 #define LCD_PID_MAJOR_M 0x00000700 // Major Release Number 91 #define LCD_PID_MINOR_M 0x0000003F // Minor Release Number 92 #define LCD_PID_MAJOR_S 8 93 #define LCD_PID_MINOR_S 0 94 95 //***************************************************************************** 96 // 97 // The following are defines for the bit fields in the LCD_O_CTL register. 98 // 99 //***************************************************************************** 100 #define LCD_CTL_CLKDIV_M 0x0000FF00 // Clock Divisor 101 #define LCD_CTL_UFLOWRST 0x00000002 // Underflow Restart 102 #define LCD_CTL_LCDMODE 0x00000001 // LCD Mode Select 103 #define LCD_CTL_CLKDIV_S 8 104 105 //***************************************************************************** 106 // 107 // The following are defines for the bit fields in the LCD_O_LIDDCTL register. 108 // 109 //***************************************************************************** 110 #define LCD_LIDDCTL_DMACS 0x00000200 // CS0/CS1 Select for LIDD DMA 111 // Writes 112 #define LCD_LIDDCTL_DMAEN 0x00000100 // LIDD DMA Enable 113 #define LCD_LIDDCTL_CS1E1 0x00000080 // Chip Select 1 (CS1)/Enable 1(E1) 114 // Polarity Control 115 #define LCD_LIDDCTL_CS0E0 0x00000040 // Chip Select 0 (CS0)/Enable 0 116 // (E0) Polarity Control 117 #define LCD_LIDDCTL_WRDIRINV 0x00000020 // Write Strobe (WR) /Direction 118 // (DIR) Polarity Control 119 #define LCD_LIDDCTL_RDEN 0x00000010 // Read Strobe (RD) /Direct Enable 120 // (EN) Polarity Control 121 #define LCD_LIDDCTL_ALE 0x00000008 // Address Latch Enable (ALE) 122 // Polarity Control 123 #define LCD_LIDDCTL_MODE_M 0x00000007 // LIDD Mode Select 124 #define LCD_LIDDCTL_MODE_SYNCM68 \ 125 0x00000000 // Synchronous Motorola 6800 Mode 126 #define LCD_LIDDCTL_MODE_ASYNCM68 \ 127 0x00000001 // Asynchronous Motorola 6800 Mode 128 #define LCD_LIDDCTL_MODE_SYNCM80 \ 129 0x00000002 // Synchronous Intel 8080 mode 130 #define LCD_LIDDCTL_MODE_ASYNCM80 \ 131 0x00000003 // Asynchronous Intel 8080 mode 132 #define LCD_LIDDCTL_MODE_ASYNCHIT \ 133 0x00000004 // Asynchronous Hitachi mode 134 135 //***************************************************************************** 136 // 137 // The following are defines for the bit fields in the LCD_O_LIDDCS0CFG 138 // register. 139 // 140 //***************************************************************************** 141 #define LCD_LIDDCS0CFG_WRSU_M 0xF8000000 // Write Strobe (WR) Set-Up Cycles 142 #define LCD_LIDDCS0CFG_WRDUR_M 0x07E00000 // Write Strobe (WR) Duration 143 // Cycles 144 #define LCD_LIDDCS0CFG_WRHOLD_M 0x001E0000 // Write Strobe (WR) Hold cycles 145 #define LCD_LIDDCS0CFG_RDSU_M 0x0001F000 // Read Strobe (RD) Set-Up cycles 146 #define LCD_LIDDCS0CFG_RDDUR_M 0x00000FC0 // Read Strobe (RD) Duration cycles 147 #define LCD_LIDDCS0CFG_RDHOLD_M 0x0000003C // Read Strobe (RD) Hold cycles 148 #define LCD_LIDDCS0CFG_GAP_M 0x00000003 // Field value defines the number 149 // of LCDMCLK cycles (GAP +1) 150 // between the end of one CS0 151 // (LCDAC) device access and the 152 // start of another CS0 (LCDAC) 153 // device access unless the two 154 // accesses are both reads 155 #define LCD_LIDDCS0CFG_WRSU_S 27 156 #define LCD_LIDDCS0CFG_WRDUR_S 21 157 #define LCD_LIDDCS0CFG_WRHOLD_S 17 158 #define LCD_LIDDCS0CFG_RDSU_S 12 159 #define LCD_LIDDCS0CFG_RDDUR_S 6 160 #define LCD_LIDDCS0CFG_RDHOLD_S 2 161 #define LCD_LIDDCS0CFG_GAP_S 0 162 163 //***************************************************************************** 164 // 165 // The following are defines for the bit fields in the LCD_O_LIDDCS0ADDR 166 // register. 167 // 168 //***************************************************************************** 169 #define LCD_LIDDCS0ADDR_CS0ADDR_M \ 170 0x0000FFFF // LCD Address 171 #define LCD_LIDDCS0ADDR_CS0ADDR_S \ 172 0 173 174 //***************************************************************************** 175 // 176 // The following are defines for the bit fields in the LCD_O_LIDDCS0DATA 177 // register. 178 // 179 //***************************************************************************** 180 #define LCD_LIDDCS0DATA_CS0DATA_M \ 181 0x0000FFFF // LCD Data Read/Write 182 #define LCD_LIDDCS0DATA_CS0DATA_S \ 183 0 184 185 //***************************************************************************** 186 // 187 // The following are defines for the bit fields in the LCD_O_LIDDCS1CFG 188 // register. 189 // 190 //***************************************************************************** 191 #define LCD_LIDDCS1CFG_WRSU_M 0xF8000000 // Write Strobe (WR) Set-Up Cycles 192 #define LCD_LIDDCS1CFG_WRDUR_M 0x07E00000 // Write Strobe (WR) Duration 193 // Cycles 194 #define LCD_LIDDCS1CFG_WRHOLD_M 0x001E0000 // Write Strobe (WR) Hold cycles 195 #define LCD_LIDDCS1CFG_RDSU_M 0x0001F000 // Read Strobe (RD) Set-Up cycles 196 #define LCD_LIDDCS1CFG_RDDUR_M 0x00000FC0 // Read Strobe (RD) Duration cycles 197 #define LCD_LIDDCS1CFG_RDHOLD_M 0x0000003C // Read Strobe (RD) Hold cycles 198 #define LCD_LIDDCS1CFG_GAP_M 0x00000003 // Field value defines the number 199 // of LCDMCLK cycles (GAP + 1) 200 // between the end of one CS1 201 // (LCDAC) device access and the 202 // start of another CS0 (LCDAC) 203 // device access unless the two 204 // accesses are both reads 205 #define LCD_LIDDCS1CFG_WRSU_S 27 206 #define LCD_LIDDCS1CFG_WRDUR_S 21 207 #define LCD_LIDDCS1CFG_WRHOLD_S 17 208 #define LCD_LIDDCS1CFG_RDSU_S 12 209 #define LCD_LIDDCS1CFG_RDDUR_S 6 210 #define LCD_LIDDCS1CFG_RDHOLD_S 2 211 #define LCD_LIDDCS1CFG_GAP_S 0 212 213 //***************************************************************************** 214 // 215 // The following are defines for the bit fields in the LCD_O_LIDDCS1ADDR 216 // register. 217 // 218 //***************************************************************************** 219 #define LCD_LIDDCS1ADDR_CS1ADDR_M \ 220 0x0000FFFF // LCD Address Bus 221 #define LCD_LIDDCS1ADDR_CS1ADDR_S \ 222 0 223 224 //***************************************************************************** 225 // 226 // The following are defines for the bit fields in the LCD_O_LIDDCS1DATA 227 // register. 228 // 229 //***************************************************************************** 230 #define LCD_LIDDCS1DATA_CS0DATA_M \ 231 0x0000FFFF // LCD Data Read/Write Initiation 232 #define LCD_LIDDCS1DATA_CS0DATA_S \ 233 0 234 235 //***************************************************************************** 236 // 237 // The following are defines for the bit fields in the LCD_O_RASTRCTL register. 238 // 239 //***************************************************************************** 240 #define LCD_RASTRCTL_TFT24UPCK 0x04000000 // 24-bit TFT Mode Packing 241 #define LCD_RASTRCTL_TFT24 0x02000000 // 24-Bit TFT Mode 242 #define LCD_RASTRCTL_FRMBUFSZ 0x01000000 // Frame Buffer Select 243 #define LCD_RASTRCTL_TFTMAP 0x00800000 // TFT Mode Alternate Signal 244 // Mapping for Palettized 245 // Framebuffer 246 #define LCD_RASTRCTL_NIBMODE 0x00400000 // Nibble Mode 247 #define LCD_RASTRCTL_PALMODE_M 0x00300000 // Pallette Loading Mode 248 #define LCD_RASTRCTL_PALMODE_PALDAT \ 249 0x00000000 // Palette and data loading, reset 250 // value 251 #define LCD_RASTRCTL_PALMODE_PAL \ 252 0x00100000 // Palette loading only 253 #define LCD_RASTRCTL_PALMODE_DAT \ 254 0x00200000 // Data loading only 255 #define LCD_RASTRCTL_REQDLY_M 0x000FF000 // Palette Loading Delay 256 #define LCD_RASTRCTL_MONO8B 0x00000200 // Mono 8-Bit 257 #define LCD_RASTRCTL_RDORDER 0x00000100 // Raster Data Order Select 258 #define LCD_RASTRCTL_LCDTFT 0x00000080 // LCD TFT 259 #define LCD_RASTRCTL_LCDBW 0x00000002 // LCD Monochrome 260 #define LCD_RASTRCTL_LCDEN 0x00000001 // LCD Controller Enable for Raster 261 // Operations 262 #define LCD_RASTRCTL_REQDLY_S 12 263 264 //***************************************************************************** 265 // 266 // The following are defines for the bit fields in the LCD_O_RASTRTIM0 267 // register. 268 // 269 //***************************************************************************** 270 #define LCD_RASTRTIM0_HBP_M 0xFF000000 // Horizontal Back Porch Lowbits 271 #define LCD_RASTRTIM0_HFP_M 0x00FF0000 // Horizontal Front Porch Lowbits 272 #define LCD_RASTRTIM0_HSW_M 0x0000FC00 // Horizontal Sync Pulse Width 273 // Lowbits 274 #define LCD_RASTRTIM0_PPL_M 0x000003F0 // Pixels-per-line LSB[9:4] 275 #define LCD_RASTRTIM0_MSBPPL 0x00000008 // Pixels-per-line MSB[10] 276 #define LCD_RASTRTIM0_HBP_S 24 277 #define LCD_RASTRTIM0_HFP_S 16 278 #define LCD_RASTRTIM0_HSW_S 10 279 #define LCD_RASTRTIM0_PPL_S 4 280 #define LCD_RASTRTIM0_MSBPPL_S 3 281 282 //***************************************************************************** 283 // 284 // The following are defines for the bit fields in the LCD_O_RASTRTIM1 285 // register. 286 // 287 //***************************************************************************** 288 #define LCD_RASTRTIM1_VBP_M 0xFF000000 // Vertical Back Porch 289 #define LCD_RASTRTIM1_VFP_M 0x00FF0000 // Vertical Front Porch 290 #define LCD_RASTRTIM1_VSW_M 0x0000FC00 // Vertical Sync Width Pulse 291 #define LCD_RASTRTIM1_LPP_M 0x000003FF // Lines Per Panel 292 #define LCD_RASTRTIM1_VBP_S 24 293 #define LCD_RASTRTIM1_VFP_S 16 294 #define LCD_RASTRTIM1_VSW_S 10 295 #define LCD_RASTRTIM1_LPP_S 0 296 297 //***************************************************************************** 298 // 299 // The following are defines for the bit fields in the LCD_O_RASTRTIM2 300 // register. 301 // 302 //***************************************************************************** 303 #define LCD_RASTRTIM2_HSW_M 0x78000000 // Bits 9:6 of the horizontal sync 304 // width field 305 #define LCD_RASTRTIM2_MSBLPP 0x04000000 // MSB of Lines Per Panel 306 #define LCD_RASTRTIM2_PXLCLKCTL 0x02000000 // Hsync/Vsync Pixel Clock Control 307 // On/Off 308 #define LCD_RASTRTIM2_PSYNCRF 0x01000000 // Program HSYNC/VSYNC Rise or Fall 309 #define LCD_RASTRTIM2_INVOE 0x00800000 // Invert Output Enable 310 #define LCD_RASTRTIM2_INVPXLCLK 0x00400000 // Invert Pixel Clock 311 #define LCD_RASTRTIM2_IHS 0x00200000 // Invert Hysync 312 #define LCD_RASTRTIM2_IVS 0x00100000 // Invert Vsync 313 #define LCD_RASTRTIM2_ACBI_M 0x000F0000 // AC Bias Pins Transitions per 314 // Interrupt 315 #define LCD_RASTRTIM2_ACBF_M 0x0000FF00 // AC Bias Pin Frequency 316 #define LCD_RASTRTIM2_MSBHBP_M 0x00000030 // Bits 9:8 of the horizontal back 317 // porch field 318 #define LCD_RASTRTIM2_MSBHFP_M 0x00000003 // Bits 9:8 of the horizontal front 319 // porch field 320 #define LCD_RASTRTIM2_HSW_S 27 321 #define LCD_RASTRTIM2_MSBLPP_S 26 322 #define LCD_RASTRTIM2_ACBI_S 16 323 #define LCD_RASTRTIM2_ACBF_S 8 324 #define LCD_RASTRTIM2_MSBHBP_S 4 325 #define LCD_RASTRTIM2_MSBHFP_S 0 326 327 //***************************************************************************** 328 // 329 // The following are defines for the bit fields in the LCD_O_RASTRSUBP1 330 // register. 331 // 332 //***************************************************************************** 333 #define LCD_RASTRSUBP1_SPEN 0x80000000 // Sub Panel Enable 334 #define LCD_RASTRSUBP1_HOLS 0x20000000 // High or Low Signal 335 #define LCD_RASTRSUBP1_LPPT_M 0x03FF0000 // Line Per Panel Threshold 336 #define LCD_RASTRSUBP1_DPDLSB_M 0x0000FFFF // Default Pixel Data LSB[15:0] 337 #define LCD_RASTRSUBP1_LPPT_S 16 338 #define LCD_RASTRSUBP1_DPDLSB_S 0 339 340 //***************************************************************************** 341 // 342 // The following are defines for the bit fields in the LCD_O_RASTRSUBP2 343 // register. 344 // 345 //***************************************************************************** 346 #define LCD_RASTRSUBP2_LPPTMSB 0x00000100 // Lines Per Panel Threshold Bit 10 347 #define LCD_RASTRSUBP2_DPDMSB_M 0x000000FF // Default Pixel Data MSB [23:16] 348 #define LCD_RASTRSUBP2_DPDMSB_S 0 349 350 //***************************************************************************** 351 // 352 // The following are defines for the bit fields in the LCD_O_DMACTL register. 353 // 354 //***************************************************************************** 355 #define LCD_DMACTL_FIFORDY_M 0x00000700 // DMA FIFO threshold 356 #define LCD_DMACTL_FIFORDY_8 0x00000000 // 8 words 357 #define LCD_DMACTL_FIFORDY_16 0x00000100 // 16 words 358 #define LCD_DMACTL_FIFORDY_32 0x00000200 // 32 words 359 #define LCD_DMACTL_FIFORDY_64 0x00000300 // 64 words 360 #define LCD_DMACTL_FIFORDY_128 0x00000400 // 128 words 361 #define LCD_DMACTL_FIFORDY_256 0x00000500 // 256 words 362 #define LCD_DMACTL_FIFORDY_512 0x00000600 // 512 words 363 #define LCD_DMACTL_BURSTSZ_M 0x00000070 // Burst Size setting for DMA 364 // transfers (all DMA transfers are 365 // 32 bits wide): 366 #define LCD_DMACTL_BURSTSZ_4 0x00000020 // burst size of 4 367 #define LCD_DMACTL_BURSTSZ_8 0x00000030 // burst size of 8 368 #define LCD_DMACTL_BURSTSZ_16 0x00000040 // burst size of 16 369 #define LCD_DMACTL_BYTESWAP 0x00000008 // This bit controls the bytelane 370 // ordering of the data on the 371 // output of the DMA module 372 #define LCD_DMACTL_BIGDEND 0x00000002 // Big Endian Enable 373 #define LCD_DMACTL_FMODE 0x00000001 // Frame Mode 374 375 //***************************************************************************** 376 // 377 // The following are defines for the bit fields in the LCD_O_DMABAFB0 register. 378 // 379 //***************************************************************************** 380 #define LCD_DMABAFB0_FB0BA_M 0xFFFFFFFC // Frame Buffer 0 Base Address 381 // pointer 382 #define LCD_DMABAFB0_FB0BA_S 2 383 384 //***************************************************************************** 385 // 386 // The following are defines for the bit fields in the LCD_O_DMACAFB0 register. 387 // 388 //***************************************************************************** 389 #define LCD_DMACAFB0_FB0CA_M 0xFFFFFFFC // Frame Buffer 0 Ceiling Address 390 // pointer 391 #define LCD_DMACAFB0_FB0CA_S 2 392 393 //***************************************************************************** 394 // 395 // The following are defines for the bit fields in the LCD_O_DMABAFB1 register. 396 // 397 //***************************************************************************** 398 #define LCD_DMABAFB1_FB1BA_M 0xFFFFFFFC // Frame Buffer 1 Base Address 399 // pointer 400 #define LCD_DMABAFB1_FB1BA_S 2 401 402 //***************************************************************************** 403 // 404 // The following are defines for the bit fields in the LCD_O_DMACAFB1 register. 405 // 406 //***************************************************************************** 407 #define LCD_DMACAFB1_FB1CA_M 0xFFFFFFFC // Frame Buffer 1 Ceiling Address 408 // pointer 409 #define LCD_DMACAFB1_FB1CA_S 2 410 411 //***************************************************************************** 412 // 413 // The following are defines for the bit fields in the LCD_O_SYSCFG register. 414 // 415 //***************************************************************************** 416 #define LCD_SYSCFG_STDBY_M 0x00000030 // Standby Mode 417 #define LCD_SYSCFG_STDBY_FORCE 0x00000000 // Force-standby mode: local 418 // initiator is unconditionally 419 // placed in standby state. Backup 420 // mode, for debug only 421 #define LCD_SYSCFG_STDBY_NONE 0x00000010 // No-standby mode: local initiator 422 // is unconditionally placed out of 423 // standby state. Backup mode, for 424 // debug only 425 #define LCD_SYSCFG_STDBY_SMART 0x00000020 // Smart-standby mode: local 426 // initiator standby status depends 427 // on local conditions, that is, 428 // the module's functional 429 // requirement from the initiator. 430 // IP module shall not generate 431 // (initiator-related) wakeup 432 // events 433 #define LCD_SYSCFG_IDLEMODE_M 0x0000000C // Idle Mode 434 #define LCD_SYSCFG_IDLEMODE_FORCE \ 435 0x00000000 // Force-idle mode: local target's 436 // idle state follows 437 // (acknowledges) the system's idle 438 // requests unconditionally, that 439 // is, regardless of the IP 440 // module's internal requirements. 441 // Backup mode, for debug only 442 #define LCD_SYSCFG_IDLEMODE_NONE \ 443 0x00000004 // No-idle mode: local target never 444 // enters idle state. Backup mode, 445 // for debug only 446 #define LCD_SYSCFG_IDLEMODE_SMART \ 447 0x00000008 // Smart-idle mode: local target's 448 // idle state eventually follows 449 // (acknowledges) the system's idle 450 // requests, depending on the IP 451 // module's internal requirements. 452 // IP module shall not generate 453 // (IRQ- or DMA-requestrelated) 454 // wakeup events 455 456 //***************************************************************************** 457 // 458 // The following are defines for the bit fields in the LCD_O_RISSET register. 459 // 460 //***************************************************************************** 461 #define LCD_RISSET_EOF1 0x00000200 // DMA End-of-Frame 1 Raw Interrupt 462 // Status and Set 463 #define LCD_RISSET_EOF0 0x00000100 // DMA End-of-Frame 0 Raw Interrupt 464 // Status and Set 465 #define LCD_RISSET_PALLOAD 0x00000040 // DMA Palette Loaded Raw Interrupt 466 // Status and Set 467 #define LCD_RISSET_FIFOU 0x00000020 // DMA FIFO Underflow Raw Interrupt 468 // Status and Set 469 #define LCD_RISSET_ACBS 0x00000008 // AC Bias Count Raw Interrupt 470 // Status and Set 471 #define LCD_RISSET_SYNCS 0x00000004 // Frame Synchronization Lost Raw 472 // Interrupt Status and Set 473 #define LCD_RISSET_RRASTRDONE 0x00000002 // Raster Mode Frame Done interrupt 474 #define LCD_RISSET_DONE 0x00000001 // Raster or LIDD Frame Done 475 // (shared, depends on whether 476 // Raster or LIDD mode enabled) Raw 477 // Interrupt Status and Set 478 479 //***************************************************************************** 480 // 481 // The following are defines for the bit fields in the LCD_O_MISCLR register. 482 // 483 //***************************************************************************** 484 #define LCD_MISCLR_EOF1 0x00000200 // DMA End-of-Frame 1 Enabled 485 // Interrupt and Clear 486 #define LCD_MISCLR_EOF0 0x00000100 // DMA End-of-Frame 0 Raw Interrupt 487 // and Clear 488 #define LCD_MISCLR_PALLOAD 0x00000040 // DMA Palette Loaded Enabled 489 // Interrupt and Clear 490 #define LCD_MISCLR_FIFOU 0x00000020 // DMA FIFO Underflow Enabled 491 // Interrupt and Clear 492 #define LCD_MISCLR_ACBS 0x00000008 // AC Bias Count Enabled Interrupt 493 // and Clear 494 #define LCD_MISCLR_SYNCS 0x00000004 // Frame Synchronization Lost 495 // Enabled Interrupt and Clear 496 #define LCD_MISCLR_RRASTRDONE 0x00000002 // Raster Mode Frame Done interrupt 497 #define LCD_MISCLR_DONE 0x00000001 // Raster or LIDD Frame Done 498 // (shared, depends on whether 499 // Raster or LIDD mode enabled) 500 // Enabled Interrupt and Clear 501 502 //***************************************************************************** 503 // 504 // The following are defines for the bit fields in the LCD_O_IM register. 505 // 506 //***************************************************************************** 507 #define LCD_IM_EOF1 0x00000200 // DMA End-of-Frame 1 Interrupt 508 // Enable Set 509 #define LCD_IM_EOF0 0x00000100 // DMA End-of-Frame 0 Interrupt 510 // Enable Set 511 #define LCD_IM_PALLOAD 0x00000040 // DMA Palette Loaded Interrupt 512 // Enable Set 513 #define LCD_IM_FIFOU 0x00000020 // DMA FIFO Underflow Interrupt 514 // Enable Set 515 #define LCD_IM_ACBS 0x00000008 // AC Bias Count Interrupt Enable 516 // Set 517 #define LCD_IM_SYNCS 0x00000004 // Frame Synchronization Lost 518 // Interrupt Enable Set 519 #define LCD_IM_RRASTRDONE 0x00000002 // Raster Mode Frame Done Interrupt 520 // Enable Set 521 #define LCD_IM_DONE 0x00000001 // Raster or LIDD Frame Done 522 // (shared, depends on whether 523 // Raster or LIDD mode enabled) 524 // Interrupt Enable Set 525 526 //***************************************************************************** 527 // 528 // The following are defines for the bit fields in the LCD_O_IENC register. 529 // 530 //***************************************************************************** 531 #define LCD_IENC_EOF1 0x00000200 // DMA End-of-Frame 1 Interrupt 532 // Enable Clear 533 #define LCD_IENC_EOF0 0x00000100 // DMA End-of-Frame 0 Interrupt 534 // Enable Clear 535 #define LCD_IENC_PALLOAD 0x00000040 // DMA Palette Loaded Interrupt 536 // Enable Clear 537 #define LCD_IENC_FIFOU 0x00000020 // DMA FIFO Underflow Interrupt 538 // Enable Clear 539 #define LCD_IENC_ACBS 0x00000008 // AC Bias Count Interrupt Enable 540 // Clear 541 #define LCD_IENC_SYNCS 0x00000004 // Frame Synchronization Lost 542 // Interrupt Enable Clear 543 #define LCD_IENC_RRASTRDONE 0x00000002 // Raster Mode Frame Done Interrupt 544 // Enable Clear 545 #define LCD_IENC_DONE 0x00000001 // Raster or LIDD Frame Done 546 // (shared, depends on whether 547 // Raster or LIDD mode enabled) 548 // Interrupt Enable Clear 549 550 //***************************************************************************** 551 // 552 // The following are defines for the bit fields in the LCD_O_CLKEN register. 553 // 554 //***************************************************************************** 555 #define LCD_CLKEN_DMA 0x00000004 // DMA Clock Enable 556 #define LCD_CLKEN_LIDD 0x00000002 // LIDD Submodule Clock Enable 557 #define LCD_CLKEN_CORE 0x00000001 // LCD Core Clock Enable 558 559 //***************************************************************************** 560 // 561 // The following are defines for the bit fields in the LCD_O_CLKRESET register. 562 // 563 //***************************************************************************** 564 #define LCD_CLKRESET_MAIN 0x00000008 // Software Reset for the entire 565 // LCD module 566 #define LCD_CLKRESET_DMA 0x00000004 // Software Reset for the DMA 567 // submodule 568 #define LCD_CLKRESET_LIDD 0x00000002 // Software Reset for the LIDD 569 // submodule (character displays) 570 #define LCD_CLKRESET_CORE 0x00000001 // Software Reset for the Core, 571 // which encompasses the Raster 572 // Active Matrix and Passive Matrix 573 // logic 574 575 #endif // __HW_LCD_H__ 576