1 //***************************************************************************** 2 // 3 // hw_onewire.h - Macros used when accessing the One wire hardware. 4 // 5 // Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved. 6 // Software License Agreement 7 // 8 // Redistribution and use in source and binary forms, with or without 9 // modification, are permitted provided that the following conditions 10 // are met: 11 // 12 // Redistributions of source code must retain the above copyright 13 // notice, this list of conditions and the following disclaimer. 14 // 15 // Redistributions in binary form must reproduce the above copyright 16 // notice, this list of conditions and the following disclaimer in the 17 // documentation and/or other materials provided with the 18 // distribution. 19 // 20 // Neither the name of Texas Instruments Incorporated nor the names of 21 // its contributors may be used to endorse or promote products derived 22 // from this software without specific prior written permission. 23 // 24 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 27 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 28 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 29 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 30 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 34 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 // 36 // This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. 37 // 38 //***************************************************************************** 39 40 #ifndef __HW_ONEWIRE_H__ 41 #define __HW_ONEWIRE_H__ 42 43 //***************************************************************************** 44 // 45 // The following are defines for the One wire register offsets. 46 // 47 //***************************************************************************** 48 #define ONEWIRE_O_CS 0x00000000 // 1-Wire Control and Status 49 #define ONEWIRE_O_TIM 0x00000004 // 1-Wire Timing Override 50 #define ONEWIRE_O_DATW 0x00000008 // 1-Wire Data Write 51 #define ONEWIRE_O_DATR 0x0000000C // 1-Wire Data Read 52 #define ONEWIRE_O_IM 0x00000100 // 1-Wire Interrupt Mask 53 #define ONEWIRE_O_RIS 0x00000104 // 1-Wire Raw Interrupt Status 54 #define ONEWIRE_O_MIS 0x00000108 // 1-Wire Masked Interrupt Status 55 #define ONEWIRE_O_ICR 0x0000010C // 1-Wire Interrupt Clear 56 #define ONEWIRE_O_DMA 0x00000120 // 1-Wire uDMA Control 57 #define ONEWIRE_O_PP 0x00000FC0 // 1-Wire Peripheral Properties 58 59 //***************************************************************************** 60 // 61 // The following are defines for the bit fields in the ONEWIRE_O_CS register. 62 // 63 //***************************************************************************** 64 #define ONEWIRE_CS_USEALT 0x80000000 // Two Wire Enable 65 #define ONEWIRE_CS_ALTP 0x40000000 // Alternate Polarity Enable 66 #define ONEWIRE_CS_BSIZE_M 0x00070000 // Last Byte Size 67 #define ONEWIRE_CS_BSIZE_8 0x00000000 // 8 bits (1 byte) 68 #define ONEWIRE_CS_BSIZE_1 0x00010000 // 1 bit 69 #define ONEWIRE_CS_BSIZE_2 0x00020000 // 2 bits 70 #define ONEWIRE_CS_BSIZE_3 0x00030000 // 3 bits 71 #define ONEWIRE_CS_BSIZE_4 0x00040000 // 4 bits 72 #define ONEWIRE_CS_BSIZE_5 0x00050000 // 5 bits 73 #define ONEWIRE_CS_BSIZE_6 0x00060000 // 6 bits 74 #define ONEWIRE_CS_BSIZE_7 0x00070000 // 7 bits 75 #define ONEWIRE_CS_STUCK 0x00000400 // STUCK Status 76 #define ONEWIRE_CS_NOATR 0x00000200 // Answer-to-Reset Status 77 #define ONEWIRE_CS_BUSY 0x00000100 // Busy Status 78 #define ONEWIRE_CS_SKATR 0x00000080 // Skip Answer-to-Reset Enable 79 #define ONEWIRE_CS_LSAM 0x00000040 // Late Sample Enable 80 #define ONEWIRE_CS_ODRV 0x00000020 // Overdrive Enable 81 #define ONEWIRE_CS_SZ_M 0x00000018 // Data Operation Size 82 #define ONEWIRE_CS_OP_M 0x00000006 // Operation Request 83 #define ONEWIRE_CS_OP_NONE 0x00000000 // No operation 84 #define ONEWIRE_CS_OP_RD 0x00000002 // Read 85 #define ONEWIRE_CS_OP_WR 0x00000004 // Write 86 #define ONEWIRE_CS_OP_WRRD 0x00000006 // Write/Read 87 #define ONEWIRE_CS_RST 0x00000001 // Reset Request 88 #define ONEWIRE_CS_SZ_S 3 89 90 //***************************************************************************** 91 // 92 // The following are defines for the bit fields in the ONEWIRE_O_TIM register. 93 // 94 //***************************************************************************** 95 #define ONEWIRE_TIM_W1TIM_M 0xF0000000 // Value '1' Timing 96 #define ONEWIRE_TIM_W0TIM_M 0x0F800000 // Value '0' Timing 97 #define ONEWIRE_TIM_W0REST_M 0x00780000 // Rest Time 98 #define ONEWIRE_TIM_W1SAM_M 0x00078000 // Sample Time 99 #define ONEWIRE_TIM_ATRSAM_M 0x00007800 // Answer-to-Reset Sample 100 #define ONEWIRE_TIM_ATRTIM_M 0x000007C0 // Answer-to-Reset/Rest Period 101 #define ONEWIRE_TIM_RSTTIM_M 0x0000003F // Reset Low Time 102 #define ONEWIRE_TIM_W1TIM_S 28 103 #define ONEWIRE_TIM_W0TIM_S 23 104 #define ONEWIRE_TIM_W0REST_S 19 105 #define ONEWIRE_TIM_W1SAM_S 15 106 #define ONEWIRE_TIM_ATRSAM_S 11 107 #define ONEWIRE_TIM_ATRTIM_S 6 108 #define ONEWIRE_TIM_RSTTIM_S 0 109 110 //***************************************************************************** 111 // 112 // The following are defines for the bit fields in the ONEWIRE_O_DATW register. 113 // 114 //***************************************************************************** 115 #define ONEWIRE_DATW_B3_M 0xFF000000 // Upper Data Byte 116 #define ONEWIRE_DATW_B2_M 0x00FF0000 // Upper Middle Data Byte 117 #define ONEWIRE_DATW_B1_M 0x0000FF00 // Lower Middle Data Byte 118 #define ONEWIRE_DATW_B0_M 0x000000FF // Lowest Data Byte 119 #define ONEWIRE_DATW_B3_S 24 120 #define ONEWIRE_DATW_B2_S 16 121 #define ONEWIRE_DATW_B1_S 8 122 #define ONEWIRE_DATW_B0_S 0 123 124 //***************************************************************************** 125 // 126 // The following are defines for the bit fields in the ONEWIRE_O_DATR register. 127 // 128 //***************************************************************************** 129 #define ONEWIRE_DATR_B3_M 0xFF000000 // Upper Data Byte 130 #define ONEWIRE_DATR_B2_M 0x00FF0000 // Upper Middle Data Byte 131 #define ONEWIRE_DATR_B1_M 0x0000FF00 // Lower Middle Data Byte 132 #define ONEWIRE_DATR_B0_M 0x000000FF // Lowest Data Byte 133 #define ONEWIRE_DATR_B3_S 24 134 #define ONEWIRE_DATR_B2_S 16 135 #define ONEWIRE_DATR_B1_S 8 136 #define ONEWIRE_DATR_B0_S 0 137 138 //***************************************************************************** 139 // 140 // The following are defines for the bit fields in the ONEWIRE_O_IM register. 141 // 142 //***************************************************************************** 143 #define ONEWIRE_IM_DMA 0x00000010 // DMA Done Interrupt Mask 144 #define ONEWIRE_IM_STUCK 0x00000008 // Stuck Status Interrupt Mask 145 #define ONEWIRE_IM_NOATR 0x00000004 // No Answer-to-Reset Interrupt 146 // Mask 147 #define ONEWIRE_IM_OPC 0x00000002 // Operation Complete Interrupt 148 // Mask 149 #define ONEWIRE_IM_RST 0x00000001 // Reset Interrupt Mask 150 151 //***************************************************************************** 152 // 153 // The following are defines for the bit fields in the ONEWIRE_O_RIS register. 154 // 155 //***************************************************************************** 156 #define ONEWIRE_RIS_DMA 0x00000010 // DMA Done Raw Interrupt Status 157 #define ONEWIRE_RIS_STUCK 0x00000008 // Stuck Status Raw Interrupt 158 // Status 159 #define ONEWIRE_RIS_NOATR 0x00000004 // No Answer-to-Reset Raw Interrupt 160 // Status 161 #define ONEWIRE_RIS_OPC 0x00000002 // Operation Complete Raw Interrupt 162 // Status 163 #define ONEWIRE_RIS_RST 0x00000001 // Reset Raw Interrupt Status 164 165 //***************************************************************************** 166 // 167 // The following are defines for the bit fields in the ONEWIRE_O_MIS register. 168 // 169 //***************************************************************************** 170 #define ONEWIRE_MIS_DMA 0x00000010 // DMA Done Masked Interrupt Status 171 #define ONEWIRE_MIS_STUCK 0x00000008 // Stuck Status Masked Interrupt 172 // Status 173 #define ONEWIRE_MIS_NOATR 0x00000004 // No Answer-to-Reset Masked 174 // Interrupt Status 175 #define ONEWIRE_MIS_OPC 0x00000002 // Operation Complete Masked 176 // Interrupt Status 177 #define ONEWIRE_MIS_RST 0x00000001 // Reset Interrupt Mask 178 179 //***************************************************************************** 180 // 181 // The following are defines for the bit fields in the ONEWIRE_O_ICR register. 182 // 183 //***************************************************************************** 184 #define ONEWIRE_ICR_DMA 0x00000010 // DMA Done Interrupt Clear 185 #define ONEWIRE_ICR_STUCK 0x00000008 // Stuck Status Interrupt Clear 186 #define ONEWIRE_ICR_NOATR 0x00000004 // No Answer-to-Reset Interrupt 187 // Clear 188 #define ONEWIRE_ICR_OPC 0x00000002 // Operation Complete Interrupt 189 // Clear 190 #define ONEWIRE_ICR_RST 0x00000001 // Reset Interrupt Clear 191 192 //***************************************************************************** 193 // 194 // The following are defines for the bit fields in the ONEWIRE_O_DMA register. 195 // 196 //***************************************************************************** 197 #define ONEWIRE_DMA_SG 0x00000008 // Scatter-Gather Enable 198 #define ONEWIRE_DMA_DMAOP_M 0x00000006 // uDMA Operation 199 #define ONEWIRE_DMA_DMAOP_DIS 0x00000000 // uDMA disabled 200 #define ONEWIRE_DMA_DMAOP_RDSNG 0x00000002 // uDMA single read: 1-Wire 201 // requests uDMA to read 202 // ONEWIREDATR register after each 203 // read transaction 204 #define ONEWIRE_DMA_DMAOP_WRMUL 0x00000004 // uDMA multiple write: 1-Wire 205 // requests uDMA to load whenever 206 // the ONEWIREDATW register is 207 // empty 208 #define ONEWIRE_DMA_DMAOP_RDMUL 0x00000006 // uDMA multiple read: An initial 209 // read occurs and subsequent reads 210 // start after uDMA has read the 211 // ONEWIREDATR register 212 #define ONEWIRE_DMA_RST 0x00000001 // uDMA Reset 213 214 //***************************************************************************** 215 // 216 // The following are defines for the bit fields in the ONEWIRE_O_PP register. 217 // 218 //***************************************************************************** 219 #define ONEWIRE_PP_DMAP 0x00000010 // uDMA Present 220 #define ONEWIRE_PP_CNT_M 0x00000003 // 1-Wire Bus Count 221 #define ONEWIRE_PP_CNT_S 0 222 223 #endif // __HW_ONEWIRE_H__ 224