1 //***************************************************************************** 2 // 3 // hw_shamd5.h - Macros used when accessing the SHA/MD5 hardware. 4 // 5 // Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved. 6 // Software License Agreement 7 // 8 // Redistribution and use in source and binary forms, with or without 9 // modification, are permitted provided that the following conditions 10 // are met: 11 // 12 // Redistributions of source code must retain the above copyright 13 // notice, this list of conditions and the following disclaimer. 14 // 15 // Redistributions in binary form must reproduce the above copyright 16 // notice, this list of conditions and the following disclaimer in the 17 // documentation and/or other materials provided with the 18 // distribution. 19 // 20 // Neither the name of Texas Instruments Incorporated nor the names of 21 // its contributors may be used to endorse or promote products derived 22 // from this software without specific prior written permission. 23 // 24 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 27 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 28 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 29 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 30 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 34 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 // 36 // This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. 37 // 38 //***************************************************************************** 39 40 #ifndef __HW_SHAMD5_H__ 41 #define __HW_SHAMD5_H__ 42 43 //***************************************************************************** 44 // 45 // The following are defines for the SHA/MD5 register offsets. 46 // 47 //***************************************************************************** 48 #define SHAMD5_O_ODIGEST_A 0x00000000 // SHA Outer Digest A 49 #define SHAMD5_O_ODIGEST_B 0x00000004 // SHA Outer Digest B 50 #define SHAMD5_O_ODIGEST_C 0x00000008 // SHA Outer Digest C 51 #define SHAMD5_O_ODIGEST_D 0x0000000C // SHA Outer Digest D 52 #define SHAMD5_O_ODIGEST_E 0x00000010 // SHA Outer Digest E 53 #define SHAMD5_O_ODIGEST_F 0x00000014 // SHA Outer Digest F 54 #define SHAMD5_O_ODIGEST_G 0x00000018 // SHA Outer Digest G 55 #define SHAMD5_O_ODIGEST_H 0x0000001C // SHA Outer Digest H 56 #define SHAMD5_O_IDIGEST_A 0x00000020 // SHA Inner Digest A 57 #define SHAMD5_O_IDIGEST_B 0x00000024 // SHA Inner Digest B 58 #define SHAMD5_O_IDIGEST_C 0x00000028 // SHA Inner Digest C 59 #define SHAMD5_O_IDIGEST_D 0x0000002C // SHA Inner Digest D 60 #define SHAMD5_O_IDIGEST_E 0x00000030 // SHA Inner Digest E 61 #define SHAMD5_O_IDIGEST_F 0x00000034 // SHA Inner Digest F 62 #define SHAMD5_O_IDIGEST_G 0x00000038 // SHA Inner Digest G 63 #define SHAMD5_O_IDIGEST_H 0x0000003C // SHA Inner Digest H 64 #define SHAMD5_O_DIGEST_COUNT 0x00000040 // SHA Digest Count 65 #define SHAMD5_O_MODE 0x00000044 // SHA Mode 66 #define SHAMD5_O_LENGTH 0x00000048 // SHA Length 67 #define SHAMD5_O_DATA_0_IN 0x00000080 // SHA Data 0 Input 68 #define SHAMD5_O_DATA_1_IN 0x00000084 // SHA Data 1 Input 69 #define SHAMD5_O_DATA_2_IN 0x00000088 // SHA Data 2 Input 70 #define SHAMD5_O_DATA_3_IN 0x0000008C // SHA Data 3 Input 71 #define SHAMD5_O_DATA_4_IN 0x00000090 // SHA Data 4 Input 72 #define SHAMD5_O_DATA_5_IN 0x00000094 // SHA Data 5 Input 73 #define SHAMD5_O_DATA_6_IN 0x00000098 // SHA Data 6 Input 74 #define SHAMD5_O_DATA_7_IN 0x0000009C // SHA Data 7 Input 75 #define SHAMD5_O_DATA_8_IN 0x000000A0 // SHA Data 8 Input 76 #define SHAMD5_O_DATA_9_IN 0x000000A4 // SHA Data 9 Input 77 #define SHAMD5_O_DATA_10_IN 0x000000A8 // SHA Data 10 Input 78 #define SHAMD5_O_DATA_11_IN 0x000000AC // SHA Data 11 Input 79 #define SHAMD5_O_DATA_12_IN 0x000000B0 // SHA Data 12 Input 80 #define SHAMD5_O_DATA_13_IN 0x000000B4 // SHA Data 13 Input 81 #define SHAMD5_O_DATA_14_IN 0x000000B8 // SHA Data 14 Input 82 #define SHAMD5_O_DATA_15_IN 0x000000BC // SHA Data 15 Input 83 #define SHAMD5_O_REVISION 0x00000100 // SHA Revision 84 #define SHAMD5_O_SYSCONFIG 0x00000110 // SHA System Configuration 85 #define SHAMD5_O_SYSSTATUS 0x00000114 // SHA System Status 86 #define SHAMD5_O_IRQSTATUS 0x00000118 // SHA Interrupt Status 87 #define SHAMD5_O_IRQENABLE 0x0000011C // SHA Interrupt Enable 88 #define SHAMD5_O_DMAIM 0xFFFFC010 // SHA DMA Interrupt Mask 89 #define SHAMD5_O_DMARIS 0xFFFFC014 // SHA DMA Raw Interrupt Status 90 #define SHAMD5_O_DMAMIS 0xFFFFC018 // SHA DMA Masked Interrupt Status 91 #define SHAMD5_O_DMAIC 0xFFFFC01C // SHA DMA Interrupt Clear 92 93 //***************************************************************************** 94 // 95 // The following are defines for the bit fields in the SHAMD5_O_ODIGEST_A 96 // register. 97 // 98 //***************************************************************************** 99 #define SHAMD5_ODIGEST_A_DATA_M 0xFFFFFFFF // Digest/Key Data 100 #define SHAMD5_ODIGEST_A_DATA_S 0 101 102 //***************************************************************************** 103 // 104 // The following are defines for the bit fields in the SHAMD5_O_ODIGEST_B 105 // register. 106 // 107 //***************************************************************************** 108 #define SHAMD5_ODIGEST_B_DATA_M 0xFFFFFFFF // Digest/Key Data 109 #define SHAMD5_ODIGEST_B_DATA_S 0 110 111 //***************************************************************************** 112 // 113 // The following are defines for the bit fields in the SHAMD5_O_ODIGEST_C 114 // register. 115 // 116 //***************************************************************************** 117 #define SHAMD5_ODIGEST_C_DATA_M 0xFFFFFFFF // Digest/Key Data 118 #define SHAMD5_ODIGEST_C_DATA_S 0 119 120 //***************************************************************************** 121 // 122 // The following are defines for the bit fields in the SHAMD5_O_ODIGEST_D 123 // register. 124 // 125 //***************************************************************************** 126 #define SHAMD5_ODIGEST_D_DATA_M 0xFFFFFFFF // Digest/Key Data 127 #define SHAMD5_ODIGEST_D_DATA_S 0 128 129 //***************************************************************************** 130 // 131 // The following are defines for the bit fields in the SHAMD5_O_ODIGEST_E 132 // register. 133 // 134 //***************************************************************************** 135 #define SHAMD5_ODIGEST_E_DATA_M 0xFFFFFFFF // Digest/Key Data 136 #define SHAMD5_ODIGEST_E_DATA_S 0 137 138 //***************************************************************************** 139 // 140 // The following are defines for the bit fields in the SHAMD5_O_ODIGEST_F 141 // register. 142 // 143 //***************************************************************************** 144 #define SHAMD5_ODIGEST_F_DATA_M 0xFFFFFFFF // Digest/Key Data 145 #define SHAMD5_ODIGEST_F_DATA_S 0 146 147 //***************************************************************************** 148 // 149 // The following are defines for the bit fields in the SHAMD5_O_ODIGEST_G 150 // register. 151 // 152 //***************************************************************************** 153 #define SHAMD5_ODIGEST_G_DATA_M 0xFFFFFFFF // Digest/Key Data 154 #define SHAMD5_ODIGEST_G_DATA_S 0 155 156 //***************************************************************************** 157 // 158 // The following are defines for the bit fields in the SHAMD5_O_ODIGEST_H 159 // register. 160 // 161 //***************************************************************************** 162 #define SHAMD5_ODIGEST_H_DATA_M 0xFFFFFFFF // Digest/Key Data 163 #define SHAMD5_ODIGEST_H_DATA_S 0 164 165 //***************************************************************************** 166 // 167 // The following are defines for the bit fields in the SHAMD5_O_IDIGEST_A 168 // register. 169 // 170 //***************************************************************************** 171 #define SHAMD5_IDIGEST_A_DATA_M 0xFFFFFFFF // Digest/Key Data 172 #define SHAMD5_IDIGEST_A_DATA_S 0 173 174 //***************************************************************************** 175 // 176 // The following are defines for the bit fields in the SHAMD5_O_IDIGEST_B 177 // register. 178 // 179 //***************************************************************************** 180 #define SHAMD5_IDIGEST_B_DATA_M 0xFFFFFFFF // Digest/Key Data 181 #define SHAMD5_IDIGEST_B_DATA_S 0 182 183 //***************************************************************************** 184 // 185 // The following are defines for the bit fields in the SHAMD5_O_IDIGEST_C 186 // register. 187 // 188 //***************************************************************************** 189 #define SHAMD5_IDIGEST_C_DATA_M 0xFFFFFFFF // Digest/Key Data 190 #define SHAMD5_IDIGEST_C_DATA_S 0 191 192 //***************************************************************************** 193 // 194 // The following are defines for the bit fields in the SHAMD5_O_IDIGEST_D 195 // register. 196 // 197 //***************************************************************************** 198 #define SHAMD5_IDIGEST_D_DATA_M 0xFFFFFFFF // Digest/Key Data 199 #define SHAMD5_IDIGEST_D_DATA_S 0 200 201 //***************************************************************************** 202 // 203 // The following are defines for the bit fields in the SHAMD5_O_IDIGEST_E 204 // register. 205 // 206 //***************************************************************************** 207 #define SHAMD5_IDIGEST_E_DATA_M 0xFFFFFFFF // Digest/Key Data 208 #define SHAMD5_IDIGEST_E_DATA_S 0 209 210 //***************************************************************************** 211 // 212 // The following are defines for the bit fields in the SHAMD5_O_IDIGEST_F 213 // register. 214 // 215 //***************************************************************************** 216 #define SHAMD5_IDIGEST_F_DATA_M 0xFFFFFFFF // Digest/Key Data 217 #define SHAMD5_IDIGEST_F_DATA_S 0 218 219 //***************************************************************************** 220 // 221 // The following are defines for the bit fields in the SHAMD5_O_IDIGEST_G 222 // register. 223 // 224 //***************************************************************************** 225 #define SHAMD5_IDIGEST_G_DATA_M 0xFFFFFFFF // Digest/Key Data 226 #define SHAMD5_IDIGEST_G_DATA_S 0 227 228 //***************************************************************************** 229 // 230 // The following are defines for the bit fields in the SHAMD5_O_IDIGEST_H 231 // register. 232 // 233 //***************************************************************************** 234 #define SHAMD5_IDIGEST_H_DATA_M 0xFFFFFFFF // Digest/Key Data 235 #define SHAMD5_IDIGEST_H_DATA_S 0 236 237 //***************************************************************************** 238 // 239 // The following are defines for the bit fields in the SHAMD5_O_DIGEST_COUNT 240 // register. 241 // 242 //***************************************************************************** 243 #define SHAMD5_DIGEST_COUNT_M 0xFFFFFFFF // Digest Count 244 #define SHAMD5_DIGEST_COUNT_S 0 245 246 //***************************************************************************** 247 // 248 // The following are defines for the bit fields in the SHAMD5_O_MODE register. 249 // 250 //***************************************************************************** 251 #define SHAMD5_MODE_HMAC_OUTER_HASH \ 252 0x00000080 // HMAC Outer Hash Processing 253 // Enable 254 #define SHAMD5_MODE_HMAC_KEY_PROC \ 255 0x00000020 // HMAC Key Processing Enable 256 #define SHAMD5_MODE_CLOSE_HASH 0x00000010 // Performs the padding, the 257 // Hash/HMAC will be 'closed' at 258 // the end of the block, as per 259 // MD5/SHA-1/SHA-2 specification 260 #define SHAMD5_MODE_ALGO_CONSTANT \ 261 0x00000008 // The initial digest register will 262 // be overwritten with the 263 // algorithm constants for the 264 // selected algorithm when hashing 265 // and the initial digest count 266 // register will be reset to 0 267 #define SHAMD5_MODE_ALGO_M 0x00000007 // Hash Algorithm 268 #define SHAMD5_MODE_ALGO_MD5 0x00000000 // MD5 269 #define SHAMD5_MODE_ALGO_SHA1 0x00000002 // SHA-1 270 #define SHAMD5_MODE_ALGO_SHA224 0x00000004 // SHA-224 271 #define SHAMD5_MODE_ALGO_SHA256 0x00000006 // SHA-256 272 273 //***************************************************************************** 274 // 275 // The following are defines for the bit fields in the SHAMD5_O_LENGTH 276 // register. 277 // 278 //***************************************************************************** 279 #define SHAMD5_LENGTH_M 0xFFFFFFFF // Block Length/Remaining Byte 280 // Count 281 #define SHAMD5_LENGTH_S 0 282 283 //***************************************************************************** 284 // 285 // The following are defines for the bit fields in the SHAMD5_O_DATA_0_IN 286 // register. 287 // 288 //***************************************************************************** 289 #define SHAMD5_DATA_0_IN_DATA_M 0xFFFFFFFF // Digest/Key Data 290 #define SHAMD5_DATA_0_IN_DATA_S 0 291 292 //***************************************************************************** 293 // 294 // The following are defines for the bit fields in the SHAMD5_O_DATA_1_IN 295 // register. 296 // 297 //***************************************************************************** 298 #define SHAMD5_DATA_1_IN_DATA_M 0xFFFFFFFF // Digest/Key Data 299 #define SHAMD5_DATA_1_IN_DATA_S 0 300 301 //***************************************************************************** 302 // 303 // The following are defines for the bit fields in the SHAMD5_O_DATA_2_IN 304 // register. 305 // 306 //***************************************************************************** 307 #define SHAMD5_DATA_2_IN_DATA_M 0xFFFFFFFF // Digest/Key Data 308 #define SHAMD5_DATA_2_IN_DATA_S 0 309 310 //***************************************************************************** 311 // 312 // The following are defines for the bit fields in the SHAMD5_O_DATA_3_IN 313 // register. 314 // 315 //***************************************************************************** 316 #define SHAMD5_DATA_3_IN_DATA_M 0xFFFFFFFF // Digest/Key Data 317 #define SHAMD5_DATA_3_IN_DATA_S 0 318 319 //***************************************************************************** 320 // 321 // The following are defines for the bit fields in the SHAMD5_O_DATA_4_IN 322 // register. 323 // 324 //***************************************************************************** 325 #define SHAMD5_DATA_4_IN_DATA_M 0xFFFFFFFF // Digest/Key Data 326 #define SHAMD5_DATA_4_IN_DATA_S 0 327 328 //***************************************************************************** 329 // 330 // The following are defines for the bit fields in the SHAMD5_O_DATA_5_IN 331 // register. 332 // 333 //***************************************************************************** 334 #define SHAMD5_DATA_5_IN_DATA_M 0xFFFFFFFF // Digest/Key Data 335 #define SHAMD5_DATA_5_IN_DATA_S 0 336 337 //***************************************************************************** 338 // 339 // The following are defines for the bit fields in the SHAMD5_O_DATA_6_IN 340 // register. 341 // 342 //***************************************************************************** 343 #define SHAMD5_DATA_6_IN_DATA_M 0xFFFFFFFF // Digest/Key Data 344 #define SHAMD5_DATA_6_IN_DATA_S 0 345 346 //***************************************************************************** 347 // 348 // The following are defines for the bit fields in the SHAMD5_O_DATA_7_IN 349 // register. 350 // 351 //***************************************************************************** 352 #define SHAMD5_DATA_7_IN_DATA_M 0xFFFFFFFF // Digest/Key Data 353 #define SHAMD5_DATA_7_IN_DATA_S 0 354 355 //***************************************************************************** 356 // 357 // The following are defines for the bit fields in the SHAMD5_O_DATA_8_IN 358 // register. 359 // 360 //***************************************************************************** 361 #define SHAMD5_DATA_8_IN_DATA_M 0xFFFFFFFF // Digest/Key Data 362 #define SHAMD5_DATA_8_IN_DATA_S 0 363 364 //***************************************************************************** 365 // 366 // The following are defines for the bit fields in the SHAMD5_O_DATA_9_IN 367 // register. 368 // 369 //***************************************************************************** 370 #define SHAMD5_DATA_9_IN_DATA_M 0xFFFFFFFF // Digest/Key Data 371 #define SHAMD5_DATA_9_IN_DATA_S 0 372 373 //***************************************************************************** 374 // 375 // The following are defines for the bit fields in the SHAMD5_O_DATA_10_IN 376 // register. 377 // 378 //***************************************************************************** 379 #define SHAMD5_DATA_10_IN_DATA_M \ 380 0xFFFFFFFF // Digest/Key Data 381 #define SHAMD5_DATA_10_IN_DATA_S \ 382 0 383 384 //***************************************************************************** 385 // 386 // The following are defines for the bit fields in the SHAMD5_O_DATA_11_IN 387 // register. 388 // 389 //***************************************************************************** 390 #define SHAMD5_DATA_11_IN_DATA_M \ 391 0xFFFFFFFF // Digest/Key Data 392 #define SHAMD5_DATA_11_IN_DATA_S \ 393 0 394 395 //***************************************************************************** 396 // 397 // The following are defines for the bit fields in the SHAMD5_O_DATA_12_IN 398 // register. 399 // 400 //***************************************************************************** 401 #define SHAMD5_DATA_12_IN_DATA_M \ 402 0xFFFFFFFF // Digest/Key Data 403 #define SHAMD5_DATA_12_IN_DATA_S \ 404 0 405 406 //***************************************************************************** 407 // 408 // The following are defines for the bit fields in the SHAMD5_O_DATA_13_IN 409 // register. 410 // 411 //***************************************************************************** 412 #define SHAMD5_DATA_13_IN_DATA_M \ 413 0xFFFFFFFF // Digest/Key Data 414 #define SHAMD5_DATA_13_IN_DATA_S \ 415 0 416 417 //***************************************************************************** 418 // 419 // The following are defines for the bit fields in the SHAMD5_O_DATA_14_IN 420 // register. 421 // 422 //***************************************************************************** 423 #define SHAMD5_DATA_14_IN_DATA_M \ 424 0xFFFFFFFF // Digest/Key Data 425 #define SHAMD5_DATA_14_IN_DATA_S \ 426 0 427 428 //***************************************************************************** 429 // 430 // The following are defines for the bit fields in the SHAMD5_O_DATA_15_IN 431 // register. 432 // 433 //***************************************************************************** 434 #define SHAMD5_DATA_15_IN_DATA_M \ 435 0xFFFFFFFF // Digest/Key Data 436 #define SHAMD5_DATA_15_IN_DATA_S \ 437 0 438 439 //***************************************************************************** 440 // 441 // The following are defines for the bit fields in the SHAMD5_O_REVISION 442 // register. 443 // 444 //***************************************************************************** 445 #define SHAMD5_REVISION_M 0xFFFFFFFF // Revision Number 446 #define SHAMD5_REVISION_S 0 447 448 //***************************************************************************** 449 // 450 // The following are defines for the bit fields in the SHAMD5_O_SYSCONFIG 451 // register. 452 // 453 //***************************************************************************** 454 #define SHAMD5_SYSCONFIG_SADVANCED \ 455 0x00000080 // Advanced Mode Enable 456 #define SHAMD5_SYSCONFIG_SIDLE_M \ 457 0x00000030 // Sidle mode 458 #define SHAMD5_SYSCONFIG_SIDLE_FORCE \ 459 0x00000000 // Force-idle mode 460 #define SHAMD5_SYSCONFIG_DMA_EN 0x00000008 // uDMA Request Enable 461 #define SHAMD5_SYSCONFIG_IT_EN 0x00000004 // Interrupt Enable 462 #define SHAMD5_SYSCONFIG_SOFTRESET \ 463 0x00000002 // Soft reset 464 465 //***************************************************************************** 466 // 467 // The following are defines for the bit fields in the SHAMD5_O_SYSSTATUS 468 // register. 469 // 470 //***************************************************************************** 471 #define SHAMD5_SYSSTATUS_RESETDONE \ 472 0x00000001 // Reset done status 473 474 //***************************************************************************** 475 // 476 // The following are defines for the bit fields in the SHAMD5_O_IRQSTATUS 477 // register. 478 // 479 //***************************************************************************** 480 #define SHAMD5_IRQSTATUS_CONTEXT_READY \ 481 0x00000008 // Context Ready Status 482 #define SHAMD5_IRQSTATUS_INPUT_READY \ 483 0x00000002 // Input Ready Status 484 #define SHAMD5_IRQSTATUS_OUTPUT_READY \ 485 0x00000001 // Output Ready Status 486 487 //***************************************************************************** 488 // 489 // The following are defines for the bit fields in the SHAMD5_O_IRQENABLE 490 // register. 491 // 492 //***************************************************************************** 493 #define SHAMD5_IRQENABLE_CONTEXT_READY \ 494 0x00000008 // Mask for context ready interrupt 495 #define SHAMD5_IRQENABLE_INPUT_READY \ 496 0x00000002 // Mask for input ready interrupt 497 #define SHAMD5_IRQENABLE_OUTPUT_READY \ 498 0x00000001 // Mask for output ready interrupt 499 500 //***************************************************************************** 501 // 502 // The following are defines for the bit fields in the SHAMD5_O_DMAIM register. 503 // 504 //***************************************************************************** 505 #define SHAMD5_DMAIM_COUT 0x00000004 // Context Out DMA Done Interrupt 506 // Mask 507 #define SHAMD5_DMAIM_DIN 0x00000002 // Data In DMA Done Interrupt Mask 508 #define SHAMD5_DMAIM_CIN 0x00000001 // Context In DMA Done Interrupt 509 // Mask 510 511 //***************************************************************************** 512 // 513 // The following are defines for the bit fields in the SHAMD5_O_DMARIS 514 // register. 515 // 516 //***************************************************************************** 517 #define SHAMD5_DMARIS_COUT 0x00000004 // Context Out DMA Done Raw 518 // Interrupt Status 519 #define SHAMD5_DMARIS_DIN 0x00000002 // Data In DMA Done Raw Interrupt 520 // Status 521 #define SHAMD5_DMARIS_CIN 0x00000001 // Context In DMA Done Raw 522 // Interrupt Status 523 524 //***************************************************************************** 525 // 526 // The following are defines for the bit fields in the SHAMD5_O_DMAMIS 527 // register. 528 // 529 //***************************************************************************** 530 #define SHAMD5_DMAMIS_COUT 0x00000004 // Context Out DMA Done Masked 531 // Interrupt Status 532 #define SHAMD5_DMAMIS_DIN 0x00000002 // Data In DMA Done Masked 533 // Interrupt Status 534 #define SHAMD5_DMAMIS_CIN 0x00000001 // Context In DMA Done Raw 535 // Interrupt Status 536 537 //***************************************************************************** 538 // 539 // The following are defines for the bit fields in the SHAMD5_O_DMAIC register. 540 // 541 //***************************************************************************** 542 #define SHAMD5_DMAIC_COUT 0x00000004 // Context Out DMA Done Masked 543 // Interrupt Status 544 #define SHAMD5_DMAIC_DIN 0x00000002 // Data In DMA Done Interrupt Clear 545 #define SHAMD5_DMAIC_CIN 0x00000001 // Context In DMA Done Raw 546 // Interrupt Status 547 548 #endif // __HW_SHAMD5_H__ 549