1 //***************************************************************************** 2 // 3 // hw_ssi.h - Macros used when accessing the SSI hardware. 4 // 5 // Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. 6 // Software License Agreement 7 // 8 // Redistribution and use in source and binary forms, with or without 9 // modification, are permitted provided that the following conditions 10 // are met: 11 // 12 // Redistributions of source code must retain the above copyright 13 // notice, this list of conditions and the following disclaimer. 14 // 15 // Redistributions in binary form must reproduce the above copyright 16 // notice, this list of conditions and the following disclaimer in the 17 // documentation and/or other materials provided with the 18 // distribution. 19 // 20 // Neither the name of Texas Instruments Incorporated nor the names of 21 // its contributors may be used to endorse or promote products derived 22 // from this software without specific prior written permission. 23 // 24 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 27 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 28 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 29 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 30 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 34 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 // 36 // This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. 37 // 38 //***************************************************************************** 39 40 #ifndef __HW_SSI_H__ 41 #define __HW_SSI_H__ 42 43 //***************************************************************************** 44 // 45 // The following are defines for the SSI register offsets. 46 // 47 //***************************************************************************** 48 #define SSI_O_CR0 0x00000000 // SSI Control 0 49 #define SSI_O_CR1 0x00000004 // SSI Control 1 50 #define SSI_O_DR 0x00000008 // SSI Data 51 #define SSI_O_SR 0x0000000C // SSI Status 52 #define SSI_O_CPSR 0x00000010 // SSI Clock Prescale 53 #define SSI_O_IM 0x00000014 // SSI Interrupt Mask 54 #define SSI_O_RIS 0x00000018 // SSI Raw Interrupt Status 55 #define SSI_O_MIS 0x0000001C // SSI Masked Interrupt Status 56 #define SSI_O_ICR 0x00000020 // SSI Interrupt Clear 57 #define SSI_O_DMACTL 0x00000024 // SSI DMA Control 58 #define SSI_O_PP 0x00000FC0 // SSI Peripheral Properties 59 #define SSI_O_CC 0x00000FC8 // SSI Clock Configuration 60 61 //***************************************************************************** 62 // 63 // The following are defines for the bit fields in the SSI_O_CR0 register. 64 // 65 //***************************************************************************** 66 #define SSI_CR0_SCR_M 0x0000FF00 // SSI Serial Clock Rate 67 #define SSI_CR0_SPH 0x00000080 // SSI Serial Clock Phase 68 #define SSI_CR0_SPO 0x00000040 // SSI Serial Clock Polarity 69 #define SSI_CR0_FRF_M 0x00000030 // SSI Frame Format Select 70 #define SSI_CR0_FRF_MOTO 0x00000000 // Freescale SPI Frame Format 71 #define SSI_CR0_FRF_TI 0x00000010 // Synchronous Serial Frame Format 72 #define SSI_CR0_FRF_NMW 0x00000020 // MICROWIRE Frame Format 73 #define SSI_CR0_DSS_M 0x0000000F // SSI Data Size Select 74 #define SSI_CR0_DSS_4 0x00000003 // 4-bit data 75 #define SSI_CR0_DSS_5 0x00000004 // 5-bit data 76 #define SSI_CR0_DSS_6 0x00000005 // 6-bit data 77 #define SSI_CR0_DSS_7 0x00000006 // 7-bit data 78 #define SSI_CR0_DSS_8 0x00000007 // 8-bit data 79 #define SSI_CR0_DSS_9 0x00000008 // 9-bit data 80 #define SSI_CR0_DSS_10 0x00000009 // 10-bit data 81 #define SSI_CR0_DSS_11 0x0000000A // 11-bit data 82 #define SSI_CR0_DSS_12 0x0000000B // 12-bit data 83 #define SSI_CR0_DSS_13 0x0000000C // 13-bit data 84 #define SSI_CR0_DSS_14 0x0000000D // 14-bit data 85 #define SSI_CR0_DSS_15 0x0000000E // 15-bit data 86 #define SSI_CR0_DSS_16 0x0000000F // 16-bit data 87 #define SSI_CR0_SCR_S 8 88 89 //***************************************************************************** 90 // 91 // The following are defines for the bit fields in the SSI_O_CR1 register. 92 // 93 //***************************************************************************** 94 #define SSI_CR1_EOM 0x00000800 // Stop Frame (End of Message) 95 #define SSI_CR1_FSSHLDFRM 0x00000400 // FSS Hold Frame 96 #define SSI_CR1_HSCLKEN 0x00000200 // High Speed Clock Enable 97 #define SSI_CR1_DIR 0x00000100 // SSI Direction of Operation 98 #define SSI_CR1_MODE_M 0x000000C0 // SSI Mode 99 #define SSI_CR1_MODE_LEGACY 0x00000000 // Legacy SSI mode 100 #define SSI_CR1_MODE_BI 0x00000040 // Bi-SSI mode 101 #define SSI_CR1_MODE_QUAD 0x00000080 // Quad-SSI Mode 102 #define SSI_CR1_MODE_ADVANCED 0x000000C0 // Advanced SSI Mode with 8-bit 103 // packet size 104 #define SSI_CR1_EOT 0x00000010 // End of Transmission 105 #define SSI_CR1_MS 0x00000004 // SSI Master/Slave Select 106 #define SSI_CR1_SSE 0x00000002 // SSI Synchronous Serial Port 107 // Enable 108 #define SSI_CR1_LBM 0x00000001 // SSI Loopback Mode 109 110 //***************************************************************************** 111 // 112 // The following are defines for the bit fields in the SSI_O_DR register. 113 // 114 //***************************************************************************** 115 #define SSI_DR_DATA_M 0x0000FFFF // SSI Receive/Transmit Data 116 #define SSI_DR_DATA_S 0 117 118 //***************************************************************************** 119 // 120 // The following are defines for the bit fields in the SSI_O_SR register. 121 // 122 //***************************************************************************** 123 #define SSI_SR_BSY 0x00000010 // SSI Busy Bit 124 #define SSI_SR_RFF 0x00000008 // SSI Receive FIFO Full 125 #define SSI_SR_RNE 0x00000004 // SSI Receive FIFO Not Empty 126 #define SSI_SR_TNF 0x00000002 // SSI Transmit FIFO Not Full 127 #define SSI_SR_TFE 0x00000001 // SSI Transmit FIFO Empty 128 129 //***************************************************************************** 130 // 131 // The following are defines for the bit fields in the SSI_O_CPSR register. 132 // 133 //***************************************************************************** 134 #define SSI_CPSR_CPSDVSR_M 0x000000FF // SSI Clock Prescale Divisor 135 #define SSI_CPSR_CPSDVSR_S 0 136 137 //***************************************************************************** 138 // 139 // The following are defines for the bit fields in the SSI_O_IM register. 140 // 141 //***************************************************************************** 142 #define SSI_IM_EOTIM 0x00000040 // End of Transmit Interrupt Mask 143 #define SSI_IM_DMATXIM 0x00000020 // SSI Transmit DMA Interrupt Mask 144 #define SSI_IM_DMARXIM 0x00000010 // SSI Receive DMA Interrupt Mask 145 #define SSI_IM_TXIM 0x00000008 // SSI Transmit FIFO Interrupt Mask 146 #define SSI_IM_RXIM 0x00000004 // SSI Receive FIFO Interrupt Mask 147 #define SSI_IM_RTIM 0x00000002 // SSI Receive Time-Out Interrupt 148 // Mask 149 #define SSI_IM_RORIM 0x00000001 // SSI Receive Overrun Interrupt 150 // Mask 151 152 //***************************************************************************** 153 // 154 // The following are defines for the bit fields in the SSI_O_RIS register. 155 // 156 //***************************************************************************** 157 #define SSI_RIS_EOTRIS 0x00000040 // End of Transmit Raw Interrupt 158 // Status 159 #define SSI_RIS_DMATXRIS 0x00000020 // SSI Transmit DMA Raw Interrupt 160 // Status 161 #define SSI_RIS_DMARXRIS 0x00000010 // SSI Receive DMA Raw Interrupt 162 // Status 163 #define SSI_RIS_TXRIS 0x00000008 // SSI Transmit FIFO Raw Interrupt 164 // Status 165 #define SSI_RIS_RXRIS 0x00000004 // SSI Receive FIFO Raw Interrupt 166 // Status 167 #define SSI_RIS_RTRIS 0x00000002 // SSI Receive Time-Out Raw 168 // Interrupt Status 169 #define SSI_RIS_RORRIS 0x00000001 // SSI Receive Overrun Raw 170 // Interrupt Status 171 172 //***************************************************************************** 173 // 174 // The following are defines for the bit fields in the SSI_O_MIS register. 175 // 176 //***************************************************************************** 177 #define SSI_MIS_EOTMIS 0x00000040 // End of Transmit Masked Interrupt 178 // Status 179 #define SSI_MIS_DMATXMIS 0x00000020 // SSI Transmit DMA Masked 180 // Interrupt Status 181 #define SSI_MIS_DMARXMIS 0x00000010 // SSI Receive DMA Masked Interrupt 182 // Status 183 #define SSI_MIS_TXMIS 0x00000008 // SSI Transmit FIFO Masked 184 // Interrupt Status 185 #define SSI_MIS_RXMIS 0x00000004 // SSI Receive FIFO Masked 186 // Interrupt Status 187 #define SSI_MIS_RTMIS 0x00000002 // SSI Receive Time-Out Masked 188 // Interrupt Status 189 #define SSI_MIS_RORMIS 0x00000001 // SSI Receive Overrun Masked 190 // Interrupt Status 191 192 //***************************************************************************** 193 // 194 // The following are defines for the bit fields in the SSI_O_ICR register. 195 // 196 //***************************************************************************** 197 #define SSI_ICR_EOTIC 0x00000040 // End of Transmit Interrupt Clear 198 #define SSI_ICR_DMATXIC 0x00000020 // SSI Transmit DMA Interrupt Clear 199 #define SSI_ICR_DMARXIC 0x00000010 // SSI Receive DMA Interrupt Clear 200 #define SSI_ICR_RTIC 0x00000002 // SSI Receive Time-Out Interrupt 201 // Clear 202 #define SSI_ICR_RORIC 0x00000001 // SSI Receive Overrun Interrupt 203 // Clear 204 205 //***************************************************************************** 206 // 207 // The following are defines for the bit fields in the SSI_O_DMACTL register. 208 // 209 //***************************************************************************** 210 #define SSI_DMACTL_TXDMAE 0x00000002 // Transmit DMA Enable 211 #define SSI_DMACTL_RXDMAE 0x00000001 // Receive DMA Enable 212 213 //***************************************************************************** 214 // 215 // The following are defines for the bit fields in the SSI_O_PP register. 216 // 217 //***************************************************************************** 218 #define SSI_PP_FSSHLDFRM 0x00000008 // FSS Hold Frame Capability 219 #define SSI_PP_MODE_M 0x00000006 // Mode of Operation 220 #define SSI_PP_MODE_LEGACY 0x00000000 // Legacy SSI mode 221 #define SSI_PP_MODE_ADVBI 0x00000002 // Legacy mode, Advanced SSI mode 222 // and Bi-SSI mode enabled 223 #define SSI_PP_MODE_ADVBIQUAD 0x00000004 // Legacy mode, Advanced mode, 224 // Bi-SSI and Quad-SSI mode enabled 225 #define SSI_PP_HSCLK 0x00000001 // High Speed Capability 226 227 //***************************************************************************** 228 // 229 // The following are defines for the bit fields in the SSI_O_CC register. 230 // 231 //***************************************************************************** 232 #define SSI_CC_CS_M 0x0000000F // SSI Baud Clock Source 233 #define SSI_CC_CS_SYSPLL 0x00000000 // System clock (based on clock 234 // source and divisor factor) 235 #define SSI_CC_CS_PIOSC 0x00000005 // PIOSC 236 237 #endif // __HW_SSI_H__ 238