1 //***************************************************************************** 2 // 3 // udma.h - Prototypes and macros for the uDMA controller. 4 // 5 // Copyright (c) 2007-2017 Texas Instruments Incorporated. All rights reserved. 6 // Software License Agreement 7 // 8 // Redistribution and use in source and binary forms, with or without 9 // modification, are permitted provided that the following conditions 10 // are met: 11 // 12 // Redistributions of source code must retain the above copyright 13 // notice, this list of conditions and the following disclaimer. 14 // 15 // Redistributions in binary form must reproduce the above copyright 16 // notice, this list of conditions and the following disclaimer in the 17 // documentation and/or other materials provided with the 18 // distribution. 19 // 20 // Neither the name of Texas Instruments Incorporated nor the names of 21 // its contributors may be used to endorse or promote products derived 22 // from this software without specific prior written permission. 23 // 24 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 27 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 28 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 29 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 30 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 34 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 // 36 // This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. 37 // 38 //***************************************************************************** 39 40 #ifndef __DRIVERLIB_UDMA_H__ 41 #define __DRIVERLIB_UDMA_H__ 42 43 //***************************************************************************** 44 // 45 // If building with a C++ compiler, make all of the definitions in this header 46 // have a C binding. 47 // 48 //***************************************************************************** 49 #ifdef __cplusplus 50 extern "C" 51 { 52 #endif 53 54 //***************************************************************************** 55 // 56 //! \addtogroup udma_api 57 //! @{ 58 // 59 //***************************************************************************** 60 61 //***************************************************************************** 62 // 63 // A structure that defines an entry in the channel control table. These 64 // fields are used by the uDMA controller and normally it is not necessary for 65 // software to directly read or write fields in the table. 66 // 67 //***************************************************************************** 68 typedef struct 69 { 70 // 71 // The ending source address of the data transfer. 72 // 73 volatile void *pvSrcEndAddr; 74 75 // 76 // The ending destination address of the data transfer. 77 // 78 volatile void *pvDstEndAddr; 79 80 // 81 // The channel control mode. 82 // 83 volatile uint32_t ui32Control; 84 85 // 86 // An unused location. 87 // 88 volatile uint32_t ui32Spare; 89 } 90 tDMAControlTable; 91 92 //***************************************************************************** 93 // 94 //! A helper macro for building scatter-gather task table entries. 95 //! 96 //! \param ui32TransferCount is the count of items to transfer for this task. 97 //! \param ui32ItemSize is the bit size of the items to transfer for this task. 98 //! \param ui32SrcIncrement is the bit size increment for source data. 99 //! \param pvSrcAddr is the starting address of the data to transfer. 100 //! \param ui32DstIncrement is the bit size increment for destination data. 101 //! \param pvDstAddr is the starting address of the destination data. 102 //! \param ui32ArbSize is the arbitration size to use for the transfer task. 103 //! \param ui32Mode is the transfer mode for this task. 104 //! 105 //! This macro is intended to be used to help populate a table of uDMA tasks 106 //! for a scatter-gather transfer. This macro will calculate the values for 107 //! the fields of a task structure entry based on the input parameters. 108 //! 109 //! There are specific requirements for the values of each parameter. No 110 //! checking is done so it is up to the caller to ensure that correct values 111 //! are used for the parameters. 112 //! 113 //! The \e ui32TransferCount parameter is the number of items that will be 114 //! transferred by this task. It must be in the range 1-1024. 115 //! 116 //! The \e ui32ItemSize parameter is the bit size of the transfer data. It 117 //! must be one of \b UDMA_SIZE_8, \b UDMA_SIZE_16, or \b UDMA_SIZE_32. 118 //! 119 //! The \e ui32SrcIncrement parameter is the increment size for the source 120 //! data. It must be one of \b UDMA_SRC_INC_8, \b UDMA_SRC_INC_16, 121 //! \b UDMA_SRC_INC_32, or \b UDMA_SRC_INC_NONE. 122 //! 123 //! The \e pvSrcAddr parameter is a void pointer to the beginning of the source 124 //! data. 125 //! 126 //! The \e ui32DstIncrement parameter is the increment size for the destination 127 //! data. It must be one of \b UDMA_DST_INC_8, \b UDMA_DST_INC_16, 128 //! \b UDMA_DST_INC_32, or \b UDMA_DST_INC_NONE. 129 //! 130 //! The \e pvDstAddr parameter is a void pointer to the beginning of the 131 //! location where the data will be transferred. 132 //! 133 //! The \e ui32ArbSize parameter is the arbitration size for the transfer, and 134 //! must be one of \b UDMA_ARB_1, \b UDMA_ARB_2, \b UDMA_ARB_4, and so on 135 //! up to \b UDMA_ARB_1024. This is used to select the arbitration size in 136 //! powers of 2, from 1 to 1024. 137 //! 138 //! The \e ui32Mode parameter is the mode to use for this transfer task. It 139 //! must be one of \b UDMA_MODE_BASIC, \b UDMA_MODE_AUTO, 140 //! \b UDMA_MODE_MEM_SCATTER_GATHER, or \b UDMA_MODE_PER_SCATTER_GATHER. Note 141 //! that normally all tasks will be one of the scatter-gather modes while the 142 //! last task is a task list will be AUTO or BASIC. 143 //! 144 //! This macro is intended to be used to initialize individual entries of 145 //! a structure of tDMAControlTable type, like this: 146 //! 147 //! \verbatim 148 //! tDMAControlTable MyTaskList[] = 149 //! { 150 //! uDMATaskStructEntry(Task1Count, UDMA_SIZE_8, 151 //! UDMA_SRC_INC_8, MySourceBuf, 152 //! UDMA_DST_INC_8, MyDestBuf, 153 //! UDMA_ARB_8, UDMA_MODE_MEM_SCATTER_GATHER), 154 //! uDMATaskStructEntry(Task2Count, ...), 155 //! } 156 //! \endverbatim 157 //! 158 //! \return Nothing; this is not a function. 159 // 160 //***************************************************************************** 161 #define uDMATaskStructEntry(ui32TransferCount, \ 162 ui32ItemSize, \ 163 ui32SrcIncrement, \ 164 pvSrcAddr, \ 165 ui32DstIncrement, \ 166 pvDstAddr, \ 167 ui32ArbSize, \ 168 ui32Mode) \ 169 { \ 170 (((ui32SrcIncrement) == UDMA_SRC_INC_NONE) ? (void *)(pvSrcAddr) : \ 171 ((void *)(&((uint8_t *)(pvSrcAddr))[((ui32TransferCount) << \ 172 ((ui32SrcIncrement) >> 26)) - 1]))), \ 173 (((ui32DstIncrement) == UDMA_DST_INC_NONE) ? (void *)(pvDstAddr) :\ 174 ((void *)(&((uint8_t *)(pvDstAddr))[((ui32TransferCount) << \ 175 ((ui32DstIncrement) >> 30)) - 1]))), \ 176 (ui32SrcIncrement) | (ui32DstIncrement) | (ui32ItemSize) | \ 177 (ui32ArbSize) | \ 178 (((ui32TransferCount) - 1) << 4) | \ 179 ((((ui32Mode) == UDMA_MODE_MEM_SCATTER_GATHER) || \ 180 ((ui32Mode) == UDMA_MODE_PER_SCATTER_GATHER)) ? \ 181 (ui32Mode) | UDMA_MODE_ALT_SELECT : (ui32Mode)), 0 \ 182 } 183 184 //***************************************************************************** 185 // 186 // Close the Doxygen group. 187 //! @} 188 // 189 //***************************************************************************** 190 191 //***************************************************************************** 192 // 193 // Flags that can be passed to uDMAChannelAttributeEnable(), 194 // uDMAChannelAttributeDisable(), and returned from uDMAChannelAttributeGet(). 195 // 196 //***************************************************************************** 197 #define UDMA_ATTR_USEBURST 0x00000001 198 #define UDMA_ATTR_ALTSELECT 0x00000002 199 #define UDMA_ATTR_HIGH_PRIORITY 0x00000004 200 #define UDMA_ATTR_REQMASK 0x00000008 201 #define UDMA_ATTR_ALL 0x0000000F 202 203 //***************************************************************************** 204 // 205 // DMA control modes that can be passed to uDMAModeSet() and returned 206 // uDMAModeGet(). 207 // 208 //***************************************************************************** 209 #define UDMA_MODE_STOP 0x00000000 210 #define UDMA_MODE_BASIC 0x00000001 211 #define UDMA_MODE_AUTO 0x00000002 212 #define UDMA_MODE_PINGPONG 0x00000003 213 #define UDMA_MODE_MEM_SCATTER_GATHER \ 214 0x00000004 215 #define UDMA_MODE_PER_SCATTER_GATHER \ 216 0x00000006 217 #define UDMA_MODE_ALT_SELECT 0x00000001 218 219 //***************************************************************************** 220 // 221 // Channel configuration values that can be passed to uDMAControlSet(). 222 // 223 //***************************************************************************** 224 #define UDMA_DST_INC_8 0x00000000 225 #define UDMA_DST_INC_16 0x40000000 226 #define UDMA_DST_INC_32 0x80000000 227 #define UDMA_DST_INC_NONE 0xc0000000 228 #define UDMA_SRC_INC_8 0x00000000 229 #define UDMA_SRC_INC_16 0x04000000 230 #define UDMA_SRC_INC_32 0x08000000 231 #define UDMA_SRC_INC_NONE 0x0c000000 232 #define UDMA_SIZE_8 0x00000000 233 #define UDMA_SIZE_16 0x11000000 234 #define UDMA_SIZE_32 0x22000000 235 #define UDMA_DST_PROT_PRIV 0x00200000 236 #define UDMA_SRC_PROT_PRIV 0x00040000 237 #define UDMA_ARB_1 0x00000000 238 #define UDMA_ARB_2 0x00004000 239 #define UDMA_ARB_4 0x00008000 240 #define UDMA_ARB_8 0x0000c000 241 #define UDMA_ARB_16 0x00010000 242 #define UDMA_ARB_32 0x00014000 243 #define UDMA_ARB_64 0x00018000 244 #define UDMA_ARB_128 0x0001c000 245 #define UDMA_ARB_256 0x00020000 246 #define UDMA_ARB_512 0x00024000 247 #define UDMA_ARB_1024 0x00028000 248 #define UDMA_NEXT_USEBURST 0x00000008 249 250 //***************************************************************************** 251 // 252 // Channel numbers to be passed to API functions that require a channel number 253 // ID. 254 // 255 //***************************************************************************** 256 #define UDMA_CHANNEL_USBEP1RX 0 257 #define UDMA_CHANNEL_USBEP1TX 1 258 #define UDMA_CHANNEL_USBEP2RX 2 259 #define UDMA_CHANNEL_USBEP2TX 3 260 #define UDMA_CHANNEL_USBEP3RX 4 261 #define UDMA_CHANNEL_USBEP3TX 5 262 #define UDMA_CHANNEL_ETH0RX 6 263 #define UDMA_CHANNEL_ETH0TX 7 264 #define UDMA_CHANNEL_UART0RX 8 265 #define UDMA_CHANNEL_UART0TX 9 266 #define UDMA_CHANNEL_SSI0RX 10 267 #define UDMA_CHANNEL_SSI0TX 11 268 #define UDMA_CHANNEL_ADC0 14 269 #define UDMA_CHANNEL_ADC1 15 270 #define UDMA_CHANNEL_ADC2 16 271 #define UDMA_CHANNEL_ADC3 17 272 #define UDMA_CHANNEL_TMR0A 18 273 #define UDMA_CHANNEL_TMR0B 19 274 #define UDMA_CHANNEL_TMR1A 20 275 #define UDMA_CHANNEL_TMR1B 21 276 #define UDMA_CHANNEL_UART1RX 22 277 #define UDMA_CHANNEL_UART1TX 23 278 #define UDMA_CHANNEL_SSI1RX 24 279 #define UDMA_CHANNEL_SSI1TX 25 280 #define UDMA_CHANNEL_I2S0RX 28 281 #define UDMA_CHANNEL_I2S0TX 29 282 #define UDMA_CHANNEL_SW 30 283 284 //***************************************************************************** 285 // 286 // Flags to be OR'd with the channel ID to indicate if the primary or alternate 287 // control structure should be used. 288 // 289 //***************************************************************************** 290 #define UDMA_PRI_SELECT 0x00000000 291 #define UDMA_ALT_SELECT 0x00000020 292 293 //***************************************************************************** 294 // 295 // Channel numbers to be passed to API functions that require a channel number 296 // ID. These are for secondary peripheral assignments. 297 // 298 //***************************************************************************** 299 #define UDMA_SEC_CHANNEL_UART2RX_0 \ 300 0 301 #define UDMA_SEC_CHANNEL_UART2TX_1 \ 302 1 303 #define UDMA_SEC_CHANNEL_TMR3A 2 304 #define UDMA_SEC_CHANNEL_TMR3B 3 305 #define UDMA_SEC_CHANNEL_TMR2A_4 \ 306 4 307 #define UDMA_SEC_CHANNEL_TMR2B_5 \ 308 5 309 #define UDMA_SEC_CHANNEL_TMR2A_6 \ 310 6 311 #define UDMA_SEC_CHANNEL_TMR2B_7 \ 312 7 313 #define UDMA_SEC_CHANNEL_UART1RX \ 314 8 315 #define UDMA_SEC_CHANNEL_UART1TX \ 316 9 317 #define UDMA_SEC_CHANNEL_SSI1RX 10 318 #define UDMA_SEC_CHANNEL_SSI1TX 11 319 #define UDMA_SEC_CHANNEL_UART2RX_12 \ 320 12 321 #define UDMA_SEC_CHANNEL_UART2TX_13 \ 322 13 323 #define UDMA_SEC_CHANNEL_TMR2A_14 \ 324 14 325 #define UDMA_SEC_CHANNEL_TMR2B_15 \ 326 15 327 #define UDMA_SEC_CHANNEL_TMR1A 18 328 #define UDMA_SEC_CHANNEL_TMR1B 19 329 #define UDMA_SEC_CHANNEL_EPI0RX 20 330 #define UDMA_SEC_CHANNEL_EPI0TX 21 331 #define UDMA_SEC_CHANNEL_ADC10 24 332 #define UDMA_SEC_CHANNEL_ADC11 25 333 #define UDMA_SEC_CHANNEL_ADC12 26 334 #define UDMA_SEC_CHANNEL_ADC13 27 335 #define UDMA_SEC_CHANNEL_SW 30 336 337 //***************************************************************************** 338 // 339 // Values that can be passed to uDMAChannelAssign() to select peripheral 340 // mapping for each channel. The channels named RESERVED may be assigned 341 // to a peripheral in future parts. 342 // 343 //***************************************************************************** 344 // 345 // Channel 0 346 // 347 #define UDMA_CH0_USB0EP1RX 0x00000000 348 #define UDMA_CH0_UART2RX 0x00010000 349 #define UDMA_CH0_RESERVED2 0x00020000 350 #define UDMA_CH0_TIMER4A 0x00030000 351 #define UDMA_CH0_RESERVED4 0x00040000 352 #define UDMA_CH0_RESERVED5 0x00050000 353 #define UDMA_CH0_I2C0RX 0x00060000 354 #define UDMA_CH0_RESERVED7 0x00070000 355 #define UDMA_CH0_RESERVED8 0x00080000 356 357 // 358 // Channel 1 359 // 360 #define UDMA_CH1_USB0EP1TX 0x00000001 361 #define UDMA_CH1_UART2TX 0x00010001 362 #define UDMA_CH1_RESERVED2 0x00020001 363 #define UDMA_CH1_TIMER4B 0x00030001 364 #define UDMA_CH1_RESERVED4 0x00040001 365 #define UDMA_CH1_RESERVED5 0x00050001 366 #define UDMA_CH1_I2C0TX 0x00060001 367 #define UDMA_CH1_RESERVED7 0x00070001 368 #define UDMA_CH1_RESERVED8 0x00080001 369 370 // 371 // Channel 2 372 // 373 #define UDMA_CH2_USB0EP2RX 0x00000002 374 #define UDMA_CH2_TIMER3A 0x00010002 375 #define UDMA_CH2_RESERVED2 0x00020002 376 #define UDMA_CH2_RESERVED3 0x00030002 377 #define UDMA_CH2_RESERVED4 0x00040002 378 #define UDMA_CH2_RESERVED5 0x00050002 379 #define UDMA_CH2_I2C1RX 0x00060002 380 #define UDMA_CH2_RESERVED7 0x00070002 381 #define UDMA_CH2_RESERVED8 0x00080002 382 383 // 384 // Channel 3 385 // 386 #define UDMA_CH3_USB0EP2TX 0x00000003 387 #define UDMA_CH3_TIMER3B 0x00010003 388 #define UDMA_CH3_RESERVED2 0x00020003 389 #define UDMA_CH3_LPC0_3 0x00030003 390 #define UDMA_CH3_RESERVED4 0x00040003 391 #define UDMA_CH3_RESERVED5 0x00050003 392 #define UDMA_CH3_I2C1TX 0x00060003 393 #define UDMA_CH3_RESERVED7 0x00070003 394 #define UDMA_CH3_RESERVED8 0x00080003 395 396 // 397 // Channel 4 398 // 399 #define UDMA_CH4_USB0EP3RX 0x00000004 400 #define UDMA_CH4_TIMER2A 0x00010004 401 #define UDMA_CH4_RESERVED2 0x00020004 402 #define UDMA_CH4_GPIOA 0x00030004 403 #define UDMA_CH4_RESERVED4 0x00040004 404 #define UDMA_CH4_SHAMD50CIN 0x00050004 405 #define UDMA_CH4_I2C2RX 0x00060004 406 #define UDMA_CH4_RESERVED7 0x00070004 407 #define UDMA_CH4_RESERVED8 0x00080004 408 409 // 410 // Channel 5 411 // 412 #define UDMA_CH5_USB0EP3TX 0x00000005 413 #define UDMA_CH5_TIMER2B 0x00010005 414 #define UDMA_CH5_RESERVED2 0x00020005 415 #define UDMA_CH5_GPIOB 0x00030005 416 #define UDMA_CH5_RESERVED4 0x00040005 417 #define UDMA_CH5_SHAMD50DIN 0x00050005 418 #define UDMA_CH5_I2C2TX 0x00060005 419 #define UDMA_CH5_RESERVED7 0x00070005 420 #define UDMA_CH5_RESERVED8 0x00080005 421 422 // 423 // Channel 6 424 // 425 #define UDMA_CH6_RESERVED0 0x00000006 426 #define UDMA_CH6_ETH0RX 0x00000006 427 #define UDMA_CH6_TIMER2A 0x00010006 428 #define UDMA_CH6_UART5RX 0x00020006 429 #define UDMA_CH6_GPIOC 0x00030006 430 #define UDMA_CH6_I2C0RX 0x00040006 431 #define UDMA_CH6_SHAMD50COUT 0x00050006 432 #define UDMA_CH6_RESERVED6 0x00060006 433 #define UDMA_CH6_RESERVED7 0x00070006 434 #define UDMA_CH6_RESERVED8 0x00080006 435 436 // 437 // Channel 7 438 // 439 #define UDMA_CH7_RESERVED0 0x00000007 440 #define UDMA_CH7_ETH0TX 0x00000007 441 #define UDMA_CH7_TIMER2B 0x00010007 442 #define UDMA_CH7_UART5TX 0x00020007 443 #define UDMA_CH7_GPIOD 0x00030007 444 #define UDMA_CH7_I2C0TX 0x00040007 445 #define UDMA_CH7_RESERVED5 0x00050007 446 #define UDMA_CH7_RESERVED6 0x00060007 447 #define UDMA_CH7_RESERVED7 0x00070007 448 #define UDMA_CH7_RESERVED8 0x00080007 449 450 // 451 // Channel 8 452 // 453 #define UDMA_CH8_UART0RX 0x00000008 454 #define UDMA_CH8_UART1RX 0x00010008 455 #define UDMA_CH8_RESERVED2 0x00020008 456 #define UDMA_CH8_TIMER5A 0x00030008 457 #define UDMA_CH8_I2C1RX 0x00040008 458 #define UDMA_CH8_RESERVED5 0x00050008 459 #define UDMA_CH8_RESERVED6 0x00060008 460 #define UDMA_CH8_RESERVED7 0x00070008 461 #define UDMA_CH8_RESERVED8 0x00080008 462 463 // 464 // Channel 9 465 // 466 #define UDMA_CH9_UART0TX 0x00000009 467 #define UDMA_CH9_UART1TX 0x00010009 468 #define UDMA_CH9_RESERVED2 0x00020009 469 #define UDMA_CH9_TIMER5B 0x00030009 470 #define UDMA_CH9_I2C1TX 0x00040009 471 #define UDMA_CH9_RESERVED5 0x00050009 472 #define UDMA_CH9_RESERVED6 0x00060009 473 #define UDMA_CH9_RESERVED7 0x00070009 474 #define UDMA_CH9_RESERVED8 0x00080009 475 476 // 477 // Channel 10 478 // 479 #define UDMA_CH10_SSI0RX 0x0000000A 480 #define UDMA_CH10_SSI1RX 0x0001000A 481 #define UDMA_CH10_UART6RX 0x0002000A 482 #define UDMA_CH10_WTIMER0A 0x0003000A 483 #define UDMA_CH10_I2C2RX 0x0004000A 484 #define UDMA_CH10_RESERVED5 0x0005000A 485 #define UDMA_CH10_RESERVED6 0x0006000A 486 #define UDMA_CH10_TIMER6A 0x0007000A 487 #define UDMA_CH10_RESERVED8 0x0008000A 488 489 // 490 // Channel 11 491 // 492 #define UDMA_CH11_SSI0TX 0x0000000B 493 #define UDMA_CH11_SSI1TX 0x0001000B 494 #define UDMA_CH11_UART6TX 0x0002000B 495 #define UDMA_CH11_WTIMER0B 0x0003000B 496 #define UDMA_CH11_I2C2TX 0x0004000B 497 #define UDMA_CH11_RESERVED5 0x0005000B 498 #define UDMA_CH11_RESERVED6 0x0006000B 499 #define UDMA_CH11_TIMER6B 0x0007000B 500 #define UDMA_CH11_RESERVED8 0x0008000B 501 502 // 503 // Channel 12 504 // 505 #define UDMA_CH12_RESERVED0 0x0000000C 506 #define UDMA_CH12_UART2RX 0x0001000C 507 #define UDMA_CH12_SSI2RX 0x0002000C 508 #define UDMA_CH12_WTIMER1A 0x0003000C 509 #define UDMA_CH12_GPIOK 0x0004000C 510 #define UDMA_CH12_AES0CIN 0x0005000C 511 #define UDMA_CH12_RESERVED6 0x0006000C 512 #define UDMA_CH12_TIMER7A 0x0007000C 513 #define UDMA_CH12_RESERVED8 0x0008000C 514 515 // 516 // Channel 13 517 // 518 #define UDMA_CH13_RESERVED0 0x0000000D 519 #define UDMA_CH13_UART2TX 0x0001000D 520 #define UDMA_CH13_SSI2TX 0x0002000D 521 #define UDMA_CH13_WTIMER1B 0x0003000D 522 #define UDMA_CH13_GPIOL 0x0004000D 523 #define UDMA_CH13_AES0COUT 0x0005000D 524 #define UDMA_CH13_RESERVED6 0x0006000D 525 #define UDMA_CH13_TIMER7B 0x0007000D 526 #define UDMA_CH13_RESERVED8 0x0008000D 527 528 // 529 // Channel 14 530 // 531 #define UDMA_CH14_ADC0_0 0x0000000E 532 #define UDMA_CH14_TIMER2A 0x0001000E 533 #define UDMA_CH14_SSI3RX 0x0002000E 534 #define UDMA_CH14_GPIOE 0x0003000E 535 #define UDMA_CH14_GPIOM 0x0004000E 536 #define UDMA_CH14_AES0DIN 0x0005000E 537 #define UDMA_CH14_RESERVED6 0x0006000E 538 #define UDMA_CH14_RESERVED7 0x0007000E 539 #define UDMA_CH14_RESERVED8 0x0008000E 540 541 // 542 // Channel 15 543 // 544 #define UDMA_CH15_ADC0_1 0x0000000F 545 #define UDMA_CH15_TIMER2B 0x0001000F 546 #define UDMA_CH15_SSI3TX 0x0002000F 547 #define UDMA_CH15_GPIOF 0x0003000F 548 #define UDMA_CH15_GPION 0x0004000F 549 #define UDMA_CH15_AES0DOUT 0x0005000F 550 #define UDMA_CH15_RESERVED6 0x0006000F 551 #define UDMA_CH15_RESERVED7 0x0007000F 552 #define UDMA_CH15_RESERVED8 0x0008000F 553 554 // 555 // Channel 16 556 // 557 #define UDMA_CH16_ADC0_2 0x00000010 558 #define UDMA_CH16_RESERVED1 0x00010010 559 #define UDMA_CH16_UART3RX 0x00020010 560 #define UDMA_CH16_WTIMER2A 0x00030010 561 #define UDMA_CH16_GPIOP 0x00040010 562 #define UDMA_CH16_RESERVED5 0x00050010 563 #define UDMA_CH16_RESERVED6 0x00060010 564 #define UDMA_CH16_RESERVED7 0x00070010 565 #define UDMA_CH16_RESERVED8 0x00080010 566 567 // 568 // Channel 17 569 // 570 #define UDMA_CH17_ADC0_3 0x00000011 571 #define UDMA_CH17_RESERVED1 0x00010011 572 #define UDMA_CH17_UART3TX 0x00020011 573 #define UDMA_CH17_WTIMER2B 0x00030011 574 #define UDMA_CH17_RESERVED4 0x00040011 575 #define UDMA_CH17_RESERVED5 0x00050011 576 #define UDMA_CH17_RESERVED6 0x00060011 577 #define UDMA_CH17_RESERVED7 0x00070011 578 #define UDMA_CH17_RESERVED8 0x00080011 579 580 // 581 // Channel 18 582 // 583 #define UDMA_CH18_TIMER0A 0x00000012 584 #define UDMA_CH18_TIMER1A 0x00010012 585 #define UDMA_CH18_UART4RX 0x00020012 586 #define UDMA_CH18_GPIOB 0x00030012 587 #define UDMA_CH18_I2C3RX 0x00040012 588 #define UDMA_CH18_RESERVED5 0x00050012 589 #define UDMA_CH18_RESERVED6 0x00060012 590 #define UDMA_CH18_RESERVED7 0x00070012 591 #define UDMA_CH18_RESERVED8 0x00080012 592 593 // 594 // Channel 19 595 // 596 #define UDMA_CH19_TIMER0B 0x00000013 597 #define UDMA_CH19_TIMER1B 0x00010013 598 #define UDMA_CH19_UART4TX 0x00020013 599 #define UDMA_CH19_GPIOG 0x00030013 600 #define UDMA_CH19_I2C3TX 0x00040013 601 #define UDMA_CH19_RESERVED5 0x00050013 602 #define UDMA_CH19_RESERVED6 0x00060013 603 #define UDMA_CH19_RESERVED7 0x00070013 604 #define UDMA_CH19_RESERVED8 0x00080013 605 606 // 607 // Channel 20 608 // 609 #define UDMA_CH20_TIMER1A 0x00000014 610 #define UDMA_CH20_RESERVED1 0x00010014 611 #define UDMA_CH20_EPI0RX 0x00010014 612 #define UDMA_CH20_UART7RX 0x00020014 613 #define UDMA_CH20_GPIOH 0x00030014 614 #define UDMA_CH20_I2C4RX 0x00040014 615 #define UDMA_CH20_DES0CIN 0x00050014 616 #define UDMA_CH20_RESERVED6 0x00060014 617 #define UDMA_CH20_RESERVED7 0x00070014 618 #define UDMA_CH20_RESERVED8 0x00080014 619 620 // 621 // Channel 21 622 // 623 #define UDMA_CH21_TIMER1B 0x00000015 624 #define UDMA_CH21_RESERVED1 0x00010015 625 #define UDMA_CH21_EPI0TX 0x00010015 626 #define UDMA_CH21_UART7TX 0x00020015 627 #define UDMA_CH21_GPIOJ 0x00030015 628 #define UDMA_CH21_I2C4TX 0x00040015 629 #define UDMA_CH21_DES0DIN 0x00050015 630 #define UDMA_CH21_RESERVED6 0x00060015 631 #define UDMA_CH21_RESERVED7 0x00070015 632 #define UDMA_CH21_RESERVED8 0x00080015 633 634 // 635 // Channel 22 636 // 637 #define UDMA_CH22_UART1RX 0x00000016 638 #define UDMA_CH22_RESERVED1 0x00010016 639 #define UDMA_CH22_RESERVED2 0x00020016 640 #define UDMA_CH22_LPC0_2 0x00030016 641 #define UDMA_CH22_I2C5RX 0x00040016 642 #define UDMA_CH22_DES0DOUT 0x00050016 643 #define UDMA_CH22_RESERVED6 0x00060016 644 #define UDMA_CH22_RESERVED7 0x00070016 645 #define UDMA_CH22_I2C8RX 0x00080016 646 647 // 648 // Channel 23 649 // 650 #define UDMA_CH23_UART1TX 0x00000017 651 #define UDMA_CH23_RESERVED1 0x00010017 652 #define UDMA_CH23_RESERVED2 0x00020017 653 #define UDMA_CH23_LPC0_1 0x00030017 654 #define UDMA_CH23_I2C5TX 0x00040017 655 #define UDMA_CH23_RESERVED5 0x00050017 656 #define UDMA_CH23_RESERVED6 0x00060017 657 #define UDMA_CH23_RESERVED7 0x00070017 658 #define UDMA_CH23_I2C8TX 0x00080017 659 660 // 661 // Channel 24 662 // 663 #define UDMA_CH24_SSI1RX 0x00000018 664 #define UDMA_CH24_ADC1_0 0x00010018 665 #define UDMA_CH24_RESERVED2 0x00020018 666 #define UDMA_CH24_WTIMER3A 0x00030018 667 #define UDMA_CH24_GPIOQ 0x00040018 668 #define UDMA_CH24_RESERVED5 0x00050018 669 #define UDMA_CH24_RESERVED6 0x00060018 670 #define UDMA_CH24_RESERVED7 0x00070018 671 #define UDMA_CH24_I2C9RX 0x00080018 672 673 // 674 // Channel 25 675 // 676 #define UDMA_CH25_SSI1TX 0x00000019 677 #define UDMA_CH25_ADC1_1 0x00010019 678 #define UDMA_CH25_RESERVED2 0x00020019 679 #define UDMA_CH25_WTIMER3B 0x00030019 680 #define UDMA_CH25_RESERVED4 0x00040019 681 #define UDMA_CH25_RESERVED5 0x00050019 682 #define UDMA_CH25_RESERVED6 0x00060019 683 #define UDMA_CH25_RESERVED7 0x00070019 684 #define UDMA_CH25_I2C9TX 0x00080019 685 686 // 687 // Channel 26 688 // 689 #define UDMA_CH26_RESERVED0 0x0000001A 690 #define UDMA_CH26_ADC1_2 0x0001001A 691 #define UDMA_CH26_RESERVED2 0x0002001A 692 #define UDMA_CH26_WTIMER4A 0x0003001A 693 #define UDMA_CH26_RESERVED4 0x0004001A 694 #define UDMA_CH26_RESERVED5 0x0005001A 695 #define UDMA_CH26_RESERVED6 0x0006001A 696 #define UDMA_CH26_RESERVED7 0x0007001A 697 #define UDMA_CH26_I2C6RX 0x0008001A 698 699 // 700 // Channel 27 701 // 702 #define UDMA_CH27_RESERVED0 0x0000001B 703 #define UDMA_CH27_ADC1_3 0x0001001B 704 #define UDMA_CH27_RESERVED2 0x0002001B 705 #define UDMA_CH27_WTIMER4B 0x0003001B 706 #define UDMA_CH27_RESERVED4 0x0004001B 707 #define UDMA_CH27_RESERVED5 0x0005001B 708 #define UDMA_CH27_RESERVED6 0x0006001B 709 #define UDMA_CH27_RESERVED7 0x0007001B 710 #define UDMA_CH27_I2C6TX 0x0008001B 711 712 // 713 // Channel 28 714 // 715 #define UDMA_CH28_RESERVED0 0x0000001C 716 #define UDMA_CH28_RESERVED1 0x0001001C 717 #define UDMA_CH28_RESERVED2 0x0002001C 718 #define UDMA_CH28_WTIMER5A 0x0003001C 719 #define UDMA_CH28_RESERVED4 0x0004001C 720 #define UDMA_CH28_RESERVED5 0x0005001C 721 #define UDMA_CH28_RESERVED6 0x0006001C 722 #define UDMA_CH28_RESERVED7 0x0007001C 723 #define UDMA_CH28_I2C7RX 0x0008001C 724 725 // 726 // Channel 29 727 // 728 #define UDMA_CH29_RESERVED0 0x0000001D 729 #define UDMA_CH29_RESERVED1 0x0001001D 730 #define UDMA_CH29_RESERVED2 0x0002001D 731 #define UDMA_CH29_WTIMER5B 0x0003001D 732 #define UDMA_CH29_RESERVED4 0x0004001D 733 #define UDMA_CH29_RESERVED5 0x0005001D 734 #define UDMA_CH29_RESERVED6 0x0006001D 735 #define UDMA_CH29_RESERVED7 0x0007001D 736 #define UDMA_CH29_I2C7TX 0x0008001D 737 738 // 739 // Channel 30 740 // 741 #define UDMA_CH30_SW 0x0000001E 742 #define UDMA_CH30_RESERVED1 0x0001001E 743 #define UDMA_CH30_RESERVED2 0x0002001E 744 #define UDMA_CH30_RESERVED3 0x0003001E 745 #define UDMA_CH30_RESERVED4 0x0004001E 746 #define UDMA_CH30_RESERVED5 0x0005001E 747 #define UDMA_CH30_RESERVED6 0x0006001E 748 #define UDMA_CH30_EPI0RX 0x0007001E 749 #define UDMA_CH30_1WIRE0 0x0008001E 750 751 // 752 // Channel 31 753 // 754 #define UDMA_CH31_RESERVED0 0x0000001F 755 #define UDMA_CH31_RESERVED1 0x0001001F 756 #define UDMA_CH31_RESERVED2 0x0002001F 757 #define UDMA_CH31_LPC0_0 0x0003001F 758 #define UDMA_CH31_RESERVED4 0x0004001F 759 #define UDMA_CH31_RESERVED5 0x0005001F 760 #define UDMA_CH31_RESERVED6 0x0006001F 761 #define UDMA_CH31_EPI0RX 0x0007001F 762 #define UDMA_CH31_RESERVED8 0x0008001F 763 764 //***************************************************************************** 765 // 766 // API Function prototypes 767 // 768 //***************************************************************************** 769 extern void uDMAEnable(void); 770 extern void uDMADisable(void); 771 extern uint32_t uDMAErrorStatusGet(void); 772 extern void uDMAErrorStatusClear(void); 773 extern void uDMAChannelEnable(uint32_t ui32ChannelNum); 774 extern void uDMAChannelDisable(uint32_t ui32ChannelNum); 775 extern bool uDMAChannelIsEnabled(uint32_t ui32ChannelNum); 776 extern void uDMAControlBaseSet(void *pControlTable); 777 extern void *uDMAControlBaseGet(void); 778 extern void *uDMAControlAlternateBaseGet(void); 779 extern void uDMAChannelRequest(uint32_t ui32ChannelNum); 780 extern void uDMAChannelAttributeEnable(uint32_t ui32ChannelNum, 781 uint32_t ui32Attr); 782 extern void uDMAChannelAttributeDisable(uint32_t ui32ChannelNum, 783 uint32_t ui32Attr); 784 extern uint32_t uDMAChannelAttributeGet(uint32_t ui32ChannelNum); 785 extern void uDMAChannelControlSet(uint32_t ui32ChannelStructIndex, 786 uint32_t ui32Control); 787 extern void uDMAChannelTransferSet(uint32_t ui32ChannelStructIndex, 788 uint32_t ui32Mode, void *pvSrcAddr, 789 void *pvDstAddr, uint32_t ui32TransferSize); 790 extern void uDMAChannelScatterGatherSet(uint32_t ui32ChannelNum, 791 uint32_t ui32TaskCount, 792 void *pvTaskList, 793 uint32_t ui32IsPeriphSG); 794 extern uint32_t uDMAChannelSizeGet(uint32_t ui32ChannelStructIndex); 795 extern uint32_t uDMAChannelModeGet(uint32_t ui32ChannelStructIndex); 796 extern void uDMAIntRegister(uint32_t ui32IntChannel, void (*pfnHandler)(void)); 797 extern void uDMAIntUnregister(uint32_t ui32IntChannel); 798 extern uint32_t uDMAIntStatus(void); 799 extern void uDMAIntClear(uint32_t ui32ChanMask); 800 extern void uDMAChannelAssign(uint32_t ui32Mapping); 801 802 //***************************************************************************** 803 // 804 // The following functions and definitions are deprecated and will be removed 805 // from the API in the future. Use uDMAChannelAssign() instead to accomplish 806 // the same end. 807 // 808 //***************************************************************************** 809 #ifndef DEPRECATED 810 //***************************************************************************** 811 // 812 // uDMA default/secondary peripheral selections, to be passed to 813 // uDMAChannelSelectSecondary() and uDMAChannelSelectDefault(). 814 // 815 //***************************************************************************** 816 #define UDMA_DEF_USBEP1RX_SEC_UART2RX \ 817 0x00000001 818 #define UDMA_DEF_USBEP1TX_SEC_UART2TX \ 819 0x00000002 820 #define UDMA_DEF_USBEP2RX_SEC_TMR3A \ 821 0x00000004 822 #define UDMA_DEF_USBEP2TX_SEC_TMR3B \ 823 0x00000008 824 #define UDMA_DEF_USBEP3RX_SEC_TMR2A \ 825 0x00000010 826 #define UDMA_DEF_USBEP3TX_SEC_TMR2B \ 827 0x00000020 828 #define UDMA_DEF_ETH0RX_SEC_TMR2A \ 829 0x00000040 830 #define UDMA_DEF_ETH0TX_SEC_TMR2B \ 831 0x00000080 832 #define UDMA_DEF_UART0RX_SEC_UART1RX \ 833 0x00000100 834 #define UDMA_DEF_UART0TX_SEC_UART1TX \ 835 0x00000200 836 #define UDMA_DEF_SSI0RX_SEC_SSI1RX \ 837 0x00000400 838 #define UDMA_DEF_SSI0TX_SEC_SSI1TX \ 839 0x00000800 840 #define UDMA_DEF_RESERVED_SEC_UART2RX \ 841 0x00001000 842 #define UDMA_DEF_RESERVED_SEC_UART2TX \ 843 0x00002000 844 #define UDMA_DEF_ADC00_SEC_TMR2A \ 845 0x00004000 846 #define UDMA_DEF_ADC01_SEC_TMR2B \ 847 0x00008000 848 #define UDMA_DEF_ADC02_SEC_RESERVED \ 849 0x00010000 850 #define UDMA_DEF_ADC03_SEC_RESERVED \ 851 0x00020000 852 #define UDMA_DEF_TMR0A_SEC_TMR1A \ 853 0x00040000 854 #define UDMA_DEF_TMR0B_SEC_TMR1B \ 855 0x00080000 856 #define UDMA_DEF_TMR1A_SEC_EPI0RX \ 857 0x00100000 858 #define UDMA_DEF_TMR1B_SEC_EPI0TX \ 859 0x00200000 860 #define UDMA_DEF_UART1RX_SEC_RESERVED \ 861 0x00400000 862 #define UDMA_DEF_UART1TX_SEC_RESERVED \ 863 0x00800000 864 #define UDMA_DEF_SSI1RX_SEC_ADC10 \ 865 0x01000000 866 #define UDMA_DEF_SSI1TX_SEC_ADC11 \ 867 0x02000000 868 #define UDMA_DEF_RESERVED_SEC_ADC12 \ 869 0x04000000 870 #define UDMA_DEF_RESERVED_SEC_ADC13 \ 871 0x08000000 872 #define UDMA_DEF_I2S0RX_SEC_RESERVED \ 873 0x10000000 874 #define UDMA_DEF_I2S0TX_SEC_RESERVED \ 875 0x20000000 876 877 extern void uDMAChannelSelectDefault(uint32_t ui32DefPeriphs); 878 extern void uDMAChannelSelectSecondary(uint32_t ui32SecPeriphs); 879 880 #endif 881 //***************************************************************************** 882 // 883 // Mark the end of the C bindings section for C++ compilers. 884 // 885 //***************************************************************************** 886 #ifdef __cplusplus 887 } 888 #endif 889 890 #endif // __DRIVERLIB_UDMA_H__ 891