1 //***************************************************************************** 2 // 3 // emac.h - Defines and Macros for the Ethernet module on Snowflake-class 4 // devices. 5 // 6 // Copyright (c) 2012-2020 Texas Instruments Incorporated. All rights reserved. 7 // Software License Agreement 8 // 9 // Redistribution and use in source and binary forms, with or without 10 // modification, are permitted provided that the following conditions 11 // are met: 12 // 13 // Redistributions of source code must retain the above copyright 14 // notice, this list of conditions and the following disclaimer. 15 // 16 // Redistributions in binary form must reproduce the above copyright 17 // notice, this list of conditions and the following disclaimer in the 18 // documentation and/or other materials provided with the 19 // distribution. 20 // 21 // Neither the name of Texas Instruments Incorporated nor the names of 22 // its contributors may be used to endorse or promote products derived 23 // from this software without specific prior written permission. 24 // 25 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 // 37 // This is part of revision 2.2.0.295 of the Tiva Peripheral Driver Library. 38 // 39 //***************************************************************************** 40 41 #ifndef __DRIVERLIB_EMAC_H__ 42 #define __DRIVERLIB_EMAC_H__ 43 44 //***************************************************************************** 45 // 46 // If building with a C++ compiler, make all of the definitions in this header 47 // have a C binding. 48 // 49 //***************************************************************************** 50 #ifdef __cplusplus 51 extern "C" 52 { 53 #endif 54 55 //***************************************************************************** 56 // 57 //! \addtogroup emac_api 58 //! @{ 59 // 60 //***************************************************************************** 61 62 //***************************************************************************** 63 // 64 // The physical address of the internal PHY. This should be in hw_emac.h. 65 // 66 //***************************************************************************** 67 #define EMAC_PHY_ADDR 0 68 69 //***************************************************************************** 70 // 71 // Helper Macros for Ethernet Processing 72 // 73 //***************************************************************************** 74 // 75 // htonl/ntohl - Big endian/little endian byte swapping macros for 32-bit 76 // values. 77 // 78 //***************************************************************************** 79 #ifndef htonl 80 #define htonl(a) \ 81 ((((a) >> 24) & 0x000000ff) | \ 82 (((a) >> 8) & 0x0000ff00) | \ 83 (((a) << 8) & 0x00ff0000) | \ 84 (((a) << 24) & 0xff000000)) 85 #endif 86 87 #ifndef ntohl 88 #define ntohl(a) htonl((a)) 89 #endif 90 91 //***************************************************************************** 92 // 93 // htons/ntohs - Big endian/little endian byte swapping macros for 16-bit 94 // values. 95 // 96 //***************************************************************************** 97 #ifndef htons 98 #define htons(a) \ 99 ((((a) >> 8) & 0x00ff) | \ 100 (((a) << 8) & 0xff00)) 101 #endif 102 103 #ifndef ntohs 104 #define ntohs(a) htons((a)) 105 #endif 106 107 //***************************************************************************** 108 // 109 // Forward reference to the Ethernet DMA descriptor structure. 110 // 111 //***************************************************************************** 112 typedef struct tEMACDMADescriptor tEMACDMADescriptor; 113 114 //***************************************************************************** 115 // 116 //! A union used to describe the two overlapping fields forming the third 117 //! word of the Ethernet DMA descriptor. 118 // 119 //***************************************************************************** 120 typedef union 121 { 122 // 123 //! When DMA descriptors are used in chained mode, this field is used to 124 //! provide a link to the next descriptor. 125 // 126 tEMACDMADescriptor *pLink; 127 128 // 129 //! When the DMA descriptors are unchained, this field may be used to point 130 //! to a second buffer containing data for transmission or providing 131 //! storage for a received frame. 132 // 133 void *pvBuffer2; 134 } 135 tEMACDES3; 136 137 //***************************************************************************** 138 // 139 //! A structure defining a single Ethernet DMA buffer descriptor. 140 // 141 //***************************************************************************** 142 struct tEMACDMADescriptor 143 { 144 // 145 //! The first DMA descriptor word contains various control and status bits 146 //! depending upon whether the descriptor is in the transmit or receive 147 //! queue. Bit 31 is always the ``OWN'' bit which, when set, indicates 148 //! that the hardware has control of the descriptor. 149 // 150 volatile uint32_t ui32CtrlStatus; 151 152 // 153 //! The second descriptor word contains information on the size of the 154 //! buffer or buffers attached to the descriptor and various additional 155 //! control bits. 156 // 157 volatile uint32_t ui32Count; 158 159 // 160 //! The third descriptor word contains a pointer to the buffer containing 161 //! data to transmit or into which received data should be written. This 162 //! pointer must refer to a buffer in internal SRAM. Pointers to flash or 163 //! EPI-connected memory may not be used and will result in the MAC 164 //! reporting a bus error. 165 // 166 void *pvBuffer1; 167 168 // 169 //! The fourth descriptor word contains either a pointer to the next 170 //! descriptor in the ring or a pointer to a second data buffer. The 171 //! meaning of the word is controlled by the ``CHAINED'' control bit which 172 //! appears in the first word of the transmit descriptor or the second 173 //! word of the receive descriptor. 174 //! 175 tEMACDES3 DES3; 176 177 // 178 //! The fifth descriptor word is reserved for transmit descriptors but 179 //! used to report extended status in a receive descriptor. 180 // 181 volatile uint32_t ui32ExtRxStatus; 182 183 // 184 //! The sixth descriptor word is reserved for both transmit and receive 185 //! descriptors. 186 // 187 uint32_t ui32Reserved; 188 189 // 190 //! The seventh descriptor word contains the low 32 bits of the 64-bit 191 //! timestamp captured for transmitted or received data. The value is set 192 //! only when the transmitted or received data contains the end of a 193 //! packet. Availability of the timestamp is indicated via a status bit 194 //! in the first descriptor word. 195 // 196 volatile uint32_t ui32IEEE1588TimeLo; 197 198 // 199 //! The eighth descriptor word contains the high 32 bits of the 64-bit 200 //! timestamp captured for transmitted or received data. 201 // 202 volatile uint32_t ui32IEEE1588TimeHi; 203 }; 204 205 //***************************************************************************** 206 // 207 // Fields found in the DES0 word of the transmit descriptor (ui32CtrlStatus in 208 // tEMACDMADescriptor) 209 // 210 //***************************************************************************** 211 #define DES0_TX_CTRL_OWN 0x80000000 212 #define DES0_TX_CTRL_INTERRUPT 0x40000000 213 #define DES0_TX_CTRL_LAST_SEG 0x20000000 214 #define DES0_TX_CTRL_FIRST_SEG 0x10000000 215 216 // 217 // This value indicates that the MAC should not append a CRC to transmitted 218 // packets. If used with DES0_TX_CTRL_REPLACE_CRC, the last 4 bytes of the 219 // packet passed to the transmitter are replaced with a newly calculated CRC. 220 // If DES0_TX_CTRL_REPLACE_CRC is not specified, it is assumed that packets 221 // transmitted have valid CRCs precomputed and included in the frame data. 222 // 223 // If DES0_TX_CTRL_DISABLE_CRC is not specified, the MAC will calculate the 224 // CRC for all frames transmitted and append this value as the 4-byte FCS 225 // after the last data byte in the frame. 226 // 227 #define DES0_TX_CTRL_DISABLE_CRC 0x08000000 228 #define DES0_TX_CTRL_DISABLE_PADDING 0x04000000 229 #define DES0_TX_CTRL_ENABLE_TS 0x02000000 230 231 // 232 // This value is only valid if used alongside DES0_TX_CTRL_DISABLE_CRC. When 233 // specified, the MAC will replace the last 4 bytes of a transmitted frame 234 // with a newly calculated CRC. 235 // 236 #define DES0_TX_CTRL_REPLACE_CRC 0x01000000 237 #define DES0_TX_CTRL_CHKSUM_M 0x00C00000 238 #define DES0_TX_CTRL_NO_CHKSUM 0x00000000 239 #define DES0_TX_CTRL_IP_HDR_CHKSUM 0x00400000 240 #define DES0_TX_CTRL_IP_HDR_PAY_CHKSUM 0x00800000 241 #define DES0_TX_CTRL_IP_ALL_CKHSUMS 0x00C00000 242 #define DES0_TX_CTRL_END_OF_RING 0x00200000 243 #define DES0_TX_CTRL_CHAINED 0x00100000 244 #define DES0_TX_CTRL_VLAN_M 0x000C0000 245 #define DES0_TX_CTRL_VLAN_NONE 0x00000000 246 #define DES0_TX_CTRL_VLAN_REMOVE 0x00040000 247 #define DES0_TX_CTRL_VLAN_INSERT 0x00080000 248 #define DES0_TX_CTRL_VLAN_REPLACE 0x000C0000 249 #define DES0_TX_STAT_TS_CAPTURED 0x00020000 250 #define DES0_TX_STAT_IPH_ERR 0x00010000 251 #define DES0_TX_STAT_ERR 0x00008000 252 #define DES0_TX_STAT_JABBER_TO 0x00004000 253 #define DES0_TX_STAT_FLUSHED 0x00002000 254 #define DES0_TX_STAT_PAYLOAD_ERR 0x00001000 255 #define DES0_TX_STAT_CARRIER_LOST 0x00000800 256 #define DES0_TX_STAT_NO_CARRIER 0x00000400 257 #define DES0_TX_STAT_TX_L_COLLISION 0x00000200 258 #define DES0_TX_STAT_E_COLLISION 0x00000100 259 #define DES0_TX_STAT_VLAN_FRAME 0x00000080 260 #define DES0_TX_STAT_COL_COUNT_M 0x00000078 261 #define DES0_TX_STAT_COL_COUNT_S 3 262 #define DES0_TX_STAT_E_DEFERRAL 0x00000004 263 #define DES0_TX_STAT_UNDERFLOW 0x00000002 264 #define DES0_TX_STAT_DEFERRED 0x00000001 265 266 //***************************************************************************** 267 // 268 // Fields found in the DES1 word of the transmit descriptor (ui32Count in 269 // tEMACDMADescriptor) 270 // 271 //***************************************************************************** 272 #define DES1_TX_CTRL_SADDR_MAC1 0x80000000 273 #define DES1_TX_CTRL_SADDR_M 0x60000000 274 #define DES1_TX_CTRL_SADDR_NONE 0x00000000 275 #define DES1_TX_CTRL_SADDR_INSERT 0x20000000 276 #define DES1_TX_CTRL_SADDR_REPLACE 0x40000000 277 #define DES1_TX_CTRL_BUFF2_SIZE_M 0x1FFF0000 278 #define DES1_TX_CTRL_BUFF1_SIZE_M 0x00001FFF 279 #define DES1_TX_CTRL_BUFF2_SIZE_S 16 280 #define DES1_TX_CTRL_BUFF1_SIZE_S 0 281 282 //***************************************************************************** 283 // 284 // Fields found in the DES0 word of the receive descriptor (ui32CtrlStatus in 285 // tEMACDMADescriptor) 286 // 287 //***************************************************************************** 288 #define DES0_RX_CTRL_OWN 0x80000000 289 #define DES0_RX_STAT_DEST_ADDR_FAIL 0x40000000 290 #define DES0_RX_STAT_FRAME_LENGTH_M 0x3FFF0000 291 #define DES0_RX_STAT_FRAME_LENGTH_S 16 292 #define DES0_RX_STAT_ERR 0x00008000 293 #define DES0_RX_STAT_DESCRIPTOR_ERR 0x00004000 294 #define DES0_RX_STAT_SRC_ADDR_FAIL 0x00002000 295 #define DES0_RX_STAT_LENGTH_ERR 0x00001000 296 #define DES0_RX_STAT_OVERFLOW 0x00000800 297 #define DES0_RX_STAT_VLAN_TAG 0x00000400 298 #define DES0_RX_STAT_FIRST_DESC 0x00000200 299 #define DES0_RX_STAT_LAST_DESC 0x00000100 300 #define DES0_RX_STAT_TS_AVAILABLE 0x00000080 301 #define DES0_RX_STAT_RX_L_COLLISION 0x00000040 302 #define DES0_RX_STAT_FRAME_TYPE 0x00000020 303 #define DES0_RX_STAT_WDOG_TIMEOUT 0x00000010 304 #define DES0_RX_STAT_RX_ERR 0x00000008 305 #define DES0_RX_STAT_DRIBBLE_ERR 0x00000004 306 #define DES0_RX_STAT_CRC_ERR 0x00000002 307 #define DES0_RX_STAT_MAC_ADDR 0x00000001 308 #define DES0_RX_STAT_EXT_AVAILABLE 0x00000001 309 310 //***************************************************************************** 311 // 312 // Fields found in the DES1 word of the receive descriptor (ui32Count in 313 // tEMACDMADescriptor) 314 // 315 //***************************************************************************** 316 #define DES1_RX_CTRL_DISABLE_INT 0x80000000 317 #define DES1_RX_CTRL_BUFF2_SIZE_M 0x1FFF0000 318 #define DES1_RX_CTRL_BUFF2_SIZE_S 16 319 #define DES1_RX_CTRL_END_OF_RING 0x00008000 320 #define DES1_RX_CTRL_CHAINED 0x00004000 321 #define DES1_RX_CTRL_BUFF1_SIZE_M 0x00001FFF 322 #define DES1_RX_CTRL_BUFF1_SIZE_S 0 323 324 //***************************************************************************** 325 // 326 // Fields found in the DES4 word of the receive descriptor (ui32ExtRxStatus in 327 // tEMACDMADescriptor) 328 // 329 //***************************************************************************** 330 #define DES4_RX_STAT_TS_DROPPED 0x00004000 331 #define DES4_RX_STAT_PTP_VERSION2 0x00002000 332 #define DES4_RX_STAT_PTP_TYPE_ETH 0x00001000 333 #define DES4_RX_STAT_PTP_TYPE_UDP 0x00000000 334 #define DES4_RX_STAT_PTP_MT_M 0x00000F00 335 #define DES4_RX_STAT_PTP_MT_NONE 0x00000000 336 #define DES4_RX_STAT_PTP_MT_SYNC 0x00000100 337 #define DES4_RX_STAT_PTP_MT_FOLLOW_UP 0x00000200 338 #define DES4_RX_STAT_PTP_MT_DELAY_REQ 0x00000300 339 #define DES4_RX_STAT_PTP_MT_DELAY_RESP 0x00000400 340 #define DES4_RX_STAT_PTP_MT_PDELAY_REQ 0x00000500 341 #define DES4_RX_STAT_PTP_MT_PDELAY_RESP 0x00000600 342 #define DES4_RX_STAT_PTP_MT_PDELAY_RFU 0x00000700 343 #define DES4_RX_STAT_PTP_MT_ANNOUNCE 0x00000800 344 #define DES4_RX_STAT_PTP_MT_SIGNALLING 0x00000A00 345 #define DES4_RX_STAT_PTP_MT_RESERVED 0x00000F00 346 #define DES4_RX_STAT_IPV6 0x00000080 347 #define DES4_RX_STAT_IPV4 0x00000040 348 #define DES4_RX_STAT_IP_CHK_BYPASSED 0x00000020 349 #define DES4_RX_STAT_IP_PAYLOAD_ERR 0x00000010 350 #define DES4_RX_STAT_IP_HEADER_ERR 0x00000008 351 #define DES4_RX_STAT_PAYLOAD_M 0x00000007 352 #define DES4_RX_STAT_PAYLOAD_UNKNOWN 0x00000000 353 #define DES4_RX_STAT_PAYLOAD_UDP 0x00000001 354 #define DES4_RX_STAT_PAYLOAD_TCP 0x00000002 355 #define DES4_RX_STAT_PAYLOAD_ICMP 0x00000003 356 357 //***************************************************************************** 358 // 359 // Values used in the ui32BusConfig parameter to EMACInit(). 360 // 361 //*************************************************************************** 362 #define EMAC_BCONFIG_DMA_PRIO_WEIGHT_M 0x30000000 363 #define EMAC_BCONFIG_DMA_PRIO_WEIGHT_1 0x00000000 364 #define EMAC_BCONFIG_DMA_PRIO_WEIGHT_2 0x10000000 365 #define EMAC_BCONFIG_DMA_PRIO_WEIGHT_3 0x20000000 366 #define EMAC_BCONFIG_DMA_PRIO_WEIGHT_4 0x30000000 367 #define EMAC_BCONFIG_TX_PRIORITY 0x08000000 368 #define EMAC_BCONFIG_ADDR_ALIGNED 0x02000000 369 #define EMAC_BCONFIG_PRIORITY_M 0x0000C000 370 #define EMAC_BCONFIG_PRIORITY_1_1 (0 << 14) 371 #define EMAC_BCONFIG_PRIORITY_2_1 (1 << 14) 372 #define EMAC_BCONFIG_PRIORITY_3_1 (2 << 14) 373 #define EMAC_BCONFIG_PRIORITY_4_1 (3 << 14) 374 #define EMAC_BCONFIG_PRIORITY_FIXED 0x00000002 375 #define EMAC_BCONFIG_FIXED_BURST 0x00010000 376 #define EMAC_BCONFIG_MIXED_BURST 0x04000000 377 378 //***************************************************************************** 379 // 380 // Options used in the ui32Config parameter to EMACPHYConfigSet(). 381 // 382 //***************************************************************************** 383 #define EMAC_PHY_TYPE_INTERNAL 0x00000000 384 #define EMAC_PHY_TYPE_EXTERNAL_MII 0x80000000 385 #define EMAC_PHY_TYPE_EXTERNAL_RMII 0xC0000000 386 #define EMAC_PHY_INT_NIB_TXERR_DET_DIS 0x01000000 387 #define EMAC_PHY_INT_RX_ER_DURING_IDLE 0x00800000 388 #define EMAC_PHY_INT_ISOLATE_MII_LLOSS 0x00400000 389 #define EMAC_PHY_INT_LINK_LOSS_RECOVERY 0x00200000 390 #define EMAC_PHY_INT_TDRRUN 0x00100000 391 #define EMAC_PHY_INT_LD_ON_RX_ERR_COUNT 0x00040000 392 #define EMAC_PHY_INT_LD_ON_MTL3_ERR_COUNT 0x00020000 393 #define EMAC_PHY_INT_LD_ON_LOW_SNR 0x00010000 394 #define EMAC_PHY_INT_LD_ON_SIGNAL_ENERGY 0x00008000 395 #define EMAC_PHY_INT_POLARITY_SWAP 0x00004000 396 #define EMAC_PHY_INT_MDI_SWAP 0x00002000 397 #define EMAC_PHY_INT_ROBUST_MDIX 0x00001000 398 #define EMAC_PHY_INT_FAST_MDIX 0x00000800 399 #define EMAC_PHY_INT_MDIX_EN 0x00000400 400 #define EMAC_PHY_INT_FAST_RXDV_DETECT 0x00000200 401 #define EMAC_PHY_INT_FAST_L_UP_DETECT 0x00000100 402 #define EMAC_PHY_INT_EXT_FULL_DUPLEX 0x00000080 403 #define EMAC_PHY_INT_FAST_AN_80_50_35 0x00000040 404 #define EMAC_PHY_INT_FAST_AN_120_75_50 0x00000050 405 #define EMAC_PHY_INT_FAST_AN_140_150_100 0x00000060 406 #define EMAC_PHY_FORCE_10B_T_HALF_DUPLEX 0x00000000 407 #define EMAC_PHY_FORCE_10B_T_FULL_DUPLEX 0x00000002 408 #define EMAC_PHY_FORCE_100B_T_HALF_DUPLEX 0x00000004 409 #define EMAC_PHY_FORCE_100B_T_FULL_DUPLEX 0x00000006 410 #define EMAC_PHY_AN_10B_T_HALF_DUPLEX 0x00000008 411 #define EMAC_PHY_AN_10B_T_FULL_DUPLEX 0x0000000A 412 #define EMAC_PHY_AN_100B_T_HALF_DUPLEX 0x0000000C 413 #define EMAC_PHY_AN_100B_T_FULL_DUPLEX 0x0000000E 414 #define EMAC_PHY_INT_HOLD 0x00000001 415 416 #define EMAC_PHY_TYPE_MASK 0xC0000000 417 418 //***************************************************************************** 419 // 420 // Options used in the ui32Config parameter to EMACConfigSet(). 421 // 422 //***************************************************************************** 423 #define EMAC_CONFIG_USE_MACADDR1 0x40000000 424 #define EMAC_CONFIG_USE_MACADDR0 0x00000000 425 #define EMAC_CONFIG_SA_FROM_DESCRIPTOR 0x00000000 426 #define EMAC_CONFIG_SA_INSERT 0x20000000 427 #define EMAC_CONFIG_SA_REPLACE 0x30000000 428 #define EMAC_CONFIG_2K_PACKETS 0x08000000 429 #define EMAC_CONFIG_STRIP_CRC 0x02000000 430 #define EMAC_CONFIG_JABBER_DISABLE 0x00400000 431 #define EMAC_CONFIG_JUMBO_ENABLE 0x00100000 432 #define EMAC_CONFIG_IF_GAP_MASK 0x000E0000 433 #define EMAC_CONFIG_IF_GAP_96BITS (0x0 << 17) 434 #define EMAC_CONFIG_IF_GAP_88BITS (0x1 << 17) 435 #define EMAC_CONFIG_IF_GAP_80BITS (0x2 << 17) 436 #define EMAC_CONFIG_IF_GAP_72BITS (0x3 << 17) 437 #define EMAC_CONFIG_IF_GAP_64BITS (0x4 << 17) 438 #define EMAC_CONFIG_IF_GAP_56BITS (0x5 << 17) 439 #define EMAC_CONFIG_IF_GAP_48BITS (0x6 << 17) 440 #define EMAC_CONFIG_IF_GAP_40BITS (0x7 << 17) 441 #define EMAC_CONFIG_CS_DISABLE 0x00010000 442 #define EMAC_CONFIG_100MBPS 0x00004000 443 #define EMAC_CONFIG_10MBPS 0x00000000 444 #define EMAC_CONFIG_RX_OWN_DISABLE 0x00002000 445 #define EMAC_CONFIG_LOOPBACK 0x00001000 446 #define EMAC_CONFIG_FULL_DUPLEX 0x00000800 447 #define EMAC_CONFIG_HALF_DUPLEX 0x00000000 448 #define EMAC_CONFIG_CHECKSUM_OFFLOAD 0x00000400 449 #define EMAC_CONFIG_RETRY_DISABLE 0x00000200 450 #define EMAC_CONFIG_AUTO_CRC_STRIPPING 0x00000080 451 #define EMAC_CONFIG_BO_MASK 0x00000060 452 #define EMAC_CONFIG_BO_LIMIT_1024 (0x0 << 5) 453 #define EMAC_CONFIG_BO_LIMIT_256 (0x1 << 5) 454 #define EMAC_CONFIG_BO_LIMIT_16 (0x2 << 5) 455 #define EMAC_CONFIG_BO_LIMIT_2 (0x3 << 5) 456 #define EMAC_CONFIG_DEFERRAL_CHK_ENABLE 0x00000010 457 #define EMAC_CONFIG_PREAMBLE_MASK 0x00000003 458 #define EMAC_CONFIG_7BYTE_PREAMBLE 0x00000000 459 #define EMAC_CONFIG_5BYTE_PREAMBLE 0x00000001 460 #define EMAC_CONFIG_3BYTE_PREAMBLE 0x00000002 461 462 //***************************************************************************** 463 // 464 // Options used in the ui32ModeFlags parameter to EMACConfigSet(). 465 // 466 //***************************************************************************** 467 #define EMAC_MODE_KEEP_BAD_CRC 0x04000000 468 #define EMAC_MODE_RX_STORE_FORWARD 0x02000000 469 #define EMAC_MODE_RX_FLUSH_DISABLE 0x01000000 470 #define EMAC_MODE_TX_STORE_FORWARD 0x00200000 471 #define EMAC_MODE_TX_THRESHOLD_16_BYTES (7 << 14) 472 #define EMAC_MODE_TX_THRESHOLD_24_BYTES (6 << 14) 473 #define EMAC_MODE_TX_THRESHOLD_32_BYTES (5 << 14) 474 #define EMAC_MODE_TX_THRESHOLD_40_BYTES (4 << 14) 475 #define EMAC_MODE_TX_THRESHOLD_64_BYTES (0 << 14) 476 #define EMAC_MODE_TX_THRESHOLD_128_BYTES (1 << 14) 477 #define EMAC_MODE_TX_THRESHOLD_192_BYTES (2 << 14) 478 #define EMAC_MODE_TX_THRESHOLD_256_BYTES (3 << 14) 479 #define EMAC_MODE_RX_ERROR_FRAMES 0x00000080 480 #define EMAC_MODE_RX_UNDERSIZED_FRAMES 0x00000040 481 #define EMAC_MODE_RX_THRESHOLD_64_BYTES (0 << 3) 482 #define EMAC_MODE_RX_THRESHOLD_32_BYTES (1 << 3) 483 #define EMAC_MODE_RX_THRESHOLD_96_BYTES (2 << 3) 484 #define EMAC_MODE_RX_THRESHOLD_128_BYTES (3 << 3) 485 #define EMAC_MODE_OPERATE_2ND_FRAME 0x00000002 486 487 //***************************************************************************** 488 // 489 // These two values may be returned by EMACConfigGet() in the *pui32Config 490 // parameter. The transmitter and receiver are, however, enabled and disabled 491 // using independent functions, EMACTxEnable/Disable() and 492 // EMACRxEnable/Disable(). 493 // 494 //***************************************************************************** 495 #define EMAC_CONFIG_TX_ENABLED 0x00000008 496 #define EMAC_CONFIG_RX_ENABLED 0x00000004 497 498 //***************************************************************************** 499 // 500 // These two values may be returned by EMACConfigGet() in the *pui32Mode 501 // parameter. The transmit and receive DMA channels are, however, enabled and 502 // disabled using independent functions, EMACTxEnable/Disable() and 503 // EMACRxEnable/Disable(). 504 // 505 //***************************************************************************** 506 #define EMAC_MODE_TX_DMA_ENABLED 0x00002000 507 #define EMAC_MODE_RX_DMA_ENABLED 0x00000002 508 509 //***************************************************************************** 510 // 511 // These values may be passed to EMACFrameFilterSet() in the ui32FilterOpts 512 // parameter, and are returned by EMACFrameFilterGet(). 513 // 514 //***************************************************************************** 515 #define EMAC_FRMFILTER_RX_ALL 0x80000000 516 #define EMAC_FRMFILTER_VLAN 0x00010000 517 #define EMAC_FRMFILTER_HASH_AND_PERFECT 0x00000400 518 #define EMAC_FRMFILTER_SADDR 0x00000200 519 #define EMAC_FRMFILTER_INV_SADDR 0x00000100 520 #define EMAC_FRMFILTER_PASS_MASK (0x03 << 6) 521 #define EMAC_FRMFILTER_PASS_NO_CTRL (0x00 << 6) 522 #define EMAC_FRMFILTER_PASS_NO_PAUSE (0x01 << 6) 523 #define EMAC_FRMFILTER_PASS_ALL_CTRL (0x02 << 6) 524 #define EMAC_FRMFILTER_PASS_ADDR_CTRL (0x03 << 6) 525 #define EMAC_FRMFILTER_BROADCAST 0x00000020 526 #define EMAC_FRMFILTER_PASS_MULTICAST 0x00000010 527 #define EMAC_FRMFILTER_INV_DADDR 0x00000008 528 #define EMAC_FRMFILTER_HASH_MULTICAST 0x00000004 529 #define EMAC_FRMFILTER_HASH_UNICAST 0x00000002 530 #define EMAC_FRMFILTER_PROMISCUOUS 0x00000001 531 532 //***************************************************************************** 533 // 534 // Values which may be returned by EMACStatusGet(). 535 // 536 //***************************************************************************** 537 #define EMAC_STATUS_TX_NOT_EMPTY 0x01000000 538 #define EMAC_STATUS_TX_WRITING_FIFO 0x00400000 539 #define EMAC_STATUS_TRC_STATE_MASK 0x00300000 540 #define EMAC_STATUS_TRC_STATE_IDLE (0x00 << 20) 541 #define EMAC_STATUS_TRC_STATE_READING (0x01 << 20) 542 #define EMAC_STATUS_TRC_STATE_WAITING (0x02 << 20) 543 #define EMAC_STATUS_TRC_STATE_STATUS (0x03 << 20) 544 #define EMAC_STATUS_TX_PAUSED 0x00080000 545 #define EMAC_STATUS_TFC_STATE_MASK 0x00060000 546 #define EMAC_STATUS_TFC_STATE_IDLE (0x00 << 17) 547 #define EMAC_STATUS_TFC_STATE_WAITING (0x01 << 17) 548 #define EMAC_STATUS_TFC_STATE_PAUSING (0x02 << 17) 549 #define EMAC_STATUS_TFC_STATE_WRITING (0x03 << 17) 550 #define EMAC_STATUS_MAC_NOT_IDLE 0x00010000 551 #define EMAC_STATUS_RX_FIFO_LEVEL_MASK 0x00000300 552 #define EMAC_STATUS_RX_FIFO_EMPTY (0x00 << 8) 553 #define EMAC_STATUS_RX_FIFO_BELOW (0x01 << 8) 554 #define EMAC_STATUS_RX_FIFO_ABOVE (0x02 << 8) 555 #define EMAC_STATUS_RX_FIFO_FULL (0x03 << 8) 556 #define EMAC_STATUS_RX_FIFO_STATE_MASK 0x00000060 557 #define EMAC_STATUS_RX_FIFO_IDLE (0x00 << 5) 558 #define EMAC_STATUS_RX_FIFO_READING (0x01 << 5) 559 #define EMAC_STATUS_RX_FIFO_STATUS (0x02 << 5) 560 #define EMAC_STATUS_RX_FIFO_FLUSHING (0x03 << 5) 561 #define EMAC_STATUS_RWC_ACTIVE 0x00000010 562 #define EMAC_STATUS_RPE_ACTIVE 0x00000001 563 564 //***************************************************************************** 565 // 566 // Values which may be returned by EMACDMAStateGet(). 567 // 568 //***************************************************************************** 569 #define EMAC_DMA_TXSTAT_MASK (0x07 << 20) 570 #define EMAC_DMA_TXSTAT_STOPPED (0x00 << 20) 571 #define EMAC_DMA_TXSTAT_RUN_FETCH_DESC (0x01 << 20) 572 #define EMAC_DMA_TXSTAT_RUN_WAIT_STATUS (0x02 << 20) 573 #define EMAC_DMA_TXSTAT_RUN_READING (0x03 << 20) 574 #define EMAC_DMA_TXSTAT_RUN_CLOSE_DESC (0x07 << 20) 575 #define EMAC_DMA_TXSTAT_TS_WRITE (0x04 << 20) 576 #define EMAC_DMA_TXSTAT_SUSPENDED (0x06 << 20) 577 578 #define EMAC_DMA_RXSTAT_MASK (0x07 << 17) 579 #define EMAC_DMA_RXSTAT_STOPPED (0x00 << 17) 580 #define EMAC_DMA_RXSTAT_RUN_FETCH_DESC (0x01 << 17) 581 #define EMAC_DMA_RXSTAT_RUN_WAIT_PACKET (0x03 << 17) 582 #define EMAC_DMA_RXSTAT_SUSPENDED (0x04 << 17) 583 #define EMAC_DMA_RXSTAT_RUN_CLOSE_DESC (0x05 << 17) 584 #define EMAC_DMA_RXSTAT_TS_WRITE (0x06 << 17) 585 #define EMAC_DMA_RXSTAT_RUN_RECEIVING (0x07 << 17) 586 587 #define EMAC_TX_DMA_STATE(x) ((x) & EMAC_DMA_TXSTAT_MASK) 588 #define EMAC_RX_DMA_STATE(x) ((x) & EMAC_DMA_RXSTAT_MASK) 589 590 #define EMAC_DMA_ERROR 0x00002000 591 #define EMAC_DMA_ERR_MASK 0x03800000 592 #define EMAC_DMA_ERR_RX_DATA_WRITE 0x00000000 593 #define EMAC_DMA_ERR_TX_DATA_READ 0x01800000 594 #define EMAC_DMA_ERR_RX_DESC_WRITE 0x02000000 595 #define EMAC_DMA_ERR_TX_DESC_WRITE 0x02800000 596 #define EMAC_DMA_ERR_RX_DESC_READ 0x03000000 597 #define EMAC_DMA_ERR_TX_DESC_READ 0x03800000 598 599 //***************************************************************************** 600 // 601 // Values which may be ORed together in the ui32Config parameter passed to 602 // EMACAddrFilterSet and which may be returned by EMACAddrFilterGet. 603 // 604 //***************************************************************************** 605 #define EMAC_FILTER_ADDR_ENABLE 0x80000000 606 #define EMAC_FILTER_SOURCE_ADDR 0x40000000 607 #define EMAC_FILTER_MASK_BYTE_6 0x20000000 608 #define EMAC_FILTER_MASK_BYTE_5 0x10000000 609 #define EMAC_FILTER_MASK_BYTE_4 0x08000000 610 #define EMAC_FILTER_MASK_BYTE_3 0x04000000 611 #define EMAC_FILTER_MASK_BYTE_2 0x03000000 612 #define EMAC_FILTER_MASK_BYTE_1 0x01000000 613 614 #define EMAC_FILTER_BYTE_MASK_M 0x3F000000 615 #define EMAC_FILTER_BYTE_MASK_S 24 616 617 //***************************************************************************** 618 // 619 // Flags passed to EMACTimestampConfigSet or returned from 620 // EMACTimestampConfigGet. 621 // 622 //***************************************************************************** 623 #define EMAC_TS_MAC_FILTER_ENABLE 0x00040000 624 #define EMAC_TS_MAC_FILTER_DISABLE 0x00000000 625 #define EMAC_TS_SYNC_FOLLOW_DREQ_DRESP 0x00000000 626 #define EMAC_TS_SYNC_ONLY 0x00004000 627 #define EMAC_TS_DELAYREQ_ONLY 0x0000C000 628 #define EMAC_TS_ALL 0x00010000 629 #define EMAC_TS_SYNC_PDREQ_PDRESP 0x00014000 630 #define EMAC_TS_DREQ_PDREQ_PDRESP 0x0001C000 631 #define EMAC_TS_SYNC_DELAYREQ 0x00020000 632 #define EMAC_TS_PDREQ_PDRESP 0x00030000 633 #define EMAC_TS_PROCESS_IPV4_UDP 0x00002000 634 #define EMAC_TS_PROCESS_IPV6_UDP 0x00001000 635 #define EMAC_TS_PROCESS_ETHERNET 0x00000800 636 #define EMAC_TS_PTP_VERSION_2 0x00000400 637 #define EMAC_TS_PTP_VERSION_1 0x00000000 638 #define EMAC_TS_DIGITAL_ROLLOVER 0x00000200 639 #define EMAC_TS_BINARY_ROLLOVER 0x00000000 640 #define EMAC_TS_ALL_RX_FRAMES 0x00000100 641 #define EMAC_TS_UPDATE_FINE 0x00000002 642 #define EMAC_TS_UPDATE_COARSE 0x00000000 643 644 //***************************************************************************** 645 // 646 // Some register bit definitions relating to external PHYs. These are not 647 // relevant (or available) when using the internal Ethernet PHY but having 648 // the definitions here helps when using an external MII or RMII PHY. 649 // 650 //***************************************************************************** 651 #define EPHY_SCR_INPOL_EXT 0x00000008 652 #define EPHY_SCR_TINT_EXT 0x00000004 653 #define EPHY_SCR_INTEN_EXT 0x00000002 654 #define EPHY_SCR_INTOE_EXT 0x00000001 655 656 //***************************************************************************** 657 // 658 // These interrupt sources may be passed to EMACIntEnable() and 659 // EMACIntDisable() to enable or disable various Ethernet interrupt sources. 660 // 661 //***************************************************************************** 662 // 663 // Note that interrupts relating to timestamping and power management must be 664 // independently enabled via calls to functions EMACTimestampTargetIntEnable 665 // and EMACPowerManagementControlSet. 666 // 667 // EMAC_INT_PHY is deliberately set to a reserved bit in the MAC interrupt 668 // register. We handle the fact that the PHY interrupt is controlled via an 669 // independent register within the code. If we didn't do this, the app would 670 // have to enable the MAC interrupt then enable the PHY interrupt via a 671 // different API (since they share a vector). To further complicate matters, 672 // they would have to call EMACIntStatus() and then, if it returned 0, 673 // read the PHY interrupt status to see that it fired. This would be nasty 674 // and unfriendly so we hide it inside DriverLib. 675 // 676 //***************************************************************************** 677 #define EMAC_INT_PHY 0x80000000 678 #define EMAC_INT_EARLY_RECEIVE 0x00004000 679 #define EMAC_INT_BUS_ERROR 0x00002000 680 #define EMAC_INT_EARLY_TRANSMIT 0x00000400 681 #define EMAC_INT_RX_WATCHDOG 0x00000200 682 #define EMAC_INT_RX_STOPPED 0x00000100 683 #define EMAC_INT_RX_NO_BUFFER 0x00000080 684 #define EMAC_INT_RECEIVE 0x00000040 685 #define EMAC_INT_TX_UNDERFLOW 0x00000020 686 #define EMAC_INT_RX_OVERFLOW 0x00000010 687 #define EMAC_INT_TX_JABBER 0x00000008 688 #define EMAC_INT_TX_NO_BUFFER 0x00000004 689 #define EMAC_INT_TX_STOPPED 0x00000002 690 #define EMAC_INT_TRANSMIT 0x00000001 691 692 // 693 // These interrupt sources are summary indicators. They are readable 694 // using EMACIntStatus() and must be cleared using EMACIntClear(). They 695 // may be enabled or disabled independently of the group of interrupts that 696 // they are derived from but offer merely a simple way to be informed of a 697 // normal or abnormal condition requiring software attention. 698 // 699 // EMAC_INT_NORMAL_INT is the logical OR of the masked state of 700 // EMAC_INT_TRANSMIT | EMAC_INT_RECEIVE | EMAC_INT_TX_NO_BUFFER | 701 // EMAC_INT_EARLY_RECEIVE. 702 // 703 // EMAC_INT_ABNORMAL_INT is the logical OR of the masked state of 704 // EMAC_INT_TX_STOPPED | EMAC_INT_TX_JABBER | EMAC_INT_RX_OVERFLOW | 705 // EMAC_INT_TX_UNDERFLOW | EMAC_INT_RX_NO_BUFFER | EMAC_INT_RX_STOPPED | 706 // EMAC_INT_RX_WATCHDOG | EMAC_INT_EARLY_TRANSMIT | EMAC_INT_BUS_ERROR. 707 // 708 #define EMAC_INT_NORMAL_INT 0x00010000 709 #define EMAC_INT_ABNORMAL_INT 0x00008000 710 711 // 712 // This interrupt source is readable using EMACIntStatus but must 713 // be cleared by calling the EMACEEEStatus(). 714 // 715 #define EMAC_INT_LPI 0x40000000 716 717 // 718 // This interrupt source is readable using EMACIntStatus but must 719 // be cleared by calling the EMACTimestampIntStatus(). 720 // 721 #define EMAC_INT_TIMESTAMP 0x20000000 722 723 // 724 // Interrupt sources which may be returned from EMACTimestampIntStatus(). 725 // 726 #define EMAC_TS_INT_TARGET_REACHED 0x00000002 727 #define EMAC_TS_INT_TS_SEC_OVERFLOW 0x00000001 728 729 // 730 // This interrupt source is readable using EMACIntStatus but must 731 // be cleared by calling EMACPowerManagementStatusGet(). 732 // 733 #define EMAC_INT_POWER_MGMNT 0x10000000 734 735 //***************************************************************************** 736 // 737 // Configuration flags that may be passed in the ui32FreqConfig parameter to 738 // EMACTimestampPPSSimpleModeSet(). 739 // 740 //***************************************************************************** 741 #define EMAC_PPS_SINGLE_PULSE 0x00000000 742 #define EMAC_PPS_1HZ 0x00000001 743 #define EMAC_PPS_2HZ 0x00000002 744 #define EMAC_PPS_4HZ 0x00000003 745 #define EMAC_PPS_8HZ 0x00000004 746 #define EMAC_PPS_16HZ 0x00000005 747 #define EMAC_PPS_32HZ 0x00000006 748 #define EMAC_PPS_64HZ 0x00000007 749 #define EMAC_PPS_128HZ 0x00000008 750 #define EMAC_PPS_256HZ 0x00000009 751 #define EMAC_PPS_512HZ 0x0000000A 752 #define EMAC_PPS_1024HZ 0x0000000B 753 #define EMAC_PPS_2048HZ 0x0000000C 754 #define EMAC_PPS_4096HZ 0x0000000D 755 #define EMAC_PPS_8192HZ 0x0000000E 756 #define EMAC_PPS_16384HZ 0x0000000F 757 #define EMAC_PPS_32768HZ 0x00000010 758 759 //***************************************************************************** 760 // 761 // Configuration flags that may be passed in the ui32Config parameter to 762 // EMACTimestampPPSCommandModeSet(). 763 // 764 //***************************************************************************** 765 #define EMAC_PPS_TARGET_INT 0x00000000 766 #define EMAC_PPS_TARGET_PPS 0x00000060 767 #define EMAC_PPS_TARGET_BOTH 0x00000040 768 769 //***************************************************************************** 770 // 771 // Commands which may be passed to EMACTimestampPPSCmd. 772 // 773 //***************************************************************************** 774 #define EMAC_PPS_COMMAND_NONE 0x00 775 #define EMAC_PPS_COMMAND_START_SINGLE 0x01 776 #define EMAC_PPS_COMMAND_START_TRAIN 0x02 777 #define EMAC_PPS_COMMAND_CANCEL_START 0x03 778 #define EMAC_PPS_COMMAND_STOP_AT_TIME 0x04 779 #define EMAC_PPS_COMMAND_STOP_NOW 0x05 780 #define EMAC_PPS_COMMAND_CANCEL_STOP 0x06 781 782 //***************************************************************************** 783 // 784 // Values which may be passed to EMACVLANRxConfigSet in the ui32Config 785 // parameter and which may be returned from EMACVLANRxConfigGet. 786 // 787 //***************************************************************************** 788 #define EMAC_VLAN_RX_HASH_ENABLE 0x00080000 789 #define EMAC_VLAN_RX_HASH_DISABLE 0x00000000 790 #define EMAC_VLAN_RX_SVLAN_ENABLE 0x00040000 791 #define EMAC_VLAN_RX_SVLAN_DISABLE 0x00000000 792 #define EMAC_VLAN_RX_NORMAL_MATCH 0x00000000 793 #define EMAC_VLAN_RX_INVERSE_MATCH 0x00020000 794 #define EMAC_VLAN_RX_12BIT_TAG 0x00010000 795 #define EMAC_VLAN_RX_16BIT_TAG 0x00000000 796 797 //***************************************************************************** 798 // 799 // Values which may be passed to EMACVLANTxConfigSet in the ui32Config 800 // parameter and which may be returned from EMACVLANTxConfigGet. 801 // 802 //***************************************************************************** 803 #define EMAC_VLAN_TX_CVLAN 0x00000000 804 #define EMAC_VLAN_TX_SVLAN 0x00080000 805 #define EMAC_VLAN_TX_USE_VLC 0x00040000 806 #define EMAC_VLAN_TX_VLC_NONE 0x00000000 807 #define EMAC_VLAN_TX_VLC_DELETE 0x00010000 808 #define EMAC_VLAN_TX_VLC_INSERT 0x00020000 809 #define EMAC_VLAN_TX_VLC_REPLACE 0x00030000 810 811 #define EMAC_VLAN_TX_VLC_MASK 0x00030000 812 813 #define EMAC_RWU_FILTER_ENABLE 1 814 #define EMAC_RWU_FILTER_DISABLE 0 815 #define EMAC_RWU_FILTER_MULTICAST 8 816 #define EMAC_RWU_FILTER_UNICAST 0 817 818 //***************************************************************************** 819 // 820 // The following structure fields must be packed. 821 // 822 //***************************************************************************** 823 #ifdef ewarm 824 #pragma pack(1) 825 #endif 826 827 //***************************************************************************** 828 // 829 //! This structure defines up to 4 filters that can be used to define specific 830 //! frames which will cause the MAC to wake up from sleep mode. 831 // 832 //***************************************************************************** 833 typedef struct 834 { 835 // 836 //! A byte mask for each filter defining which bytes from a sequence of 837 //! 31 (bit 31 must be clear in each mask) are used to filter incoming 838 //! packets. A 1 indicates that the relevant byte is used to update the 839 //! CRC16 for the filter, a 0 indicates that the byte is ignored. 840 // 841 uint32_t pui32ByteMask[4]; 842 843 // 844 //! Defines whether each filter is enabled and, if so, whether it filters 845 //! multicast or unicast frames. Valid values are one of 846 //! EMAC_RWU_FILTER_ENABLE or EMAC_RWU_FILTER_DISABLE ORed with one of 847 //! EMAC_RWU_FILTER_UNICAST or EMAC_RWU_FILTER_MULTICAST. 848 // 849 uint8_t pui8Command[4]; 850 851 // 852 //! Determines the byte offset within the frame at which the filter starts 853 //! examining bytes. The minimum value for each offset is 12. The first 854 //! byte of a frame is offset 0. 855 // 856 uint8_t pui8Offset[4]; 857 858 // 859 //! The CRC16 value that is expected for each filter if it passes. The 860 //! CRC is calculated using all bytes indicated by the filter's mask. 861 // 862 uint16_t pui16CRC[4]; 863 } 864 #if defined(ccs) || \ 865 defined(codered) || \ 866 defined(gcc) || \ 867 defined(rvmdk) || \ 868 defined(__ARMCC_VERSION) || \ 869 defined(sourcerygxx) 870 __attribute__ ((packed)) tEMACWakeUpFrameFilter; 871 #else 872 tEMACWakeUpFrameFilter; 873 #endif 874 875 //***************************************************************************** 876 // 877 // Turn off structure packing again. 878 // 879 //***************************************************************************** 880 #ifdef ewarm 881 #pragma pack() 882 #endif 883 884 //***************************************************************************** 885 // 886 // Values which may be ORed together and used in the ui32Flags parameter to 887 // EMACPowerManagementControlSet. These may also returned be from a call to 888 // EMACPowerManagementControlGet. 889 // 890 //***************************************************************************** 891 #define EMAC_PMT_GLOBAL_UNICAST_ENABLE 0x00000200 892 #define EMAC_PMT_WAKEUP_PACKET_ENABLE 0x00000004 893 #define EMAC_PMT_MAGIC_PACKET_ENABLE 0x00000002 894 #define EMAC_PMT_POWER_DOWN 0x00000001 895 896 //***************************************************************************** 897 // 898 // Values which may be ORed together and returned from a call to 899 // EMACPowerManagementStatusGet. This call will also return 900 // EMAC_PMT_POWER_DOWN if the MAC is in power-down mode. 901 // 902 //***************************************************************************** 903 #define EMAC_PMT_WAKEUP_PACKET_RECEIVED 0x00000040 904 #define EMAC_PMT_MAGIC_PACKET_RECEIVED 0x00000020 905 906 //***************************************************************************** 907 // 908 // Close the Doxygen group. 909 //! @} 910 // 911 //***************************************************************************** 912 913 //***************************************************************************** 914 // 915 // Public function prototypes. 916 // 917 //***************************************************************************** 918 extern void EMACInit(uint32_t ui32Base, uint32_t ui32SysClk, 919 uint32_t ui32BusConfig, uint32_t ui32RxBurst, 920 uint32_t ui32TxBurst, uint32_t ui32DescSkipSize); 921 extern void EMACReset(uint32_t ui32Base); 922 extern void EMACPHYConfigSet(uint32_t ui32Base, uint32_t ui32Config); 923 extern void EMACConfigSet(uint32_t ui32Base, uint32_t ui32Config, 924 uint32_t ui32ModeFlags, 925 uint32_t ui32RxMaxFrameSize); 926 extern void EMACFrameFilterSet(uint32_t ui32Base, uint32_t ui32FilterOpts); 927 extern uint32_t EMACFrameFilterGet(uint32_t ui32Base); 928 extern void EMACHashFilterSet(uint32_t ui32Base, uint32_t ui32HashHi, 929 uint32_t ui32HashLo); 930 extern void EMACHashFilterGet(uint32_t ui32Base, uint32_t *pui32HashHi, 931 uint32_t *pui32HashLo); 932 extern uint32_t EMACHashFilterBitCalculate(uint8_t *pui8MACAddr); 933 extern void EMACTxDMAPollDemand(uint32_t ui32Base); 934 extern void EMACRxDMAPollDemand(uint32_t ui32Base); 935 extern void EMACRxDMADescriptorListSet(uint32_t ui32Base, 936 tEMACDMADescriptor *pDescriptor); 937 extern tEMACDMADescriptor *EMACRxDMADescriptorListGet(uint32_t ui32Base); 938 extern tEMACDMADescriptor *EMACRxDMACurrentDescriptorGet(uint32_t ui32Base); 939 extern uint8_t *EMACRxDMACurrentBufferGet(uint32_t ui32Base); 940 extern void EMACTxDMADescriptorListSet(uint32_t ui32Base, 941 tEMACDMADescriptor *pDescriptor); 942 extern tEMACDMADescriptor *EMACTxDMADescriptorListGet(uint32_t ui32Base); 943 extern tEMACDMADescriptor *EMACTxDMACurrentDescriptorGet(uint32_t ui32Base); 944 extern uint8_t *EMACTxDMACurrentBufferGet(uint32_t ui32Base); 945 extern void EMACConfigGet(uint32_t ui32Base, uint32_t *pui32Config, 946 uint32_t *pui32Mode, uint32_t *pui32RxMaxFrameSize); 947 extern void EMACAddrSet(uint32_t ui32Base, uint32_t ui32Index, 948 const uint8_t *pui8MACAddr); 949 extern void EMACAddrGet(uint32_t ui32Base, uint32_t ui32Index, 950 uint8_t *pui8MACAddr); 951 extern uint32_t EMACNumAddrGet(uint32_t ui32Base); 952 extern void EMACAddrFilterSet(uint32_t ui32Base, uint32_t ui32Index, 953 uint32_t ui32Config); 954 extern uint32_t EMACAddrFilterGet(uint32_t ui32Base, uint32_t ui32Index); 955 extern void EMACRxWatchdogTimerSet(uint32_t ui32Base, uint8_t ui8Timeout); 956 extern uint32_t EMACStatusGet(uint32_t ui32Base); 957 extern uint32_t EMACDMAStateGet(uint32_t ui32Base); 958 extern void EMACTxFlush(uint32_t ui32Base); 959 extern void EMACTxEnable(uint32_t ui32Base); 960 extern void EMACTxDisable(uint32_t ui32Base); 961 extern void EMACRxEnable(uint32_t ui32Base); 962 extern void EMACRxDisable(uint32_t ui32Base); 963 extern void EMACIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags); 964 extern void EMACIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags); 965 extern uint32_t EMACIntStatus(uint32_t ui32Base, bool bMasked); 966 extern void EMACIntClear(uint32_t ui32Base, uint32_t ui32IntFlags); 967 extern void EMACIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)); 968 extern void EMACIntUnregister(uint32_t ui32Base); 969 extern void EMACPHYWrite(uint32_t ui32Base, uint8_t ui8PhyAddr, 970 uint8_t ui8RegAddr, uint16_t ui16Data); 971 extern void EMACPHYExtendedWrite(uint32_t ui32Base, uint8_t ui8PhyAddr, 972 uint16_t ui16RegAddr, uint16_t ui16Data); 973 extern uint16_t EMACPHYRead(uint32_t ui32Base, uint8_t ui8PhyAddr, 974 uint8_t ui8RegAddr); 975 extern uint16_t EMACPHYExtendedRead(uint32_t ui32Base, uint8_t ui8PhyAddr, 976 uint16_t ui16RegAddr); 977 extern void EMACPHYPowerOff(uint32_t ui32Base, uint8_t ui8PhyAddr); 978 extern void EMACPHYPowerOn(uint32_t ui32Base, uint8_t ui8PhyAddr); 979 extern void EMACTimestampConfigSet(uint32_t ui32Base, uint32_t ui32Config, 980 uint32_t ui32SubSecondInc); 981 extern uint32_t EMACTimestampConfigGet(uint32_t ui32Base, 982 uint32_t *pui32SubSecondInc); 983 extern void EMACTimestampAddendSet(uint32_t ui32Base, uint32_t ui32Seconds); 984 extern void EMACTimestampEnable(uint32_t ui32Base); 985 extern void EMACTimestampDisable(uint32_t ui32Base); 986 extern void EMACTimestampSysTimeSet(uint32_t ui32Base, uint32_t ui32Seconds, 987 uint32_t ui32SubSeconds); 988 extern void EMACTimestampSysTimeGet(uint32_t ui32Base, uint32_t *pui32Seconds, 989 uint32_t *pui32SubSeconds); 990 extern void EMACTimestampSysTimeUpdate(uint32_t ui32Base, uint32_t ui32Seconds, 991 uint32_t ui32SubSeconds, bool bInc); 992 extern void EMACTimestampTargetSet(uint32_t ui32Base, uint32_t ui32Seconds, 993 uint32_t ui32Nanoseconds); 994 extern void EMACTimestampTargetIntEnable(uint32_t ui32Base); 995 extern void EMACTimestampTargetIntDisable(uint32_t ui32Base); 996 extern uint32_t EMACTimestampIntStatus(uint32_t ui32Base); 997 extern void EMACTimestampPPSSimpleModeSet(uint32_t ui32Base, 998 uint32_t ui32FreqConfig); 999 extern void EMACTimestampPPSCommandModeSet(uint32_t ui32Base, 1000 uint32_t ui32Config); 1001 extern void EMACTimestampPPSCommand(uint32_t ui32Base, uint8_t ui8Cmd); 1002 extern void EMACTimestampPPSPeriodSet(uint32_t ui32Base, uint32_t ui32Period, 1003 uint32_t ui32Width); 1004 extern void EMACVLANRxConfigSet(uint32_t ui32Base, uint16_t ui16Tag, 1005 uint32_t ui32Config); 1006 extern uint32_t EMACVLANRxConfigGet(uint32_t ui32Base, uint16_t *pui16Tag); 1007 extern void EMACVLANTxConfigSet(uint32_t ui32Base, uint16_t ui16Tag, 1008 uint32_t ui32Config); 1009 extern uint32_t EMACVLANTxConfigGet(uint32_t ui32Base, uint16_t *pui16Tag); 1010 extern uint32_t EMACVLANHashFilterBitCalculate(uint16_t ui16Tag); 1011 extern void EMACVLANHashFilterSet(uint32_t ui32Base, uint32_t ui32Hash); 1012 extern uint32_t EMACVLANHashFilterGet(uint32_t ui32Base); 1013 extern void EMACRemoteWakeUpFrameFilterSet(uint32_t ui32Base, 1014 const tEMACWakeUpFrameFilter *pFilter); 1015 extern void EMACRemoteWakeUpFrameFilterGet(uint32_t ui32Base, 1016 tEMACWakeUpFrameFilter *pFilter); 1017 extern void EMACPowerManagementControlSet(uint32_t ui32Base, 1018 uint32_t ui32Flags); 1019 extern uint32_t EMACPowerManagementControlGet(uint32_t ui32Base); 1020 extern uint32_t EMACPowerManagementStatusGet(uint32_t ui32Base); 1021 extern void EMACWoLEnter(uint32_t ui32Base); 1022 extern void EMACLPIConfig(uint32_t ui32Base, bool bLPIConfig, 1023 uint16_t ui16LPILSTimer, uint16_t ui16LPITWTimer); 1024 extern void EMACLPIEnter(uint32_t ui32Base); 1025 extern uint16_t EMACLPIStatus(uint32_t ui32Base); 1026 extern void EMACLPILinkSet(uint32_t ui32Base); 1027 extern void EMACLPILinkClear(uint32_t ui32Base); 1028 extern void EMACPHYMMDWrite(uint32_t ui32Base, uint8_t ui8PhyAddr, 1029 uint16_t ui16RegAddr, uint16_t ui16Data); 1030 extern uint16_t EMACPHYMMDRead(uint32_t ui32Base, uint8_t ui8PhyAddr, 1031 uint16_t ui16RegAddr); 1032 //***************************************************************************** 1033 // 1034 // Mark the end of the C bindings section for C++ compilers. 1035 // 1036 //***************************************************************************** 1037 #ifdef __cplusplus 1038 } 1039 #endif 1040 1041 #endif // __DRIVERLIB_EMAC_H__ 1042