1 //***************************************************************************** 2 // 3 // sysctl.h - Prototypes for the system control driver. 4 // 5 // Copyright (c) 2005-2020 Texas Instruments Incorporated. All rights reserved. 6 // Software License Agreement 7 // 8 // Redistribution and use in source and binary forms, with or without 9 // modification, are permitted provided that the following conditions 10 // are met: 11 // 12 // Redistributions of source code must retain the above copyright 13 // notice, this list of conditions and the following disclaimer. 14 // 15 // Redistributions in binary form must reproduce the above copyright 16 // notice, this list of conditions and the following disclaimer in the 17 // documentation and/or other materials provided with the 18 // distribution. 19 // 20 // Neither the name of Texas Instruments Incorporated nor the names of 21 // its contributors may be used to endorse or promote products derived 22 // from this software without specific prior written permission. 23 // 24 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 27 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 28 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 29 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 30 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 34 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 // 36 // This is part of revision 2.2.0.295 of the Tiva Peripheral Driver Library. 37 // 38 //***************************************************************************** 39 40 #ifndef __DRIVERLIB_SYSCTL_H__ 41 #define __DRIVERLIB_SYSCTL_H__ 42 43 //***************************************************************************** 44 // 45 // If building with a C++ compiler, make all of the definitions in this header 46 // have a C binding. 47 // 48 //***************************************************************************** 49 #ifdef __cplusplus 50 extern "C" 51 { 52 #endif 53 54 //***************************************************************************** 55 // 56 // The following are values that can be passed to the 57 // SysCtlPeripheralPresent(), SysCtlPeripheralEnable(), 58 // SysCtlPeripheralDisable(), and SysCtlPeripheralReset() APIs as the 59 // ui32Peripheral parameter. The peripherals in the fourth group (upper nibble 60 // is 3) can only be used with the SysCtlPeripheralPresent() API. 61 // 62 //***************************************************************************** 63 #define SYSCTL_PERIPH_ADC0 0xf0003800 // ADC 0 64 #define SYSCTL_PERIPH_ADC1 0xf0003801 // ADC 1 65 #define SYSCTL_PERIPH_CAN0 0xf0003400 // CAN 0 66 #define SYSCTL_PERIPH_CAN1 0xf0003401 // CAN 1 67 #define SYSCTL_PERIPH_COMP0 0xf0003c00 // Analog Comparator Module 0 68 #define SYSCTL_PERIPH_EMAC0 0xf0009c00 // Ethernet MAC0 69 #define SYSCTL_PERIPH_EPHY0 0xf0003000 // Ethernet PHY0 70 #define SYSCTL_PERIPH_EPI0 0xf0001000 // EPI0 71 #define SYSCTL_PERIPH_GPIOA 0xf0000800 // GPIO A 72 #define SYSCTL_PERIPH_GPIOB 0xf0000801 // GPIO B 73 #define SYSCTL_PERIPH_GPIOC 0xf0000802 // GPIO C 74 #define SYSCTL_PERIPH_GPIOD 0xf0000803 // GPIO D 75 #define SYSCTL_PERIPH_GPIOE 0xf0000804 // GPIO E 76 #define SYSCTL_PERIPH_GPIOF 0xf0000805 // GPIO F 77 #define SYSCTL_PERIPH_GPIOG 0xf0000806 // GPIO G 78 #define SYSCTL_PERIPH_GPIOH 0xf0000807 // GPIO H 79 #define SYSCTL_PERIPH_GPIOJ 0xf0000808 // GPIO J 80 #define SYSCTL_PERIPH_HIBERNATE 0xf0001400 // Hibernation module 81 #define SYSCTL_PERIPH_CCM0 0xf0007400 // CCM 0 82 #define SYSCTL_PERIPH_EEPROM0 0xf0005800 // EEPROM 0 83 #define SYSCTL_PERIPH_FAN0 0xf0005400 // FAN 0 84 #define SYSCTL_PERIPH_FAN1 0xf0005401 // FAN 1 85 #define SYSCTL_PERIPH_GPIOK 0xf0000809 // GPIO K 86 #define SYSCTL_PERIPH_GPIOL 0xf000080a // GPIO L 87 #define SYSCTL_PERIPH_GPIOM 0xf000080b // GPIO M 88 #define SYSCTL_PERIPH_GPION 0xf000080c // GPIO N 89 #define SYSCTL_PERIPH_GPIOP 0xf000080d // GPIO P 90 #define SYSCTL_PERIPH_GPIOQ 0xf000080e // GPIO Q 91 #define SYSCTL_PERIPH_GPIOR 0xf000080f // GPIO R 92 #define SYSCTL_PERIPH_GPIOS 0xf0000810 // GPIO S 93 #define SYSCTL_PERIPH_GPIOT 0xf0000811 // GPIO T 94 #define SYSCTL_PERIPH_I2C0 0xf0002000 // I2C 0 95 #define SYSCTL_PERIPH_I2C1 0xf0002001 // I2C 1 96 #define SYSCTL_PERIPH_I2C2 0xf0002002 // I2C 2 97 #define SYSCTL_PERIPH_I2C3 0xf0002003 // I2C 3 98 #define SYSCTL_PERIPH_I2C4 0xf0002004 // I2C 4 99 #define SYSCTL_PERIPH_I2C5 0xf0002005 // I2C 5 100 #define SYSCTL_PERIPH_I2C6 0xf0002006 // I2C 6 101 #define SYSCTL_PERIPH_I2C7 0xf0002007 // I2C 7 102 #define SYSCTL_PERIPH_I2C8 0xf0002008 // I2C 8 103 #define SYSCTL_PERIPH_I2C9 0xf0002009 // I2C 9 104 #define SYSCTL_PERIPH_LCD0 0xf0009000 // LCD 0 105 #define SYSCTL_PERIPH_ONEWIRE0 0xf0009800 // One Wire 0 106 #define SYSCTL_PERIPH_PWM0 0xf0004000 // PWM 0 107 #define SYSCTL_PERIPH_PWM1 0xf0004001 // PWM 1 108 #define SYSCTL_PERIPH_QEI0 0xf0004400 // QEI 0 109 #define SYSCTL_PERIPH_QEI1 0xf0004401 // QEI 1 110 #define SYSCTL_PERIPH_SSI0 0xf0001c00 // SSI 0 111 #define SYSCTL_PERIPH_SSI1 0xf0001c01 // SSI 1 112 #define SYSCTL_PERIPH_SSI2 0xf0001c02 // SSI 2 113 #define SYSCTL_PERIPH_SSI3 0xf0001c03 // SSI 3 114 #define SYSCTL_PERIPH_TIMER0 0xf0000400 // Timer 0 115 #define SYSCTL_PERIPH_TIMER1 0xf0000401 // Timer 1 116 #define SYSCTL_PERIPH_TIMER2 0xf0000402 // Timer 2 117 #define SYSCTL_PERIPH_TIMER3 0xf0000403 // Timer 3 118 #define SYSCTL_PERIPH_TIMER4 0xf0000404 // Timer 4 119 #define SYSCTL_PERIPH_TIMER5 0xf0000405 // Timer 5 120 #define SYSCTL_PERIPH_TIMER6 0xf0000406 // Timer 6 121 #define SYSCTL_PERIPH_TIMER7 0xf0000407 // Timer 7 122 #define SYSCTL_PERIPH_UART0 0xf0001800 // UART 0 123 #define SYSCTL_PERIPH_UART1 0xf0001801 // UART 1 124 #define SYSCTL_PERIPH_UART2 0xf0001802 // UART 2 125 #define SYSCTL_PERIPH_UART3 0xf0001803 // UART 3 126 #define SYSCTL_PERIPH_UART4 0xf0001804 // UART 4 127 #define SYSCTL_PERIPH_UART5 0xf0001805 // UART 5 128 #define SYSCTL_PERIPH_UART6 0xf0001806 // UART 6 129 #define SYSCTL_PERIPH_UART7 0xf0001807 // UART 7 130 #define SYSCTL_PERIPH_UDMA 0xf0000c00 // uDMA 131 #define SYSCTL_PERIPH_USB0 0xf0002800 // USB 0 132 #define SYSCTL_PERIPH_WDOG0 0xf0000000 // Watchdog 0 133 #define SYSCTL_PERIPH_WDOG1 0xf0000001 // Watchdog 1 134 #define SYSCTL_PERIPH_WTIMER0 0xf0005c00 // Wide Timer 0 135 #define SYSCTL_PERIPH_WTIMER1 0xf0005c01 // Wide Timer 1 136 #define SYSCTL_PERIPH_WTIMER2 0xf0005c02 // Wide Timer 2 137 #define SYSCTL_PERIPH_WTIMER3 0xf0005c03 // Wide Timer 3 138 #define SYSCTL_PERIPH_WTIMER4 0xf0005c04 // Wide Timer 4 139 #define SYSCTL_PERIPH_WTIMER5 0xf0005c05 // Wide Timer 5 140 141 //***************************************************************************** 142 // 143 // The following are values that can be passed to the SysCtlLDOSleepSet() and 144 // SysCtlLDODeepSleepSet() APIs as the ui32Voltage value, or returned by the 145 // SysCtlLDOSleepGet() and SysCtlLDODeepSleepGet() APIs. 146 // 147 //***************************************************************************** 148 #define SYSCTL_LDO_0_90V 0x80000012 // LDO output of 0.90V 149 #define SYSCTL_LDO_0_95V 0x80000013 // LDO output of 0.95V 150 #define SYSCTL_LDO_1_00V 0x80000014 // LDO output of 1.00V 151 #define SYSCTL_LDO_1_05V 0x80000015 // LDO output of 1.05V 152 #define SYSCTL_LDO_1_10V 0x80000016 // LDO output of 1.10V 153 #define SYSCTL_LDO_1_15V 0x80000017 // LDO output of 1.15V 154 #define SYSCTL_LDO_1_20V 0x80000018 // LDO output of 1.20V 155 156 //***************************************************************************** 157 // 158 // The following are values that can be passed to the SysCtlIntEnable(), 159 // SysCtlIntDisable(), and SysCtlIntClear() APIs, or returned in the bit mask 160 // by the SysCtlIntStatus() API. 161 // 162 //***************************************************************************** 163 #define SYSCTL_INT_BOR0 0x00000800 // VDD under BOR0 164 #define SYSCTL_INT_VDDA_OK 0x00000400 // VDDA Power OK 165 #define SYSCTL_INT_MOSC_PUP 0x00000100 // MOSC power-up interrupt 166 #define SYSCTL_INT_USBPLL_LOCK 0x00000080 // USB PLL lock interrupt 167 #define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt 168 #define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int 169 #define SYSCTL_INT_BOR1 0x00000002 // VDD under BOR1 170 #define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt 171 172 //***************************************************************************** 173 // 174 // The following are values that can be passed to the SysCtlResetCauseClear() 175 // API or returned by the SysCtlResetCauseGet() API. 176 // 177 //***************************************************************************** 178 #define SYSCTL_CAUSE_HSRVREQ 0x00001000 // Hardware System Service Request 179 #define SYSCTL_CAUSE_HIB 0x00000040 // Hibernate reset 180 #define SYSCTL_CAUSE_WDOG1 0x00000020 // Watchdog 1 reset 181 #define SYSCTL_CAUSE_SW 0x00000010 // Software reset 182 #define SYSCTL_CAUSE_WDOG0 0x00000008 // Watchdog 0 reset 183 #ifndef DEPRECATED 184 #define SYSCTL_CAUSE_WDOG SYSCTL_CAUSE_WDOG0 185 // Watchdog reset(Deprecated) 186 #endif 187 #define SYSCTL_CAUSE_BOR 0x00000004 // Brown-out reset 188 #define SYSCTL_CAUSE_POR 0x00000002 // Power on reset 189 #define SYSCTL_CAUSE_EXT 0x00000001 // External reset 190 191 //***************************************************************************** 192 // 193 // The following are values that can be passed to the SysCtlBrownOutConfigSet() 194 // API as the ui32Config parameter. 195 // 196 //***************************************************************************** 197 #define SYSCTL_BOR_RESET 0x00000002 // Reset instead of interrupting 198 #define SYSCTL_BOR_RESAMPLE 0x00000001 // Resample BOR before asserting 199 200 //***************************************************************************** 201 // 202 // The following are values that can be passed to the SysCtlPWMClockSet() API 203 // as the ui32Config parameter, and can be returned by the SysCtlPWMClockGet() 204 // API. 205 // 206 //***************************************************************************** 207 #define SYSCTL_PWMDIV_1 0x00000000 // PWM clock is processor clock /1 208 #define SYSCTL_PWMDIV_2 0x00100000 // PWM clock is processor clock /2 209 #define SYSCTL_PWMDIV_4 0x00120000 // PWM clock is processor clock /4 210 #define SYSCTL_PWMDIV_8 0x00140000 // PWM clock is processor clock /8 211 #define SYSCTL_PWMDIV_16 0x00160000 // PWM clock is processor clock /16 212 #define SYSCTL_PWMDIV_32 0x00180000 // PWM clock is processor clock /32 213 #define SYSCTL_PWMDIV_64 0x001A0000 // PWM clock is processor clock /64 214 215 //***************************************************************************** 216 // 217 // The following are values that can be passed to the SysCtlClockSet() API as 218 // the ui32Config parameter. 219 // 220 //***************************************************************************** 221 #define SYSCTL_SYSDIV_1 0x07800000 // Processor clock is osc/pll /1 222 #define SYSCTL_SYSDIV_2 0x00C00000 // Processor clock is osc/pll /2 223 #define SYSCTL_SYSDIV_3 0x01400000 // Processor clock is osc/pll /3 224 #define SYSCTL_SYSDIV_4 0x01C00000 // Processor clock is osc/pll /4 225 #define SYSCTL_SYSDIV_5 0x02400000 // Processor clock is osc/pll /5 226 #define SYSCTL_SYSDIV_6 0x02C00000 // Processor clock is osc/pll /6 227 #define SYSCTL_SYSDIV_7 0x03400000 // Processor clock is osc/pll /7 228 #define SYSCTL_SYSDIV_8 0x03C00000 // Processor clock is osc/pll /8 229 #define SYSCTL_SYSDIV_9 0x04400000 // Processor clock is osc/pll /9 230 #define SYSCTL_SYSDIV_10 0x04C00000 // Processor clock is osc/pll /10 231 #define SYSCTL_SYSDIV_11 0x05400000 // Processor clock is osc/pll /11 232 #define SYSCTL_SYSDIV_12 0x05C00000 // Processor clock is osc/pll /12 233 #define SYSCTL_SYSDIV_13 0x06400000 // Processor clock is osc/pll /13 234 #define SYSCTL_SYSDIV_14 0x06C00000 // Processor clock is osc/pll /14 235 #define SYSCTL_SYSDIV_15 0x07400000 // Processor clock is osc/pll /15 236 #define SYSCTL_SYSDIV_16 0x07C00000 // Processor clock is osc/pll /16 237 #define SYSCTL_SYSDIV_17 0x88400000 // Processor clock is osc/pll /17 238 #define SYSCTL_SYSDIV_18 0x88C00000 // Processor clock is osc/pll /18 239 #define SYSCTL_SYSDIV_19 0x89400000 // Processor clock is osc/pll /19 240 #define SYSCTL_SYSDIV_20 0x89C00000 // Processor clock is osc/pll /20 241 #define SYSCTL_SYSDIV_21 0x8A400000 // Processor clock is osc/pll /21 242 #define SYSCTL_SYSDIV_22 0x8AC00000 // Processor clock is osc/pll /22 243 #define SYSCTL_SYSDIV_23 0x8B400000 // Processor clock is osc/pll /23 244 #define SYSCTL_SYSDIV_24 0x8BC00000 // Processor clock is osc/pll /24 245 #define SYSCTL_SYSDIV_25 0x8C400000 // Processor clock is osc/pll /25 246 #define SYSCTL_SYSDIV_26 0x8CC00000 // Processor clock is osc/pll /26 247 #define SYSCTL_SYSDIV_27 0x8D400000 // Processor clock is osc/pll /27 248 #define SYSCTL_SYSDIV_28 0x8DC00000 // Processor clock is osc/pll /28 249 #define SYSCTL_SYSDIV_29 0x8E400000 // Processor clock is osc/pll /29 250 #define SYSCTL_SYSDIV_30 0x8EC00000 // Processor clock is osc/pll /30 251 #define SYSCTL_SYSDIV_31 0x8F400000 // Processor clock is osc/pll /31 252 #define SYSCTL_SYSDIV_32 0x8FC00000 // Processor clock is osc/pll /32 253 #define SYSCTL_SYSDIV_33 0x90400000 // Processor clock is osc/pll /33 254 #define SYSCTL_SYSDIV_34 0x90C00000 // Processor clock is osc/pll /34 255 #define SYSCTL_SYSDIV_35 0x91400000 // Processor clock is osc/pll /35 256 #define SYSCTL_SYSDIV_36 0x91C00000 // Processor clock is osc/pll /36 257 #define SYSCTL_SYSDIV_37 0x92400000 // Processor clock is osc/pll /37 258 #define SYSCTL_SYSDIV_38 0x92C00000 // Processor clock is osc/pll /38 259 #define SYSCTL_SYSDIV_39 0x93400000 // Processor clock is osc/pll /39 260 #define SYSCTL_SYSDIV_40 0x93C00000 // Processor clock is osc/pll /40 261 #define SYSCTL_SYSDIV_41 0x94400000 // Processor clock is osc/pll /41 262 #define SYSCTL_SYSDIV_42 0x94C00000 // Processor clock is osc/pll /42 263 #define SYSCTL_SYSDIV_43 0x95400000 // Processor clock is osc/pll /43 264 #define SYSCTL_SYSDIV_44 0x95C00000 // Processor clock is osc/pll /44 265 #define SYSCTL_SYSDIV_45 0x96400000 // Processor clock is osc/pll /45 266 #define SYSCTL_SYSDIV_46 0x96C00000 // Processor clock is osc/pll /46 267 #define SYSCTL_SYSDIV_47 0x97400000 // Processor clock is osc/pll /47 268 #define SYSCTL_SYSDIV_48 0x97C00000 // Processor clock is osc/pll /48 269 #define SYSCTL_SYSDIV_49 0x98400000 // Processor clock is osc/pll /49 270 #define SYSCTL_SYSDIV_50 0x98C00000 // Processor clock is osc/pll /50 271 #define SYSCTL_SYSDIV_51 0x99400000 // Processor clock is osc/pll /51 272 #define SYSCTL_SYSDIV_52 0x99C00000 // Processor clock is osc/pll /52 273 #define SYSCTL_SYSDIV_53 0x9A400000 // Processor clock is osc/pll /53 274 #define SYSCTL_SYSDIV_54 0x9AC00000 // Processor clock is osc/pll /54 275 #define SYSCTL_SYSDIV_55 0x9B400000 // Processor clock is osc/pll /55 276 #define SYSCTL_SYSDIV_56 0x9BC00000 // Processor clock is osc/pll /56 277 #define SYSCTL_SYSDIV_57 0x9C400000 // Processor clock is osc/pll /57 278 #define SYSCTL_SYSDIV_58 0x9CC00000 // Processor clock is osc/pll /58 279 #define SYSCTL_SYSDIV_59 0x9D400000 // Processor clock is osc/pll /59 280 #define SYSCTL_SYSDIV_60 0x9DC00000 // Processor clock is osc/pll /60 281 #define SYSCTL_SYSDIV_61 0x9E400000 // Processor clock is osc/pll /61 282 #define SYSCTL_SYSDIV_62 0x9EC00000 // Processor clock is osc/pll /62 283 #define SYSCTL_SYSDIV_63 0x9F400000 // Processor clock is osc/pll /63 284 #define SYSCTL_SYSDIV_64 0x9FC00000 // Processor clock is osc/pll /64 285 #define SYSCTL_SYSDIV_2_5 0xC1000000 // Processor clock is pll / 2.5 286 #define SYSCTL_SYSDIV_3_5 0xC1800000 // Processor clock is pll / 3.5 287 #define SYSCTL_SYSDIV_4_5 0xC2000000 // Processor clock is pll / 4.5 288 #define SYSCTL_SYSDIV_5_5 0xC2800000 // Processor clock is pll / 5.5 289 #define SYSCTL_SYSDIV_6_5 0xC3000000 // Processor clock is pll / 6.5 290 #define SYSCTL_SYSDIV_7_5 0xC3800000 // Processor clock is pll / 7.5 291 #define SYSCTL_SYSDIV_8_5 0xC4000000 // Processor clock is pll / 8.5 292 #define SYSCTL_SYSDIV_9_5 0xC4800000 // Processor clock is pll / 9.5 293 #define SYSCTL_SYSDIV_10_5 0xC5000000 // Processor clock is pll / 10.5 294 #define SYSCTL_SYSDIV_11_5 0xC5800000 // Processor clock is pll / 11.5 295 #define SYSCTL_SYSDIV_12_5 0xC6000000 // Processor clock is pll / 12.5 296 #define SYSCTL_SYSDIV_13_5 0xC6800000 // Processor clock is pll / 13.5 297 #define SYSCTL_SYSDIV_14_5 0xC7000000 // Processor clock is pll / 14.5 298 #define SYSCTL_SYSDIV_15_5 0xC7800000 // Processor clock is pll / 15.5 299 #define SYSCTL_SYSDIV_16_5 0xC8000000 // Processor clock is pll / 16.5 300 #define SYSCTL_SYSDIV_17_5 0xC8800000 // Processor clock is pll / 17.5 301 #define SYSCTL_SYSDIV_18_5 0xC9000000 // Processor clock is pll / 18.5 302 #define SYSCTL_SYSDIV_19_5 0xC9800000 // Processor clock is pll / 19.5 303 #define SYSCTL_SYSDIV_20_5 0xCA000000 // Processor clock is pll / 20.5 304 #define SYSCTL_SYSDIV_21_5 0xCA800000 // Processor clock is pll / 21.5 305 #define SYSCTL_SYSDIV_22_5 0xCB000000 // Processor clock is pll / 22.5 306 #define SYSCTL_SYSDIV_23_5 0xCB800000 // Processor clock is pll / 23.5 307 #define SYSCTL_SYSDIV_24_5 0xCC000000 // Processor clock is pll / 24.5 308 #define SYSCTL_SYSDIV_25_5 0xCC800000 // Processor clock is pll / 25.5 309 #define SYSCTL_SYSDIV_26_5 0xCD000000 // Processor clock is pll / 26.5 310 #define SYSCTL_SYSDIV_27_5 0xCD800000 // Processor clock is pll / 27.5 311 #define SYSCTL_SYSDIV_28_5 0xCE000000 // Processor clock is pll / 28.5 312 #define SYSCTL_SYSDIV_29_5 0xCE800000 // Processor clock is pll / 29.5 313 #define SYSCTL_SYSDIV_30_5 0xCF000000 // Processor clock is pll / 30.5 314 #define SYSCTL_SYSDIV_31_5 0xCF800000 // Processor clock is pll / 31.5 315 #define SYSCTL_SYSDIV_32_5 0xD0000000 // Processor clock is pll / 32.5 316 #define SYSCTL_SYSDIV_33_5 0xD0800000 // Processor clock is pll / 33.5 317 #define SYSCTL_SYSDIV_34_5 0xD1000000 // Processor clock is pll / 34.5 318 #define SYSCTL_SYSDIV_35_5 0xD1800000 // Processor clock is pll / 35.5 319 #define SYSCTL_SYSDIV_36_5 0xD2000000 // Processor clock is pll / 36.5 320 #define SYSCTL_SYSDIV_37_5 0xD2800000 // Processor clock is pll / 37.5 321 #define SYSCTL_SYSDIV_38_5 0xD3000000 // Processor clock is pll / 38.5 322 #define SYSCTL_SYSDIV_39_5 0xD3800000 // Processor clock is pll / 39.5 323 #define SYSCTL_SYSDIV_40_5 0xD4000000 // Processor clock is pll / 40.5 324 #define SYSCTL_SYSDIV_41_5 0xD4800000 // Processor clock is pll / 41.5 325 #define SYSCTL_SYSDIV_42_5 0xD5000000 // Processor clock is pll / 42.5 326 #define SYSCTL_SYSDIV_43_5 0xD5800000 // Processor clock is pll / 43.5 327 #define SYSCTL_SYSDIV_44_5 0xD6000000 // Processor clock is pll / 44.5 328 #define SYSCTL_SYSDIV_45_5 0xD6800000 // Processor clock is pll / 45.5 329 #define SYSCTL_SYSDIV_46_5 0xD7000000 // Processor clock is pll / 46.5 330 #define SYSCTL_SYSDIV_47_5 0xD7800000 // Processor clock is pll / 47.5 331 #define SYSCTL_SYSDIV_48_5 0xD8000000 // Processor clock is pll / 48.5 332 #define SYSCTL_SYSDIV_49_5 0xD8800000 // Processor clock is pll / 49.5 333 #define SYSCTL_SYSDIV_50_5 0xD9000000 // Processor clock is pll / 50.5 334 #define SYSCTL_SYSDIV_51_5 0xD9800000 // Processor clock is pll / 51.5 335 #define SYSCTL_SYSDIV_52_5 0xDA000000 // Processor clock is pll / 52.5 336 #define SYSCTL_SYSDIV_53_5 0xDA800000 // Processor clock is pll / 53.5 337 #define SYSCTL_SYSDIV_54_5 0xDB000000 // Processor clock is pll / 54.5 338 #define SYSCTL_SYSDIV_55_5 0xDB800000 // Processor clock is pll / 55.5 339 #define SYSCTL_SYSDIV_56_5 0xDC000000 // Processor clock is pll / 56.5 340 #define SYSCTL_SYSDIV_57_5 0xDC800000 // Processor clock is pll / 57.5 341 #define SYSCTL_SYSDIV_58_5 0xDD000000 // Processor clock is pll / 58.5 342 #define SYSCTL_SYSDIV_59_5 0xDD800000 // Processor clock is pll / 59.5 343 #define SYSCTL_SYSDIV_60_5 0xDE000000 // Processor clock is pll / 60.5 344 #define SYSCTL_SYSDIV_61_5 0xDE800000 // Processor clock is pll / 61.5 345 #define SYSCTL_SYSDIV_62_5 0xDF000000 // Processor clock is pll / 62.5 346 #define SYSCTL_SYSDIV_63_5 0xDF800000 // Processor clock is pll / 63.5 347 // 348 // TivaWare 2.2.0.xxx Update 349 // Due to TM4C129x Errata Item SYSCTL#22, the SYSCTL_CFG_VCO_xxx configurations 350 // have misleading *names* as currently defined as the VCO does not run at the 351 // stated frequencies. To amend this, new *name* defintions are being used, 352 // however the register configuration remains the same. 353 // The old definitions will remain for compatibility with code ported from 354 // older versions of TivaWare. 355 // 356 #define SYSCTL_CFG_VCO_480 0xF1000000 // VCO is 480 MHz - Legacy 357 // Does not work @ 480, use 358 // SYSCTL_CFG_VCO_240 instead 359 #define SYSCTL_CFG_VCO_320 0xF0000000 // VCO is 320 MHz - Legacy 360 // Does not work @ 320, use 361 // SYSCTL_CFG_VCO_160 instead 362 #define SYSCTL_CFG_VCO_240 0xF1000000 // VCO is 240 MHz 363 #define SYSCTL_CFG_VCO_160 0xF0000000 // VCO is 160 MHz 364 #define SYSCTL_USE_PLL 0x00000000 // System clock is the PLL clock 365 #define SYSCTL_USE_OSC 0x00003800 // System clock is the osc clock 366 #define SYSCTL_XTAL_1MHZ 0x00000000 // External crystal is 1MHz 367 #define SYSCTL_XTAL_1_84MHZ 0x00000040 // External crystal is 1.8432MHz 368 #define SYSCTL_XTAL_2MHZ 0x00000080 // External crystal is 2MHz 369 #define SYSCTL_XTAL_2_45MHZ 0x000000C0 // External crystal is 2.4576MHz 370 #define SYSCTL_XTAL_3_57MHZ 0x00000100 // External crystal is 3.579545MHz 371 #define SYSCTL_XTAL_3_68MHZ 0x00000140 // External crystal is 3.6864MHz 372 #define SYSCTL_XTAL_4MHZ 0x00000180 // External crystal is 4MHz 373 #define SYSCTL_XTAL_4_09MHZ 0x000001C0 // External crystal is 4.096MHz 374 #define SYSCTL_XTAL_4_91MHZ 0x00000200 // External crystal is 4.9152MHz 375 #define SYSCTL_XTAL_5MHZ 0x00000240 // External crystal is 5MHz 376 #define SYSCTL_XTAL_5_12MHZ 0x00000280 // External crystal is 5.12MHz 377 #define SYSCTL_XTAL_6MHZ 0x000002C0 // External crystal is 6MHz 378 #define SYSCTL_XTAL_6_14MHZ 0x00000300 // External crystal is 6.144MHz 379 #define SYSCTL_XTAL_7_37MHZ 0x00000340 // External crystal is 7.3728MHz 380 #define SYSCTL_XTAL_8MHZ 0x00000380 // External crystal is 8MHz 381 #define SYSCTL_XTAL_8_19MHZ 0x000003C0 // External crystal is 8.192MHz 382 #define SYSCTL_XTAL_10MHZ 0x00000400 // External crystal is 10 MHz 383 #define SYSCTL_XTAL_12MHZ 0x00000440 // External crystal is 12 MHz 384 #define SYSCTL_XTAL_12_2MHZ 0x00000480 // External crystal is 12.288 MHz 385 #define SYSCTL_XTAL_13_5MHZ 0x000004C0 // External crystal is 13.56 MHz 386 #define SYSCTL_XTAL_14_3MHZ 0x00000500 // External crystal is 14.31818 MHz 387 #define SYSCTL_XTAL_16MHZ 0x00000540 // External crystal is 16 MHz 388 #define SYSCTL_XTAL_16_3MHZ 0x00000580 // External crystal is 16.384 MHz 389 #define SYSCTL_XTAL_18MHZ 0x000005C0 // External crystal is 18.0 MHz 390 #define SYSCTL_XTAL_20MHZ 0x00000600 // External crystal is 20.0 MHz 391 #define SYSCTL_XTAL_24MHZ 0x00000640 // External crystal is 24.0 MHz 392 #define SYSCTL_XTAL_25MHZ 0x00000680 // External crystal is 25.0 MHz 393 #define SYSCTL_OSC_MAIN 0x00000000 // Osc source is main osc 394 #define SYSCTL_OSC_INT 0x00000010 // Osc source is int. osc 395 #define SYSCTL_OSC_INT4 0x00000020 // Osc source is int. osc /4 396 #define SYSCTL_OSC_INT30 0x00000030 // Osc source is int. 30 KHz 397 #define SYSCTL_OSC_EXT32 0x80000038 // Osc source is ext. 32 KHz 398 #define SYSCTL_INT_OSC_DIS 0x00000002 // Disable internal oscillator 399 #define SYSCTL_MAIN_OSC_DIS 0x00000001 // Disable main oscillator 400 401 //***************************************************************************** 402 // 403 // The following are values that can be passed to the SysCtlDeepSleepClockSet() 404 // API as the ui32Config parameter. 405 // 406 //***************************************************************************** 407 #define SYSCTL_DSLP_DIV_1 0x00000000 // Deep-sleep clock is osc /1 408 #define SYSCTL_DSLP_DIV_2 0x00800000 // Deep-sleep clock is osc /2 409 #define SYSCTL_DSLP_DIV_3 0x01000000 // Deep-sleep clock is osc /3 410 #define SYSCTL_DSLP_DIV_4 0x01800000 // Deep-sleep clock is osc /4 411 #define SYSCTL_DSLP_DIV_5 0x02000000 // Deep-sleep clock is osc /5 412 #define SYSCTL_DSLP_DIV_6 0x02800000 // Deep-sleep clock is osc /6 413 #define SYSCTL_DSLP_DIV_7 0x03000000 // Deep-sleep clock is osc /7 414 #define SYSCTL_DSLP_DIV_8 0x03800000 // Deep-sleep clock is osc /8 415 #define SYSCTL_DSLP_DIV_9 0x04000000 // Deep-sleep clock is osc /9 416 #define SYSCTL_DSLP_DIV_10 0x04800000 // Deep-sleep clock is osc /10 417 #define SYSCTL_DSLP_DIV_11 0x05000000 // Deep-sleep clock is osc /11 418 #define SYSCTL_DSLP_DIV_12 0x05800000 // Deep-sleep clock is osc /12 419 #define SYSCTL_DSLP_DIV_13 0x06000000 // Deep-sleep clock is osc /13 420 #define SYSCTL_DSLP_DIV_14 0x06800000 // Deep-sleep clock is osc /14 421 #define SYSCTL_DSLP_DIV_15 0x07000000 // Deep-sleep clock is osc /15 422 #define SYSCTL_DSLP_DIV_16 0x07800000 // Deep-sleep clock is osc /16 423 #define SYSCTL_DSLP_DIV_17 0x08000000 // Deep-sleep clock is osc /17 424 #define SYSCTL_DSLP_DIV_18 0x08800000 // Deep-sleep clock is osc /18 425 #define SYSCTL_DSLP_DIV_19 0x09000000 // Deep-sleep clock is osc /19 426 #define SYSCTL_DSLP_DIV_20 0x09800000 // Deep-sleep clock is osc /20 427 #define SYSCTL_DSLP_DIV_21 0x0A000000 // Deep-sleep clock is osc /21 428 #define SYSCTL_DSLP_DIV_22 0x0A800000 // Deep-sleep clock is osc /22 429 #define SYSCTL_DSLP_DIV_23 0x0B000000 // Deep-sleep clock is osc /23 430 #define SYSCTL_DSLP_DIV_24 0x0B800000 // Deep-sleep clock is osc /24 431 #define SYSCTL_DSLP_DIV_25 0x0C000000 // Deep-sleep clock is osc /25 432 #define SYSCTL_DSLP_DIV_26 0x0C800000 // Deep-sleep clock is osc /26 433 #define SYSCTL_DSLP_DIV_27 0x0D000000 // Deep-sleep clock is osc /27 434 #define SYSCTL_DSLP_DIV_28 0x0D800000 // Deep-sleep clock is osc /28 435 #define SYSCTL_DSLP_DIV_29 0x0E000000 // Deep-sleep clock is osc /29 436 #define SYSCTL_DSLP_DIV_30 0x0E800000 // Deep-sleep clock is osc /30 437 #define SYSCTL_DSLP_DIV_31 0x0F000000 // Deep-sleep clock is osc /31 438 #define SYSCTL_DSLP_DIV_32 0x0F800000 // Deep-sleep clock is osc /32 439 #define SYSCTL_DSLP_DIV_33 0x10000000 // Deep-sleep clock is osc /33 440 #define SYSCTL_DSLP_DIV_34 0x10800000 // Deep-sleep clock is osc /34 441 #define SYSCTL_DSLP_DIV_35 0x11000000 // Deep-sleep clock is osc /35 442 #define SYSCTL_DSLP_DIV_36 0x11800000 // Deep-sleep clock is osc /36 443 #define SYSCTL_DSLP_DIV_37 0x12000000 // Deep-sleep clock is osc /37 444 #define SYSCTL_DSLP_DIV_38 0x12800000 // Deep-sleep clock is osc /38 445 #define SYSCTL_DSLP_DIV_39 0x13000000 // Deep-sleep clock is osc /39 446 #define SYSCTL_DSLP_DIV_40 0x13800000 // Deep-sleep clock is osc /40 447 #define SYSCTL_DSLP_DIV_41 0x14000000 // Deep-sleep clock is osc /41 448 #define SYSCTL_DSLP_DIV_42 0x14800000 // Deep-sleep clock is osc /42 449 #define SYSCTL_DSLP_DIV_43 0x15000000 // Deep-sleep clock is osc /43 450 #define SYSCTL_DSLP_DIV_44 0x15800000 // Deep-sleep clock is osc /44 451 #define SYSCTL_DSLP_DIV_45 0x16000000 // Deep-sleep clock is osc /45 452 #define SYSCTL_DSLP_DIV_46 0x16800000 // Deep-sleep clock is osc /46 453 #define SYSCTL_DSLP_DIV_47 0x17000000 // Deep-sleep clock is osc /47 454 #define SYSCTL_DSLP_DIV_48 0x17800000 // Deep-sleep clock is osc /48 455 #define SYSCTL_DSLP_DIV_49 0x18000000 // Deep-sleep clock is osc /49 456 #define SYSCTL_DSLP_DIV_50 0x18800000 // Deep-sleep clock is osc /50 457 #define SYSCTL_DSLP_DIV_51 0x19000000 // Deep-sleep clock is osc /51 458 #define SYSCTL_DSLP_DIV_52 0x19800000 // Deep-sleep clock is osc /52 459 #define SYSCTL_DSLP_DIV_53 0x1A000000 // Deep-sleep clock is osc /53 460 #define SYSCTL_DSLP_DIV_54 0x1A800000 // Deep-sleep clock is osc /54 461 #define SYSCTL_DSLP_DIV_55 0x1B000000 // Deep-sleep clock is osc /55 462 #define SYSCTL_DSLP_DIV_56 0x1B800000 // Deep-sleep clock is osc /56 463 #define SYSCTL_DSLP_DIV_57 0x1C000000 // Deep-sleep clock is osc /57 464 #define SYSCTL_DSLP_DIV_58 0x1C800000 // Deep-sleep clock is osc /58 465 #define SYSCTL_DSLP_DIV_59 0x1D000000 // Deep-sleep clock is osc /59 466 #define SYSCTL_DSLP_DIV_60 0x1D800000 // Deep-sleep clock is osc /60 467 #define SYSCTL_DSLP_DIV_61 0x1E000000 // Deep-sleep clock is osc /61 468 #define SYSCTL_DSLP_DIV_62 0x1E800000 // Deep-sleep clock is osc /62 469 #define SYSCTL_DSLP_DIV_63 0x1F000000 // Deep-sleep clock is osc /63 470 #define SYSCTL_DSLP_DIV_64 0x1F800000 // Deep-sleep clock is osc /64 471 #define SYSCTL_DSLP_OSC_MAIN 0x00000000 // Osc source is main osc 472 #define SYSCTL_DSLP_OSC_INT 0x00000010 // Osc source is int. osc 473 #define SYSCTL_DSLP_OSC_INT30 0x00000030 // Osc source is int. 30 KHz 474 #define SYSCTL_DSLP_OSC_EXT32 0x00000070 // Osc source is ext. 32 KHz 475 #define SYSCTL_DSLP_PIOSC_PD 0x00000002 // Power down PIOSC in deep-sleep 476 #define SYSCTL_DSLP_MOSC_PD 0x40000000 // Power down MOSC in deep-sleep 477 478 //***************************************************************************** 479 // 480 // The following are values that can be passed to the SysCtlPIOSCCalibrate() 481 // API as the ui32Type parameter. 482 // 483 //***************************************************************************** 484 #define SYSCTL_PIOSC_CAL_AUTO 0x00000200 // Automatic calibration 485 #define SYSCTL_PIOSC_CAL_FACT 0x00000100 // Factory calibration 486 #define SYSCTL_PIOSC_CAL_USER 0x80000100 // User-supplied calibration 487 488 //***************************************************************************** 489 // 490 // The following are values that can be passed to the SysCtlMOSCConfigSet() API 491 // as the ui32Config parameter. 492 // 493 //***************************************************************************** 494 #define SYSCTL_MOSC_VALIDATE 0x00000001 // Enable MOSC validation 495 #define SYSCTL_MOSC_INTERRUPT 0x00000002 // Generate interrupt on MOSC fail 496 #define SYSCTL_MOSC_NO_XTAL 0x00000004 // No crystal is attached to MOSC 497 #define SYSCTL_MOSC_PWR_DIS 0x00000008 // Power down the MOSC. 498 #define SYSCTL_MOSC_LOWFREQ 0x00000000 // MOSC is less than 10MHz 499 #define SYSCTL_MOSC_HIGHFREQ 0x00000010 // MOSC is greater than 10MHz 500 #define SYSCTL_MOSC_SESRC 0x00000020 // Singled ended oscillator source. 501 502 //***************************************************************************** 503 // 504 // The following are values that can be passed to the SysCtlSleepPowerSet() and 505 // SysCtlDeepSleepPowerSet() APIs as the ui32Config parameter. 506 // 507 //***************************************************************************** 508 #define SYSCTL_LDO_SLEEP 0x00000200 // LDO in sleep mode 509 // (Deep Sleep Only) 510 #define SYSCTL_TEMP_LOW_POWER 0x00000100 // Temp sensor in low power mode 511 // (Deep Sleep Only) 512 #define SYSCTL_FLASH_NORMAL 0x00000000 // Flash in normal mode 513 #define SYSCTL_FLASH_LOW_POWER 0x00000020 // Flash in low power mode 514 #define SYSCTL_SRAM_NORMAL 0x00000000 // SRAM in normal mode 515 #define SYSCTL_SRAM_STANDBY 0x00000001 // SRAM in standby mode 516 #define SYSCTL_SRAM_LOW_POWER 0x00000003 // SRAM in low power mode 517 518 //***************************************************************************** 519 // 520 // Defines for the SysCtlResetBehaviorSet() and SysCtlResetBehaviorGet() APIs. 521 // 522 //***************************************************************************** 523 #define SYSCTL_ONRST_WDOG0_POR 0x00000030 524 #define SYSCTL_ONRST_WDOG0_SYS 0x00000020 525 #define SYSCTL_ONRST_WDOG1_POR 0x000000C0 526 #define SYSCTL_ONRST_WDOG1_SYS 0x00000080 527 #define SYSCTL_ONRST_BOR_POR 0x0000000C 528 #define SYSCTL_ONRST_BOR_SYS 0x00000008 529 #define SYSCTL_ONRST_EXT_POR 0x00000003 530 #define SYSCTL_ONRST_EXT_SYS 0x00000002 531 532 //***************************************************************************** 533 // 534 // Values used with the SysCtlVoltageEventConfig() API. 535 // 536 //***************************************************************************** 537 #define SYSCTL_VEVENT_VDDABO_NONE \ 538 0x00000000 539 #define SYSCTL_VEVENT_VDDABO_INT \ 540 0x00000100 541 #define SYSCTL_VEVENT_VDDABO_NMI \ 542 0x00000200 543 #define SYSCTL_VEVENT_VDDABO_RST \ 544 0x00000300 545 #define SYSCTL_VEVENT_VDDBO_NONE \ 546 0x00000000 547 #define SYSCTL_VEVENT_VDDBO_INT 0x00000001 548 #define SYSCTL_VEVENT_VDDBO_NMI 0x00000002 549 #define SYSCTL_VEVENT_VDDBO_RST 0x00000003 550 551 //***************************************************************************** 552 // 553 // Values used with the SysCtlVoltageEventStatus() and 554 // SysCtlVoltageEventClear() APIs. 555 // 556 //***************************************************************************** 557 #define SYSCTL_VESTAT_VDDBOR 0x00000040 558 #define SYSCTL_VESTAT_VDDABOR 0x00000010 559 560 //***************************************************************************** 561 // 562 // Values used with the SysCtlNMIStatus() API. 563 // 564 //***************************************************************************** 565 #define SYSCTL_NMI_MOSCFAIL 0x00010000 566 #define SYSCTL_NMI_TAMPER 0x00000200 567 #define SYSCTL_NMI_WDT1 0x00000020 568 #define SYSCTL_NMI_WDT0 0x00000008 569 #define SYSCTL_NMI_POWER 0x00000004 570 #define SYSCTL_NMI_EXTERNAL 0x00000001 571 572 //***************************************************************************** 573 // 574 // The defines for the SysCtlClockOutConfig() API. 575 // 576 //***************************************************************************** 577 #define SYSCTL_CLKOUT_EN 0x80000000 578 #define SYSCTL_CLKOUT_DIS 0x00000000 579 #define SYSCTL_CLKOUT_SYSCLK 0x00000000 580 #define SYSCTL_CLKOUT_PIOSC 0x00010000 581 #define SYSCTL_CLKOUT_MOSC 0x00020000 582 583 //***************************************************************************** 584 // 585 // The following defines are used with the SysCtlAltClkConfig() function. 586 // 587 //***************************************************************************** 588 #define SYSCTL_ALTCLK_PIOSC 0x00000000 589 #define SYSCTL_ALTCLK_RTCOSC 0x00000003 590 #define SYSCTL_ALTCLK_LFIOSC 0x00000004 591 592 //***************************************************************************** 593 // 594 // Prototypes for the APIs. 595 // 596 //***************************************************************************** 597 extern uint32_t SysCtlSRAMSizeGet(void); 598 extern uint32_t SysCtlFlashSizeGet(void); 599 extern uint32_t SysCtlFlashSectorSizeGet(void); 600 extern bool SysCtlPeripheralPresent(uint32_t ui32Peripheral); 601 extern bool SysCtlPeripheralReady(uint32_t ui32Peripheral); 602 extern void SysCtlPeripheralPowerOn(uint32_t ui32Peripheral); 603 extern void SysCtlPeripheralPowerOff(uint32_t ui32Peripheral); 604 extern void SysCtlPeripheralReset(uint32_t ui32Peripheral); 605 extern void SysCtlPeripheralEnable(uint32_t ui32Peripheral); 606 extern void SysCtlPeripheralDisable(uint32_t ui32Peripheral); 607 extern void SysCtlPeripheralSleepEnable(uint32_t ui32Peripheral); 608 extern void SysCtlPeripheralSleepDisable(uint32_t ui32Peripheral); 609 extern void SysCtlPeripheralDeepSleepEnable(uint32_t ui32Peripheral); 610 extern void SysCtlPeripheralDeepSleepDisable(uint32_t ui32Peripheral); 611 extern void SysCtlPeripheralClockGating(bool bEnable); 612 extern void SysCtlIntRegister(void (*pfnHandler)(void)); 613 extern void SysCtlIntUnregister(void); 614 extern void SysCtlIntEnable(uint32_t ui32Ints); 615 extern void SysCtlIntDisable(uint32_t ui32Ints); 616 extern void SysCtlIntClear(uint32_t ui32Ints); 617 extern uint32_t SysCtlIntStatus(bool bMasked); 618 extern void SysCtlLDOSleepSet(uint32_t ui32Voltage); 619 extern uint32_t SysCtlLDOSleepGet(void); 620 extern void SysCtlLDODeepSleepSet(uint32_t ui32Voltage); 621 extern uint32_t SysCtlLDODeepSleepGet(void); 622 extern void SysCtlSleepPowerSet(uint32_t ui32Config); 623 extern void SysCtlDeepSleepPowerSet(uint32_t ui32Config); 624 extern void SysCtlReset(void); 625 extern void SysCtlSleep(void); 626 extern void SysCtlDeepSleep(void); 627 extern uint32_t SysCtlResetCauseGet(void); 628 extern void SysCtlResetCauseClear(uint32_t ui32Causes); 629 extern void SysCtlBrownOutConfigSet(uint32_t ui32Config, 630 uint32_t ui32Delay); 631 extern void SysCtlDelay(uint32_t ui32Count); 632 extern void SysCtlMOSCConfigSet(uint32_t ui32Config); 633 extern uint32_t SysCtlPIOSCCalibrate(uint32_t ui32Type); 634 extern void SysCtlClockSet(uint32_t ui32Config); 635 extern uint32_t SysCtlClockGet(void); 636 extern void SysCtlDeepSleepClockSet(uint32_t ui32Config); 637 extern void SysCtlDeepSleepClockConfigSet(uint32_t ui32Div, 638 uint32_t ui32Config); 639 extern void SysCtlPWMClockSet(uint32_t ui32Config); 640 extern uint32_t SysCtlPWMClockGet(void); 641 extern void SysCtlIOSCVerificationSet(bool bEnable); 642 extern void SysCtlMOSCVerificationSet(bool bEnable); 643 extern void SysCtlPLLVerificationSet(bool bEnable); 644 extern void SysCtlClkVerificationClear(void); 645 extern void SysCtlGPIOAHBEnable(uint32_t ui32GPIOPeripheral); 646 extern void SysCtlGPIOAHBDisable(uint32_t ui32GPIOPeripheral); 647 extern void SysCtlUSBPLLEnable(void); 648 extern void SysCtlUSBPLLDisable(void); 649 extern uint32_t SysCtlClockFreqSet(uint32_t ui32Config, 650 uint32_t ui32SysClock); 651 extern void SysCtlResetBehaviorSet(uint32_t ui32Behavior); 652 extern uint32_t SysCtlResetBehaviorGet(void); 653 extern void SysCtlClockOutConfig(uint32_t ui32Config, uint32_t ui32Div); 654 extern void SysCtlAltClkConfig(uint32_t ui32Config); 655 extern uint32_t SysCtlNMIStatus(void); 656 extern void SysCtlNMIClear(uint32_t ui32Status); 657 extern void SysCtlVoltageEventConfig(uint32_t ui32Config); 658 extern uint32_t SysCtlVoltageEventStatus(void); 659 extern void SysCtlVoltageEventClear(uint32_t ui32Status); 660 extern bool SysCtlVCOGet(uint32_t ui32Crystal, uint32_t *pui32VCOFrequency); 661 662 //***************************************************************************** 663 // 664 // Mark the end of the C bindings section for C++ compilers. 665 // 666 //***************************************************************************** 667 #ifdef __cplusplus 668 } 669 #endif 670 671 #endif // __DRIVERLIB_SYSCTL_H__ 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