1 //***************************************************************************** 2 // 3 // hw_des.h - Macros used when accessing the DES hardware. 4 // 5 // Copyright (c) 2012-2020 Texas Instruments Incorporated. All rights reserved. 6 // Software License Agreement 7 // 8 // Redistribution and use in source and binary forms, with or without 9 // modification, are permitted provided that the following conditions 10 // are met: 11 // 12 // Redistributions of source code must retain the above copyright 13 // notice, this list of conditions and the following disclaimer. 14 // 15 // Redistributions in binary form must reproduce the above copyright 16 // notice, this list of conditions and the following disclaimer in the 17 // documentation and/or other materials provided with the 18 // distribution. 19 // 20 // Neither the name of Texas Instruments Incorporated nor the names of 21 // its contributors may be used to endorse or promote products derived 22 // from this software without specific prior written permission. 23 // 24 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 27 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 28 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 29 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 30 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 34 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 // 36 // This is part of revision 2.2.0.295 of the Tiva Firmware Development Package. 37 // 38 //***************************************************************************** 39 40 #ifndef __HW_DES_H__ 41 #define __HW_DES_H__ 42 43 //***************************************************************************** 44 // 45 // The following are defines for the DES register offsets. 46 // 47 //***************************************************************************** 48 #define DES_O_KEY3_L 0x00000000 // DES Key 3 LSW for 192-Bit Key 49 #define DES_O_KEY3_H 0x00000004 // DES Key 3 MSW for 192-Bit Key 50 #define DES_O_KEY2_L 0x00000008 // DES Key 2 LSW for 128-Bit Key 51 #define DES_O_KEY2_H 0x0000000C // DES Key 2 MSW for 128-Bit Key 52 #define DES_O_KEY1_L 0x00000010 // DES Key 1 LSW for 64-Bit Key 53 #define DES_O_KEY1_H 0x00000014 // DES Key 1 MSW for 64-Bit Key 54 #define DES_O_IV_L 0x00000018 // DES Initialization Vector 55 #define DES_O_IV_H 0x0000001C // DES Initialization Vector 56 #define DES_O_CTRL 0x00000020 // DES Control 57 #define DES_O_LENGTH 0x00000024 // DES Cryptographic Data Length 58 #define DES_O_DATA_L 0x00000028 // DES LSW Data RW 59 #define DES_O_DATA_H 0x0000002C // DES MSW Data RW 60 #define DES_O_REVISION 0x00000030 // DES Revision Number 61 #define DES_O_SYSCONFIG 0x00000034 // DES System Configuration 62 #define DES_O_SYSSTATUS 0x00000038 // DES System Status 63 #define DES_O_IRQSTATUS 0x0000003C // DES Interrupt Status 64 #define DES_O_IRQENABLE 0x00000040 // DES Interrupt Enable 65 #define DES_O_DIRTYBITS 0x00000044 // DES Dirty Bits 66 #define DES_O_DMAIM 0xFFFF8030 // DES DMA Interrupt Mask 67 #define DES_O_DMARIS 0xFFFF8034 // DES DMA Raw Interrupt Status 68 #define DES_O_DMAMIS 0xFFFF8038 // DES DMA Masked Interrupt Status 69 #define DES_O_DMAIC 0xFFFF803C // DES DMA Interrupt Clear 70 71 //***************************************************************************** 72 // 73 // The following are defines for the bit fields in the DES_O_KEY3_L register. 74 // 75 //***************************************************************************** 76 #define DES_KEY3_L_KEY_M 0xFFFFFFFF // Key Data 77 #define DES_KEY3_L_KEY_S 0 78 79 //***************************************************************************** 80 // 81 // The following are defines for the bit fields in the DES_O_KEY3_H register. 82 // 83 //***************************************************************************** 84 #define DES_KEY3_H_KEY_M 0xFFFFFFFF // Key Data 85 #define DES_KEY3_H_KEY_S 0 86 87 //***************************************************************************** 88 // 89 // The following are defines for the bit fields in the DES_O_KEY2_L register. 90 // 91 //***************************************************************************** 92 #define DES_KEY2_L_KEY_M 0xFFFFFFFF // Key Data 93 #define DES_KEY2_L_KEY_S 0 94 95 //***************************************************************************** 96 // 97 // The following are defines for the bit fields in the DES_O_KEY2_H register. 98 // 99 //***************************************************************************** 100 #define DES_KEY2_H_KEY_M 0xFFFFFFFF // Key Data 101 #define DES_KEY2_H_KEY_S 0 102 103 //***************************************************************************** 104 // 105 // The following are defines for the bit fields in the DES_O_KEY1_L register. 106 // 107 //***************************************************************************** 108 #define DES_KEY1_L_KEY_M 0xFFFFFFFF // Key Data 109 #define DES_KEY1_L_KEY_S 0 110 111 //***************************************************************************** 112 // 113 // The following are defines for the bit fields in the DES_O_KEY1_H register. 114 // 115 //***************************************************************************** 116 #define DES_KEY1_H_KEY_M 0xFFFFFFFF // Key Data 117 #define DES_KEY1_H_KEY_S 0 118 119 //***************************************************************************** 120 // 121 // The following are defines for the bit fields in the DES_O_IV_L register. 122 // 123 //***************************************************************************** 124 #define DES_IV_L_M 0xFFFFFFFF // Initialization vector for CBC, 125 // CFB modes (LSW) 126 #define DES_IV_L_S 0 127 128 //***************************************************************************** 129 // 130 // The following are defines for the bit fields in the DES_O_IV_H register. 131 // 132 //***************************************************************************** 133 #define DES_IV_H_M 0xFFFFFFFF // Initialization vector for CBC, 134 // CFB modes (MSW) 135 #define DES_IV_H_S 0 136 137 //***************************************************************************** 138 // 139 // The following are defines for the bit fields in the DES_O_CTRL register. 140 // 141 //***************************************************************************** 142 #define DES_CTRL_CONTEXT 0x80000000 // If 1, this read-only status bit 143 // indicates that the context data 144 // registers can be overwritten and 145 // the host is permitted to write 146 // the next context 147 #define DES_CTRL_MODE_M 0x00000030 // Select CBC, ECB or CFB mode0x0: 148 // ECB mode0x1: CBC mode0x2: CFB 149 // mode0x3: reserved 150 #define DES_CTRL_TDES 0x00000008 // Select DES or triple DES 151 // encryption/decryption 152 #define DES_CTRL_DIRECTION 0x00000004 // Select encryption/decryption 153 // 0x0: decryption is selected0x1: 154 // Encryption is selected 155 #define DES_CTRL_INPUT_READY 0x00000002 // When 1, ready to encrypt/decrypt 156 // data 157 #define DES_CTRL_OUTPUT_READY 0x00000001 // When 1, Data decrypted/encrypted 158 // ready 159 #define DES_CTRL_MODE_S 4 160 161 //***************************************************************************** 162 // 163 // The following are defines for the bit fields in the DES_O_LENGTH register. 164 // 165 //***************************************************************************** 166 #define DES_LENGTH_M 0xFFFFFFFF // Cryptographic data length in 167 // bytes for all modes 168 #define DES_LENGTH_S 0 169 170 //***************************************************************************** 171 // 172 // The following are defines for the bit fields in the DES_O_DATA_L register. 173 // 174 //***************************************************************************** 175 #define DES_DATA_L_M 0xFFFFFFFF // Data for encryption/decryption, 176 // LSW 177 #define DES_DATA_L_S 0 178 179 //***************************************************************************** 180 // 181 // The following are defines for the bit fields in the DES_O_DATA_H register. 182 // 183 //***************************************************************************** 184 #define DES_DATA_H_M 0xFFFFFFFF // Data for encryption/decryption, 185 // MSW 186 #define DES_DATA_H_S 0 187 188 //***************************************************************************** 189 // 190 // The following are defines for the bit fields in the DES_O_REVISION register. 191 // 192 //***************************************************************************** 193 #define DES_REVISION_M 0xFFFFFFFF // Revision number 194 #define DES_REVISION_S 0 195 196 //***************************************************************************** 197 // 198 // The following are defines for the bit fields in the DES_O_SYSCONFIG 199 // register. 200 // 201 //***************************************************************************** 202 #define DES_SYSCONFIG_DMA_REQ_CONTEXT_IN_EN \ 203 0x00000080 // DMA Request Context In Enable 204 #define DES_SYSCONFIG_DMA_REQ_DATA_OUT_EN \ 205 0x00000040 // DMA Request Data Out Enable 206 #define DES_SYSCONFIG_DMA_REQ_DATA_IN_EN \ 207 0x00000020 // DMA Request Data In Enable 208 #define DES_SYSCONFIG_SIDLE_M 0x0000000C // Sidle mode 209 #define DES_SYSCONFIG_SIDLE_FORCE \ 210 0x00000000 // Force-idle mode 211 #define DES_SYSCONFIG_SOFTRESET 0x00000002 // Soft reset 212 213 //***************************************************************************** 214 // 215 // The following are defines for the bit fields in the DES_O_SYSSTATUS 216 // register. 217 // 218 //***************************************************************************** 219 #define DES_SYSSTATUS_RESETDONE 0x00000001 // Reset Done 220 221 //***************************************************************************** 222 // 223 // The following are defines for the bit fields in the DES_O_IRQSTATUS 224 // register. 225 // 226 //***************************************************************************** 227 #define DES_IRQSTATUS_DATA_OUT 0x00000004 // This bit indicates data output 228 // interrupt is active and triggers 229 // the interrupt output 230 #define DES_IRQSTATUS_DATA_IN 0x00000002 // This bit indicates data input 231 // interrupt is active and triggers 232 // the interrupt output 233 #define DES_IRQSTATUS_CONTEX_IN 0x00000001 // This bit indicates context 234 // interrupt is active and triggers 235 // the interrupt output 236 237 //***************************************************************************** 238 // 239 // The following are defines for the bit fields in the DES_O_IRQENABLE 240 // register. 241 // 242 //***************************************************************************** 243 #define DES_IRQENABLE_M_DATA_OUT \ 244 0x00000004 // If this bit is set to 1 the data 245 // output interrupt is enabled 246 #define DES_IRQENABLE_M_DATA_IN 0x00000002 // If this bit is set to 1 the data 247 // input interrupt is enabled 248 #define DES_IRQENABLE_M_CONTEX_IN \ 249 0x00000001 // If this bit is set to 1 the 250 // context interrupt is enabled 251 252 //***************************************************************************** 253 // 254 // The following are defines for the bit fields in the DES_O_DIRTYBITS 255 // register. 256 // 257 //***************************************************************************** 258 #define DES_DIRTYBITS_S_DIRTY 0x00000002 // This bit is set to 1 by the 259 // module if any of the DES_* 260 // registers is written 261 #define DES_DIRTYBITS_S_ACCESS 0x00000001 // This bit is set to 1 by the 262 // module if any of the DES_* 263 // registers is read 264 265 //***************************************************************************** 266 // 267 // The following are defines for the bit fields in the DES_O_DMAIM register. 268 // 269 //***************************************************************************** 270 #define DES_DMAIM_DOUT 0x00000004 // Data Out DMA Done Interrupt Mask 271 #define DES_DMAIM_DIN 0x00000002 // Data In DMA Done Interrupt Mask 272 #define DES_DMAIM_CIN 0x00000001 // Context In DMA Done Interrupt 273 // Mask 274 275 //***************************************************************************** 276 // 277 // The following are defines for the bit fields in the DES_O_DMARIS register. 278 // 279 //***************************************************************************** 280 #define DES_DMARIS_DOUT 0x00000004 // Data Out DMA Done Raw Interrupt 281 // Status 282 #define DES_DMARIS_DIN 0x00000002 // Data In DMA Done Raw Interrupt 283 // Status 284 #define DES_DMARIS_CIN 0x00000001 // Context In DMA Done Raw 285 // Interrupt Status 286 287 //***************************************************************************** 288 // 289 // The following are defines for the bit fields in the DES_O_DMAMIS register. 290 // 291 //***************************************************************************** 292 #define DES_DMAMIS_DOUT 0x00000004 // Data Out DMA Done Masked 293 // Interrupt Status 294 #define DES_DMAMIS_DIN 0x00000002 // Data In DMA Done Masked 295 // Interrupt Status 296 #define DES_DMAMIS_CIN 0x00000001 // Context In DMA Done Raw 297 // Interrupt Status 298 299 //***************************************************************************** 300 // 301 // The following are defines for the bit fields in the DES_O_DMAIC register. 302 // 303 //***************************************************************************** 304 #define DES_DMAIC_DOUT 0x00000004 // Data Out DMA Done Interrupt 305 // Clear 306 #define DES_DMAIC_DIN 0x00000002 // Data In DMA Done Interrupt Clear 307 #define DES_DMAIC_CIN 0x00000001 // Context In DMA Done Raw 308 // Interrupt Status 309 310 #endif // __HW_DES_H__ 311