1 //***************************************************************************** 2 // 3 // hw_nvic.h - Macros used when accessing the NVIC hardware. 4 // 5 // Copyright (c) 2005-2020 Texas Instruments Incorporated. All rights reserved. 6 // Software License Agreement 7 // 8 // Redistribution and use in source and binary forms, with or without 9 // modification, are permitted provided that the following conditions 10 // are met: 11 // 12 // Redistributions of source code must retain the above copyright 13 // notice, this list of conditions and the following disclaimer. 14 // 15 // Redistributions in binary form must reproduce the above copyright 16 // notice, this list of conditions and the following disclaimer in the 17 // documentation and/or other materials provided with the 18 // distribution. 19 // 20 // Neither the name of Texas Instruments Incorporated nor the names of 21 // its contributors may be used to endorse or promote products derived 22 // from this software without specific prior written permission. 23 // 24 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 27 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 28 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 29 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 30 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 34 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 // 36 // This is part of revision 2.2.0.295 of the Tiva Firmware Development Package. 37 // 38 //***************************************************************************** 39 40 #ifndef __HW_NVIC_H__ 41 #define __HW_NVIC_H__ 42 43 //***************************************************************************** 44 // 45 // The following are defines for the NVIC register addresses. 46 // 47 //***************************************************************************** 48 #define NVIC_ACTLR 0xE000E008 // Auxiliary Control 49 #define NVIC_ST_CTRL 0xE000E010 // SysTick Control and Status 50 // Register 51 #define NVIC_ST_RELOAD 0xE000E014 // SysTick Reload Value Register 52 #define NVIC_ST_CURRENT 0xE000E018 // SysTick Current Value Register 53 #define NVIC_EN0 0xE000E100 // Interrupt 0-31 Set Enable 54 #define NVIC_EN1 0xE000E104 // Interrupt 32-63 Set Enable 55 #define NVIC_EN2 0xE000E108 // Interrupt 64-95 Set Enable 56 #define NVIC_EN3 0xE000E10C // Interrupt 96-127 Set Enable 57 #define NVIC_EN4 0xE000E110 // Interrupt 128-159 Set Enable 58 #define NVIC_DIS0 0xE000E180 // Interrupt 0-31 Clear Enable 59 #define NVIC_DIS1 0xE000E184 // Interrupt 32-63 Clear Enable 60 #define NVIC_DIS2 0xE000E188 // Interrupt 64-95 Clear Enable 61 #define NVIC_DIS3 0xE000E18C // Interrupt 96-127 Clear Enable 62 #define NVIC_DIS4 0xE000E190 // Interrupt 128-159 Clear Enable 63 #define NVIC_PEND0 0xE000E200 // Interrupt 0-31 Set Pending 64 #define NVIC_PEND1 0xE000E204 // Interrupt 32-63 Set Pending 65 #define NVIC_PEND2 0xE000E208 // Interrupt 64-95 Set Pending 66 #define NVIC_PEND3 0xE000E20C // Interrupt 96-127 Set Pending 67 #define NVIC_PEND4 0xE000E210 // Interrupt 128-159 Set Pending 68 #define NVIC_UNPEND0 0xE000E280 // Interrupt 0-31 Clear Pending 69 #define NVIC_UNPEND1 0xE000E284 // Interrupt 32-63 Clear Pending 70 #define NVIC_UNPEND2 0xE000E288 // Interrupt 64-95 Clear Pending 71 #define NVIC_UNPEND3 0xE000E28C // Interrupt 96-127 Clear Pending 72 #define NVIC_UNPEND4 0xE000E290 // Interrupt 128-159 Clear Pending 73 #define NVIC_ACTIVE0 0xE000E300 // Interrupt 0-31 Active Bit 74 #define NVIC_ACTIVE1 0xE000E304 // Interrupt 32-63 Active Bit 75 #define NVIC_ACTIVE2 0xE000E308 // Interrupt 64-95 Active Bit 76 #define NVIC_ACTIVE3 0xE000E30C // Interrupt 96-127 Active Bit 77 #define NVIC_ACTIVE4 0xE000E310 // Interrupt 128-159 Active Bit 78 #define NVIC_PRI0 0xE000E400 // Interrupt 0-3 Priority 79 #define NVIC_PRI1 0xE000E404 // Interrupt 4-7 Priority 80 #define NVIC_PRI2 0xE000E408 // Interrupt 8-11 Priority 81 #define NVIC_PRI3 0xE000E40C // Interrupt 12-15 Priority 82 #define NVIC_PRI4 0xE000E410 // Interrupt 16-19 Priority 83 #define NVIC_PRI5 0xE000E414 // Interrupt 20-23 Priority 84 #define NVIC_PRI6 0xE000E418 // Interrupt 24-27 Priority 85 #define NVIC_PRI7 0xE000E41C // Interrupt 28-31 Priority 86 #define NVIC_PRI8 0xE000E420 // Interrupt 32-35 Priority 87 #define NVIC_PRI9 0xE000E424 // Interrupt 36-39 Priority 88 #define NVIC_PRI10 0xE000E428 // Interrupt 40-43 Priority 89 #define NVIC_PRI11 0xE000E42C // Interrupt 44-47 Priority 90 #define NVIC_PRI12 0xE000E430 // Interrupt 48-51 Priority 91 #define NVIC_PRI13 0xE000E434 // Interrupt 52-55 Priority 92 #define NVIC_PRI14 0xE000E438 // Interrupt 56-59 Priority 93 #define NVIC_PRI15 0xE000E43C // Interrupt 60-63 Priority 94 #define NVIC_PRI16 0xE000E440 // Interrupt 64-67 Priority 95 #define NVIC_PRI17 0xE000E444 // Interrupt 68-71 Priority 96 #define NVIC_PRI18 0xE000E448 // Interrupt 72-75 Priority 97 #define NVIC_PRI19 0xE000E44C // Interrupt 76-79 Priority 98 #define NVIC_PRI20 0xE000E450 // Interrupt 80-83 Priority 99 #define NVIC_PRI21 0xE000E454 // Interrupt 84-87 Priority 100 #define NVIC_PRI22 0xE000E458 // Interrupt 88-91 Priority 101 #define NVIC_PRI23 0xE000E45C // Interrupt 92-95 Priority 102 #define NVIC_PRI24 0xE000E460 // Interrupt 96-99 Priority 103 #define NVIC_PRI25 0xE000E464 // Interrupt 100-103 Priority 104 #define NVIC_PRI26 0xE000E468 // Interrupt 104-107 Priority 105 #define NVIC_PRI27 0xE000E46C // Interrupt 108-111 Priority 106 #define NVIC_PRI28 0xE000E470 // Interrupt 112-115 Priority 107 #define NVIC_PRI29 0xE000E474 // Interrupt 116-119 Priority 108 #define NVIC_PRI30 0xE000E478 // Interrupt 120-123 Priority 109 #define NVIC_PRI31 0xE000E47C // Interrupt 124-127 Priority 110 #define NVIC_PRI32 0xE000E480 // Interrupt 128-131 Priority 111 #define NVIC_PRI33 0xE000E484 // Interrupt 132-135 Priority 112 #define NVIC_PRI34 0xE000E488 // Interrupt 136-139 Priority 113 #define NVIC_CPUID 0xE000ED00 // CPU ID Base 114 #define NVIC_INT_CTRL 0xE000ED04 // Interrupt Control and State 115 #define NVIC_VTABLE 0xE000ED08 // Vector Table Offset 116 #define NVIC_APINT 0xE000ED0C // Application Interrupt and Reset 117 // Control 118 #define NVIC_SYS_CTRL 0xE000ED10 // System Control 119 #define NVIC_CFG_CTRL 0xE000ED14 // Configuration and Control 120 #define NVIC_SYS_PRI1 0xE000ED18 // System Handler Priority 1 121 #define NVIC_SYS_PRI2 0xE000ED1C // System Handler Priority 2 122 #define NVIC_SYS_PRI3 0xE000ED20 // System Handler Priority 3 123 #define NVIC_SYS_HND_CTRL 0xE000ED24 // System Handler Control and State 124 #define NVIC_FAULT_STAT 0xE000ED28 // Configurable Fault Status 125 #define NVIC_HFAULT_STAT 0xE000ED2C // Hard Fault Status 126 #define NVIC_DEBUG_STAT 0xE000ED30 // Debug Status Register 127 #define NVIC_MM_ADDR 0xE000ED34 // Memory Management Fault Address 128 #define NVIC_FAULT_ADDR 0xE000ED38 // Bus Fault Address 129 #define NVIC_CPAC 0xE000ED88 // Coprocessor Access Control 130 #define NVIC_MPU_TYPE 0xE000ED90 // MPU Type 131 #define NVIC_MPU_CTRL 0xE000ED94 // MPU Control 132 #define NVIC_MPU_NUMBER 0xE000ED98 // MPU Region Number 133 #define NVIC_MPU_BASE 0xE000ED9C // MPU Region Base Address 134 #define NVIC_MPU_ATTR 0xE000EDA0 // MPU Region Attribute and Size 135 #define NVIC_MPU_BASE1 0xE000EDA4 // MPU Region Base Address Alias 1 136 #define NVIC_MPU_ATTR1 0xE000EDA8 // MPU Region Attribute and Size 137 // Alias 1 138 #define NVIC_MPU_BASE2 0xE000EDAC // MPU Region Base Address Alias 2 139 #define NVIC_MPU_ATTR2 0xE000EDB0 // MPU Region Attribute and Size 140 // Alias 2 141 #define NVIC_MPU_BASE3 0xE000EDB4 // MPU Region Base Address Alias 3 142 #define NVIC_MPU_ATTR3 0xE000EDB8 // MPU Region Attribute and Size 143 // Alias 3 144 #define NVIC_DBG_CTRL 0xE000EDF0 // Debug Control and Status Reg 145 #define NVIC_DBG_XFER 0xE000EDF4 // Debug Core Reg. Transfer Select 146 #define NVIC_DBG_DATA 0xE000EDF8 // Debug Core Register Data 147 #define NVIC_DBG_INT 0xE000EDFC // Debug Reset Interrupt Control 148 #define NVIC_SW_TRIG 0xE000EF00 // Software Trigger Interrupt 149 #define NVIC_FPCC 0xE000EF34 // Floating-Point Context Control 150 #define NVIC_FPCA 0xE000EF38 // Floating-Point Context Address 151 #define NVIC_FPDSC 0xE000EF3C // Floating-Point Default Status 152 // Control 153 154 //***************************************************************************** 155 // 156 // The following are defines for the bit fields in the NVIC_ACTLR register. 157 // 158 //***************************************************************************** 159 #define NVIC_ACTLR_DISOOFP 0x00000200 // Disable Out-Of-Order Floating 160 // Point 161 #define NVIC_ACTLR_DISFPCA 0x00000100 // Disable CONTROL 162 #define NVIC_ACTLR_DISFOLD 0x00000004 // Disable IT Folding 163 #define NVIC_ACTLR_DISWBUF 0x00000002 // Disable Write Buffer 164 #define NVIC_ACTLR_DISMCYC 0x00000001 // Disable Interrupts of Multiple 165 // Cycle Instructions 166 167 //***************************************************************************** 168 // 169 // The following are defines for the bit fields in the NVIC_ST_CTRL register. 170 // 171 //***************************************************************************** 172 #define NVIC_ST_CTRL_COUNT 0x00010000 // Count Flag 173 #define NVIC_ST_CTRL_CLK_SRC 0x00000004 // Clock Source 174 #define NVIC_ST_CTRL_INTEN 0x00000002 // Interrupt Enable 175 #define NVIC_ST_CTRL_ENABLE 0x00000001 // Enable 176 177 //***************************************************************************** 178 // 179 // The following are defines for the bit fields in the NVIC_ST_RELOAD register. 180 // 181 //***************************************************************************** 182 #define NVIC_ST_RELOAD_M 0x00FFFFFF // Reload Value 183 #define NVIC_ST_RELOAD_S 0 184 185 //***************************************************************************** 186 // 187 // The following are defines for the bit fields in the NVIC_ST_CURRENT 188 // register. 189 // 190 //***************************************************************************** 191 #define NVIC_ST_CURRENT_M 0x00FFFFFF // Current Value 192 #define NVIC_ST_CURRENT_S 0 193 194 //***************************************************************************** 195 // 196 // The following are defines for the bit fields in the NVIC_EN0 register. 197 // 198 //***************************************************************************** 199 #define NVIC_EN0_INT_M 0xFFFFFFFF // Interrupt Enable 200 201 //***************************************************************************** 202 // 203 // The following are defines for the bit fields in the NVIC_EN1 register. 204 // 205 //***************************************************************************** 206 #define NVIC_EN1_INT_M 0xFFFFFFFF // Interrupt Enable 207 208 //***************************************************************************** 209 // 210 // The following are defines for the bit fields in the NVIC_EN2 register. 211 // 212 //***************************************************************************** 213 #define NVIC_EN2_INT_M 0xFFFFFFFF // Interrupt Enable 214 215 //***************************************************************************** 216 // 217 // The following are defines for the bit fields in the NVIC_EN3 register. 218 // 219 //***************************************************************************** 220 #define NVIC_EN3_INT_M 0xFFFFFFFF // Interrupt Enable 221 222 //***************************************************************************** 223 // 224 // The following are defines for the bit fields in the NVIC_EN4 register. 225 // 226 //***************************************************************************** 227 #define NVIC_EN4_INT_M 0x000007FF // Interrupt Enable 228 229 //***************************************************************************** 230 // 231 // The following are defines for the bit fields in the NVIC_DIS0 register. 232 // 233 //***************************************************************************** 234 #define NVIC_DIS0_INT_M 0xFFFFFFFF // Interrupt Disable 235 236 //***************************************************************************** 237 // 238 // The following are defines for the bit fields in the NVIC_DIS1 register. 239 // 240 //***************************************************************************** 241 #define NVIC_DIS1_INT_M 0xFFFFFFFF // Interrupt Disable 242 243 //***************************************************************************** 244 // 245 // The following are defines for the bit fields in the NVIC_DIS2 register. 246 // 247 //***************************************************************************** 248 #define NVIC_DIS2_INT_M 0xFFFFFFFF // Interrupt Disable 249 250 //***************************************************************************** 251 // 252 // The following are defines for the bit fields in the NVIC_DIS3 register. 253 // 254 //***************************************************************************** 255 #define NVIC_DIS3_INT_M 0xFFFFFFFF // Interrupt Disable 256 257 //***************************************************************************** 258 // 259 // The following are defines for the bit fields in the NVIC_DIS4 register. 260 // 261 //***************************************************************************** 262 #define NVIC_DIS4_INT_M 0x000007FF // Interrupt Disable 263 264 //***************************************************************************** 265 // 266 // The following are defines for the bit fields in the NVIC_PEND0 register. 267 // 268 //***************************************************************************** 269 #define NVIC_PEND0_INT_M 0xFFFFFFFF // Interrupt Set Pending 270 271 //***************************************************************************** 272 // 273 // The following are defines for the bit fields in the NVIC_PEND1 register. 274 // 275 //***************************************************************************** 276 #define NVIC_PEND1_INT_M 0xFFFFFFFF // Interrupt Set Pending 277 278 //***************************************************************************** 279 // 280 // The following are defines for the bit fields in the NVIC_PEND2 register. 281 // 282 //***************************************************************************** 283 #define NVIC_PEND2_INT_M 0xFFFFFFFF // Interrupt Set Pending 284 285 //***************************************************************************** 286 // 287 // The following are defines for the bit fields in the NVIC_PEND3 register. 288 // 289 //***************************************************************************** 290 #define NVIC_PEND3_INT_M 0xFFFFFFFF // Interrupt Set Pending 291 292 //***************************************************************************** 293 // 294 // The following are defines for the bit fields in the NVIC_PEND4 register. 295 // 296 //***************************************************************************** 297 #define NVIC_PEND4_INT_M 0x000007FF // Interrupt Set Pending 298 299 //***************************************************************************** 300 // 301 // The following are defines for the bit fields in the NVIC_UNPEND0 register. 302 // 303 //***************************************************************************** 304 #define NVIC_UNPEND0_INT_M 0xFFFFFFFF // Interrupt Clear Pending 305 306 //***************************************************************************** 307 // 308 // The following are defines for the bit fields in the NVIC_UNPEND1 register. 309 // 310 //***************************************************************************** 311 #define NVIC_UNPEND1_INT_M 0xFFFFFFFF // Interrupt Clear Pending 312 313 //***************************************************************************** 314 // 315 // The following are defines for the bit fields in the NVIC_UNPEND2 register. 316 // 317 //***************************************************************************** 318 #define NVIC_UNPEND2_INT_M 0xFFFFFFFF // Interrupt Clear Pending 319 320 //***************************************************************************** 321 // 322 // The following are defines for the bit fields in the NVIC_UNPEND3 register. 323 // 324 //***************************************************************************** 325 #define NVIC_UNPEND3_INT_M 0xFFFFFFFF // Interrupt Clear Pending 326 327 //***************************************************************************** 328 // 329 // The following are defines for the bit fields in the NVIC_UNPEND4 register. 330 // 331 //***************************************************************************** 332 #define NVIC_UNPEND4_INT_M 0x000007FF // Interrupt Clear Pending 333 334 //***************************************************************************** 335 // 336 // The following are defines for the bit fields in the NVIC_ACTIVE0 register. 337 // 338 //***************************************************************************** 339 #define NVIC_ACTIVE0_INT_M 0xFFFFFFFF // Interrupt Active 340 341 //***************************************************************************** 342 // 343 // The following are defines for the bit fields in the NVIC_ACTIVE1 register. 344 // 345 //***************************************************************************** 346 #define NVIC_ACTIVE1_INT_M 0xFFFFFFFF // Interrupt Active 347 348 //***************************************************************************** 349 // 350 // The following are defines for the bit fields in the NVIC_ACTIVE2 register. 351 // 352 //***************************************************************************** 353 #define NVIC_ACTIVE2_INT_M 0xFFFFFFFF // Interrupt Active 354 355 //***************************************************************************** 356 // 357 // The following are defines for the bit fields in the NVIC_ACTIVE3 register. 358 // 359 //***************************************************************************** 360 #define NVIC_ACTIVE3_INT_M 0xFFFFFFFF // Interrupt Active 361 362 //***************************************************************************** 363 // 364 // The following are defines for the bit fields in the NVIC_ACTIVE4 register. 365 // 366 //***************************************************************************** 367 #define NVIC_ACTIVE4_INT_M 0x000007FF // Interrupt Active 368 369 //***************************************************************************** 370 // 371 // The following are defines for the bit fields in the NVIC_PRI0 register. 372 // 373 //***************************************************************************** 374 #define NVIC_PRI0_INT3_M 0xE0000000 // Interrupt 3 Priority Mask 375 #define NVIC_PRI0_INT2_M 0x00E00000 // Interrupt 2 Priority Mask 376 #define NVIC_PRI0_INT1_M 0x0000E000 // Interrupt 1 Priority Mask 377 #define NVIC_PRI0_INT0_M 0x000000E0 // Interrupt 0 Priority Mask 378 #define NVIC_PRI0_INT3_S 29 379 #define NVIC_PRI0_INT2_S 21 380 #define NVIC_PRI0_INT1_S 13 381 #define NVIC_PRI0_INT0_S 5 382 383 //***************************************************************************** 384 // 385 // The following are defines for the bit fields in the NVIC_PRI1 register. 386 // 387 //***************************************************************************** 388 #define NVIC_PRI1_INT7_M 0xE0000000 // Interrupt 7 Priority Mask 389 #define NVIC_PRI1_INT6_M 0x00E00000 // Interrupt 6 Priority Mask 390 #define NVIC_PRI1_INT5_M 0x0000E000 // Interrupt 5 Priority Mask 391 #define NVIC_PRI1_INT4_M 0x000000E0 // Interrupt 4 Priority Mask 392 #define NVIC_PRI1_INT7_S 29 393 #define NVIC_PRI1_INT6_S 21 394 #define NVIC_PRI1_INT5_S 13 395 #define NVIC_PRI1_INT4_S 5 396 397 //***************************************************************************** 398 // 399 // The following are defines for the bit fields in the NVIC_PRI2 register. 400 // 401 //***************************************************************************** 402 #define NVIC_PRI2_INT11_M 0xE0000000 // Interrupt 11 Priority Mask 403 #define NVIC_PRI2_INT10_M 0x00E00000 // Interrupt 10 Priority Mask 404 #define NVIC_PRI2_INT9_M 0x0000E000 // Interrupt 9 Priority Mask 405 #define NVIC_PRI2_INT8_M 0x000000E0 // Interrupt 8 Priority Mask 406 #define NVIC_PRI2_INT11_S 29 407 #define NVIC_PRI2_INT10_S 21 408 #define NVIC_PRI2_INT9_S 13 409 #define NVIC_PRI2_INT8_S 5 410 411 //***************************************************************************** 412 // 413 // The following are defines for the bit fields in the NVIC_PRI3 register. 414 // 415 //***************************************************************************** 416 #define NVIC_PRI3_INT15_M 0xE0000000 // Interrupt 15 Priority Mask 417 #define NVIC_PRI3_INT14_M 0x00E00000 // Interrupt 14 Priority Mask 418 #define NVIC_PRI3_INT13_M 0x0000E000 // Interrupt 13 Priority Mask 419 #define NVIC_PRI3_INT12_M 0x000000E0 // Interrupt 12 Priority Mask 420 #define NVIC_PRI3_INT15_S 29 421 #define NVIC_PRI3_INT14_S 21 422 #define NVIC_PRI3_INT13_S 13 423 #define NVIC_PRI3_INT12_S 5 424 425 //***************************************************************************** 426 // 427 // The following are defines for the bit fields in the NVIC_PRI4 register. 428 // 429 //***************************************************************************** 430 #define NVIC_PRI4_INT19_M 0xE0000000 // Interrupt 19 Priority Mask 431 #define NVIC_PRI4_INT18_M 0x00E00000 // Interrupt 18 Priority Mask 432 #define NVIC_PRI4_INT17_M 0x0000E000 // Interrupt 17 Priority Mask 433 #define NVIC_PRI4_INT16_M 0x000000E0 // Interrupt 16 Priority Mask 434 #define NVIC_PRI4_INT19_S 29 435 #define NVIC_PRI4_INT18_S 21 436 #define NVIC_PRI4_INT17_S 13 437 #define NVIC_PRI4_INT16_S 5 438 439 //***************************************************************************** 440 // 441 // The following are defines for the bit fields in the NVIC_PRI5 register. 442 // 443 //***************************************************************************** 444 #define NVIC_PRI5_INT23_M 0xE0000000 // Interrupt 23 Priority Mask 445 #define NVIC_PRI5_INT22_M 0x00E00000 // Interrupt 22 Priority Mask 446 #define NVIC_PRI5_INT21_M 0x0000E000 // Interrupt 21 Priority Mask 447 #define NVIC_PRI5_INT20_M 0x000000E0 // Interrupt 20 Priority Mask 448 #define NVIC_PRI5_INT23_S 29 449 #define NVIC_PRI5_INT22_S 21 450 #define NVIC_PRI5_INT21_S 13 451 #define NVIC_PRI5_INT20_S 5 452 453 //***************************************************************************** 454 // 455 // The following are defines for the bit fields in the NVIC_PRI6 register. 456 // 457 //***************************************************************************** 458 #define NVIC_PRI6_INT27_M 0xE0000000 // Interrupt 27 Priority Mask 459 #define NVIC_PRI6_INT26_M 0x00E00000 // Interrupt 26 Priority Mask 460 #define NVIC_PRI6_INT25_M 0x0000E000 // Interrupt 25 Priority Mask 461 #define NVIC_PRI6_INT24_M 0x000000E0 // Interrupt 24 Priority Mask 462 #define NVIC_PRI6_INT27_S 29 463 #define NVIC_PRI6_INT26_S 21 464 #define NVIC_PRI6_INT25_S 13 465 #define NVIC_PRI6_INT24_S 5 466 467 //***************************************************************************** 468 // 469 // The following are defines for the bit fields in the NVIC_PRI7 register. 470 // 471 //***************************************************************************** 472 #define NVIC_PRI7_INT31_M 0xE0000000 // Interrupt 31 Priority Mask 473 #define NVIC_PRI7_INT30_M 0x00E00000 // Interrupt 30 Priority Mask 474 #define NVIC_PRI7_INT29_M 0x0000E000 // Interrupt 29 Priority Mask 475 #define NVIC_PRI7_INT28_M 0x000000E0 // Interrupt 28 Priority Mask 476 #define NVIC_PRI7_INT31_S 29 477 #define NVIC_PRI7_INT30_S 21 478 #define NVIC_PRI7_INT29_S 13 479 #define NVIC_PRI7_INT28_S 5 480 481 //***************************************************************************** 482 // 483 // The following are defines for the bit fields in the NVIC_PRI8 register. 484 // 485 //***************************************************************************** 486 #define NVIC_PRI8_INT35_M 0xE0000000 // Interrupt 35 Priority Mask 487 #define NVIC_PRI8_INT34_M 0x00E00000 // Interrupt 34 Priority Mask 488 #define NVIC_PRI8_INT33_M 0x0000E000 // Interrupt 33 Priority Mask 489 #define NVIC_PRI8_INT32_M 0x000000E0 // Interrupt 32 Priority Mask 490 #define NVIC_PRI8_INT35_S 29 491 #define NVIC_PRI8_INT34_S 21 492 #define NVIC_PRI8_INT33_S 13 493 #define NVIC_PRI8_INT32_S 5 494 495 //***************************************************************************** 496 // 497 // The following are defines for the bit fields in the NVIC_PRI9 register. 498 // 499 //***************************************************************************** 500 #define NVIC_PRI9_INT39_M 0xE0000000 // Interrupt 39 Priority Mask 501 #define NVIC_PRI9_INT38_M 0x00E00000 // Interrupt 38 Priority Mask 502 #define NVIC_PRI9_INT37_M 0x0000E000 // Interrupt 37 Priority Mask 503 #define NVIC_PRI9_INT36_M 0x000000E0 // Interrupt 36 Priority Mask 504 #define NVIC_PRI9_INT39_S 29 505 #define NVIC_PRI9_INT38_S 21 506 #define NVIC_PRI9_INT37_S 13 507 #define NVIC_PRI9_INT36_S 5 508 509 //***************************************************************************** 510 // 511 // The following are defines for the bit fields in the NVIC_PRI10 register. 512 // 513 //***************************************************************************** 514 #define NVIC_PRI10_INT43_M 0xE0000000 // Interrupt 43 Priority Mask 515 #define NVIC_PRI10_INT42_M 0x00E00000 // Interrupt 42 Priority Mask 516 #define NVIC_PRI10_INT41_M 0x0000E000 // Interrupt 41 Priority Mask 517 #define NVIC_PRI10_INT40_M 0x000000E0 // Interrupt 40 Priority Mask 518 #define NVIC_PRI10_INT43_S 29 519 #define NVIC_PRI10_INT42_S 21 520 #define NVIC_PRI10_INT41_S 13 521 #define NVIC_PRI10_INT40_S 5 522 523 //***************************************************************************** 524 // 525 // The following are defines for the bit fields in the NVIC_PRI11 register. 526 // 527 //***************************************************************************** 528 #define NVIC_PRI11_INT47_M 0xE0000000 // Interrupt 47 Priority Mask 529 #define NVIC_PRI11_INT46_M 0x00E00000 // Interrupt 46 Priority Mask 530 #define NVIC_PRI11_INT45_M 0x0000E000 // Interrupt 45 Priority Mask 531 #define NVIC_PRI11_INT44_M 0x000000E0 // Interrupt 44 Priority Mask 532 #define NVIC_PRI11_INT47_S 29 533 #define NVIC_PRI11_INT46_S 21 534 #define NVIC_PRI11_INT45_S 13 535 #define NVIC_PRI11_INT44_S 5 536 537 //***************************************************************************** 538 // 539 // The following are defines for the bit fields in the NVIC_PRI12 register. 540 // 541 //***************************************************************************** 542 #define NVIC_PRI12_INT51_M 0xE0000000 // Interrupt 51 Priority Mask 543 #define NVIC_PRI12_INT50_M 0x00E00000 // Interrupt 50 Priority Mask 544 #define NVIC_PRI12_INT49_M 0x0000E000 // Interrupt 49 Priority Mask 545 #define NVIC_PRI12_INT48_M 0x000000E0 // Interrupt 48 Priority Mask 546 #define NVIC_PRI12_INT51_S 29 547 #define NVIC_PRI12_INT50_S 21 548 #define NVIC_PRI12_INT49_S 13 549 #define NVIC_PRI12_INT48_S 5 550 551 //***************************************************************************** 552 // 553 // The following are defines for the bit fields in the NVIC_PRI13 register. 554 // 555 //***************************************************************************** 556 #define NVIC_PRI13_INT55_M 0xE0000000 // Interrupt 55 Priority Mask 557 #define NVIC_PRI13_INT54_M 0x00E00000 // Interrupt 54 Priority Mask 558 #define NVIC_PRI13_INT53_M 0x0000E000 // Interrupt 53 Priority Mask 559 #define NVIC_PRI13_INT52_M 0x000000E0 // Interrupt 52 Priority Mask 560 #define NVIC_PRI13_INT55_S 29 561 #define NVIC_PRI13_INT54_S 21 562 #define NVIC_PRI13_INT53_S 13 563 #define NVIC_PRI13_INT52_S 5 564 565 //***************************************************************************** 566 // 567 // The following are defines for the bit fields in the NVIC_PRI14 register. 568 // 569 //***************************************************************************** 570 #define NVIC_PRI14_INTD_M 0xE0000000 // Interrupt 59 Priority Mask 571 #define NVIC_PRI14_INTC_M 0x00E00000 // Interrupt 58 Priority Mask 572 #define NVIC_PRI14_INTB_M 0x0000E000 // Interrupt 57 Priority Mask 573 #define NVIC_PRI14_INTA_M 0x000000E0 // Interrupt 56 Priority Mask 574 #define NVIC_PRI14_INTD_S 29 575 #define NVIC_PRI14_INTC_S 21 576 #define NVIC_PRI14_INTB_S 13 577 #define NVIC_PRI14_INTA_S 5 578 579 //***************************************************************************** 580 // 581 // The following are defines for the bit fields in the NVIC_PRI15 register. 582 // 583 //***************************************************************************** 584 #define NVIC_PRI15_INTD_M 0xE0000000 // Interrupt 63 Priority Mask 585 #define NVIC_PRI15_INTC_M 0x00E00000 // Interrupt 62 Priority Mask 586 #define NVIC_PRI15_INTB_M 0x0000E000 // Interrupt 61 Priority Mask 587 #define NVIC_PRI15_INTA_M 0x000000E0 // Interrupt 60 Priority Mask 588 #define NVIC_PRI15_INTD_S 29 589 #define NVIC_PRI15_INTC_S 21 590 #define NVIC_PRI15_INTB_S 13 591 #define NVIC_PRI15_INTA_S 5 592 593 //***************************************************************************** 594 // 595 // The following are defines for the bit fields in the NVIC_PRI16 register. 596 // 597 //***************************************************************************** 598 #define NVIC_PRI16_INTD_M 0xE0000000 // Interrupt 67 Priority Mask 599 #define NVIC_PRI16_INTC_M 0x00E00000 // Interrupt 66 Priority Mask 600 #define NVIC_PRI16_INTB_M 0x0000E000 // Interrupt 65 Priority Mask 601 #define NVIC_PRI16_INTA_M 0x000000E0 // Interrupt 64 Priority Mask 602 #define NVIC_PRI16_INTD_S 29 603 #define NVIC_PRI16_INTC_S 21 604 #define NVIC_PRI16_INTB_S 13 605 #define NVIC_PRI16_INTA_S 5 606 607 //***************************************************************************** 608 // 609 // The following are defines for the bit fields in the NVIC_PRI17 register. 610 // 611 //***************************************************************************** 612 #define NVIC_PRI17_INTD_M 0xE0000000 // Interrupt 71 Priority Mask 613 #define NVIC_PRI17_INTC_M 0x00E00000 // Interrupt 70 Priority Mask 614 #define NVIC_PRI17_INTB_M 0x0000E000 // Interrupt 69 Priority Mask 615 #define NVIC_PRI17_INTA_M 0x000000E0 // Interrupt 68 Priority Mask 616 #define NVIC_PRI17_INTD_S 29 617 #define NVIC_PRI17_INTC_S 21 618 #define NVIC_PRI17_INTB_S 13 619 #define NVIC_PRI17_INTA_S 5 620 621 //***************************************************************************** 622 // 623 // The following are defines for the bit fields in the NVIC_PRI18 register. 624 // 625 //***************************************************************************** 626 #define NVIC_PRI18_INTD_M 0xE0000000 // Interrupt 75 Priority Mask 627 #define NVIC_PRI18_INTC_M 0x00E00000 // Interrupt 74 Priority Mask 628 #define NVIC_PRI18_INTB_M 0x0000E000 // Interrupt 73 Priority Mask 629 #define NVIC_PRI18_INTA_M 0x000000E0 // Interrupt 72 Priority Mask 630 #define NVIC_PRI18_INTD_S 29 631 #define NVIC_PRI18_INTC_S 21 632 #define NVIC_PRI18_INTB_S 13 633 #define NVIC_PRI18_INTA_S 5 634 635 //***************************************************************************** 636 // 637 // The following are defines for the bit fields in the NVIC_PRI19 register. 638 // 639 //***************************************************************************** 640 #define NVIC_PRI19_INTD_M 0xE0000000 // Interrupt 79 Priority Mask 641 #define NVIC_PRI19_INTC_M 0x00E00000 // Interrupt 78 Priority Mask 642 #define NVIC_PRI19_INTB_M 0x0000E000 // Interrupt 77 Priority Mask 643 #define NVIC_PRI19_INTA_M 0x000000E0 // Interrupt 76 Priority Mask 644 #define NVIC_PRI19_INTD_S 29 645 #define NVIC_PRI19_INTC_S 21 646 #define NVIC_PRI19_INTB_S 13 647 #define NVIC_PRI19_INTA_S 5 648 649 //***************************************************************************** 650 // 651 // The following are defines for the bit fields in the NVIC_PRI20 register. 652 // 653 //***************************************************************************** 654 #define NVIC_PRI20_INTD_M 0xE0000000 // Interrupt 83 Priority Mask 655 #define NVIC_PRI20_INTC_M 0x00E00000 // Interrupt 82 Priority Mask 656 #define NVIC_PRI20_INTB_M 0x0000E000 // Interrupt 81 Priority Mask 657 #define NVIC_PRI20_INTA_M 0x000000E0 // Interrupt 80 Priority Mask 658 #define NVIC_PRI20_INTD_S 29 659 #define NVIC_PRI20_INTC_S 21 660 #define NVIC_PRI20_INTB_S 13 661 #define NVIC_PRI20_INTA_S 5 662 663 //***************************************************************************** 664 // 665 // The following are defines for the bit fields in the NVIC_PRI21 register. 666 // 667 //***************************************************************************** 668 #define NVIC_PRI21_INTD_M 0xE0000000 // Interrupt 87 Priority Mask 669 #define NVIC_PRI21_INTC_M 0x00E00000 // Interrupt 86 Priority Mask 670 #define NVIC_PRI21_INTB_M 0x0000E000 // Interrupt 85 Priority Mask 671 #define NVIC_PRI21_INTA_M 0x000000E0 // Interrupt 84 Priority Mask 672 #define NVIC_PRI21_INTD_S 29 673 #define NVIC_PRI21_INTC_S 21 674 #define NVIC_PRI21_INTB_S 13 675 #define NVIC_PRI21_INTA_S 5 676 677 //***************************************************************************** 678 // 679 // The following are defines for the bit fields in the NVIC_PRI22 register. 680 // 681 //***************************************************************************** 682 #define NVIC_PRI22_INTD_M 0xE0000000 // Interrupt 91 Priority Mask 683 #define NVIC_PRI22_INTC_M 0x00E00000 // Interrupt 90 Priority Mask 684 #define NVIC_PRI22_INTB_M 0x0000E000 // Interrupt 89 Priority Mask 685 #define NVIC_PRI22_INTA_M 0x000000E0 // Interrupt 88 Priority Mask 686 #define NVIC_PRI22_INTD_S 29 687 #define NVIC_PRI22_INTC_S 21 688 #define NVIC_PRI22_INTB_S 13 689 #define NVIC_PRI22_INTA_S 5 690 691 //***************************************************************************** 692 // 693 // The following are defines for the bit fields in the NVIC_PRI23 register. 694 // 695 //***************************************************************************** 696 #define NVIC_PRI23_INTD_M 0xE0000000 // Interrupt 95 Priority Mask 697 #define NVIC_PRI23_INTC_M 0x00E00000 // Interrupt 94 Priority Mask 698 #define NVIC_PRI23_INTB_M 0x0000E000 // Interrupt 93 Priority Mask 699 #define NVIC_PRI23_INTA_M 0x000000E0 // Interrupt 92 Priority Mask 700 #define NVIC_PRI23_INTD_S 29 701 #define NVIC_PRI23_INTC_S 21 702 #define NVIC_PRI23_INTB_S 13 703 #define NVIC_PRI23_INTA_S 5 704 705 //***************************************************************************** 706 // 707 // The following are defines for the bit fields in the NVIC_PRI24 register. 708 // 709 //***************************************************************************** 710 #define NVIC_PRI24_INTD_M 0xE0000000 // Interrupt 99 Priority Mask 711 #define NVIC_PRI24_INTC_M 0x00E00000 // Interrupt 98 Priority Mask 712 #define NVIC_PRI24_INTB_M 0x0000E000 // Interrupt 97 Priority Mask 713 #define NVIC_PRI24_INTA_M 0x000000E0 // Interrupt 96 Priority Mask 714 #define NVIC_PRI24_INTD_S 29 715 #define NVIC_PRI24_INTC_S 21 716 #define NVIC_PRI24_INTB_S 13 717 #define NVIC_PRI24_INTA_S 5 718 719 //***************************************************************************** 720 // 721 // The following are defines for the bit fields in the NVIC_PRI25 register. 722 // 723 //***************************************************************************** 724 #define NVIC_PRI25_INTD_M 0xE0000000 // Interrupt 103 Priority Mask 725 #define NVIC_PRI25_INTC_M 0x00E00000 // Interrupt 102 Priority Mask 726 #define NVIC_PRI25_INTB_M 0x0000E000 // Interrupt 101 Priority Mask 727 #define NVIC_PRI25_INTA_M 0x000000E0 // Interrupt 100 Priority Mask 728 #define NVIC_PRI25_INTD_S 29 729 #define NVIC_PRI25_INTC_S 21 730 #define NVIC_PRI25_INTB_S 13 731 #define NVIC_PRI25_INTA_S 5 732 733 //***************************************************************************** 734 // 735 // The following are defines for the bit fields in the NVIC_PRI26 register. 736 // 737 //***************************************************************************** 738 #define NVIC_PRI26_INTD_M 0xE0000000 // Interrupt 107 Priority Mask 739 #define NVIC_PRI26_INTC_M 0x00E00000 // Interrupt 106 Priority Mask 740 #define NVIC_PRI26_INTB_M 0x0000E000 // Interrupt 105 Priority Mask 741 #define NVIC_PRI26_INTA_M 0x000000E0 // Interrupt 104 Priority Mask 742 #define NVIC_PRI26_INTD_S 29 743 #define NVIC_PRI26_INTC_S 21 744 #define NVIC_PRI26_INTB_S 13 745 #define NVIC_PRI26_INTA_S 5 746 747 //***************************************************************************** 748 // 749 // The following are defines for the bit fields in the NVIC_PRI27 register. 750 // 751 //***************************************************************************** 752 #define NVIC_PRI27_INTD_M 0xE0000000 // Interrupt 111 Priority Mask 753 #define NVIC_PRI27_INTC_M 0x00E00000 // Interrupt 110 Priority Mask 754 #define NVIC_PRI27_INTB_M 0x0000E000 // Interrupt 109 Priority Mask 755 #define NVIC_PRI27_INTA_M 0x000000E0 // Interrupt 108 Priority Mask 756 #define NVIC_PRI27_INTD_S 29 757 #define NVIC_PRI27_INTC_S 21 758 #define NVIC_PRI27_INTB_S 13 759 #define NVIC_PRI27_INTA_S 5 760 761 //***************************************************************************** 762 // 763 // The following are defines for the bit fields in the NVIC_PRI28 register. 764 // 765 //***************************************************************************** 766 #define NVIC_PRI28_INTD_M 0xE0000000 // Interrupt 115 Priority Mask 767 #define NVIC_PRI28_INTC_M 0x00E00000 // Interrupt 114 Priority Mask 768 #define NVIC_PRI28_INTB_M 0x0000E000 // Interrupt 113 Priority Mask 769 #define NVIC_PRI28_INTA_M 0x000000E0 // Interrupt 112 Priority Mask 770 #define NVIC_PRI28_INTD_S 29 771 #define NVIC_PRI28_INTC_S 21 772 #define NVIC_PRI28_INTB_S 13 773 #define NVIC_PRI28_INTA_S 5 774 775 //***************************************************************************** 776 // 777 // The following are defines for the bit fields in the NVIC_PRI29 register. 778 // 779 //***************************************************************************** 780 #define NVIC_PRI29_INTD_M 0xE0000000 // Interrupt 119 Priority Mask 781 #define NVIC_PRI29_INTC_M 0x00E00000 // Interrupt 118 Priority Mask 782 #define NVIC_PRI29_INTB_M 0x0000E000 // Interrupt 117 Priority Mask 783 #define NVIC_PRI29_INTA_M 0x000000E0 // Interrupt 116 Priority Mask 784 #define NVIC_PRI29_INTD_S 29 785 #define NVIC_PRI29_INTC_S 21 786 #define NVIC_PRI29_INTB_S 13 787 #define NVIC_PRI29_INTA_S 5 788 789 //***************************************************************************** 790 // 791 // The following are defines for the bit fields in the NVIC_PRI30 register. 792 // 793 //***************************************************************************** 794 #define NVIC_PRI30_INTD_M 0xE0000000 // Interrupt 123 Priority Mask 795 #define NVIC_PRI30_INTC_M 0x00E00000 // Interrupt 122 Priority Mask 796 #define NVIC_PRI30_INTB_M 0x0000E000 // Interrupt 121 Priority Mask 797 #define NVIC_PRI30_INTA_M 0x000000E0 // Interrupt 120 Priority Mask 798 #define NVIC_PRI30_INTD_S 29 799 #define NVIC_PRI30_INTC_S 21 800 #define NVIC_PRI30_INTB_S 13 801 #define NVIC_PRI30_INTA_S 5 802 803 //***************************************************************************** 804 // 805 // The following are defines for the bit fields in the NVIC_PRI31 register. 806 // 807 //***************************************************************************** 808 #define NVIC_PRI31_INTD_M 0xE0000000 // Interrupt 127 Priority Mask 809 #define NVIC_PRI31_INTC_M 0x00E00000 // Interrupt 126 Priority Mask 810 #define NVIC_PRI31_INTB_M 0x0000E000 // Interrupt 125 Priority Mask 811 #define NVIC_PRI31_INTA_M 0x000000E0 // Interrupt 124 Priority Mask 812 #define NVIC_PRI31_INTD_S 29 813 #define NVIC_PRI31_INTC_S 21 814 #define NVIC_PRI31_INTB_S 13 815 #define NVIC_PRI31_INTA_S 5 816 817 //***************************************************************************** 818 // 819 // The following are defines for the bit fields in the NVIC_PRI32 register. 820 // 821 //***************************************************************************** 822 #define NVIC_PRI32_INTD_M 0xE0000000 // Interrupt 131 Priority Mask 823 #define NVIC_PRI32_INTC_M 0x00E00000 // Interrupt 130 Priority Mask 824 #define NVIC_PRI32_INTB_M 0x0000E000 // Interrupt 129 Priority Mask 825 #define NVIC_PRI32_INTA_M 0x000000E0 // Interrupt 128 Priority Mask 826 #define NVIC_PRI32_INTD_S 29 827 #define NVIC_PRI32_INTC_S 21 828 #define NVIC_PRI32_INTB_S 13 829 #define NVIC_PRI32_INTA_S 5 830 831 //***************************************************************************** 832 // 833 // The following are defines for the bit fields in the NVIC_PRI33 register. 834 // 835 //***************************************************************************** 836 #define NVIC_PRI33_INTD_M 0xE0000000 // Interrupt Priority for Interrupt 837 // [4n+3] 838 #define NVIC_PRI33_INTC_M 0x00E00000 // Interrupt Priority for Interrupt 839 // [4n+2] 840 #define NVIC_PRI33_INTB_M 0x0000E000 // Interrupt Priority for Interrupt 841 // [4n+1] 842 #define NVIC_PRI33_INTA_M 0x000000E0 // Interrupt Priority for Interrupt 843 // [4n] 844 #define NVIC_PRI33_INTD_S 29 845 #define NVIC_PRI33_INTC_S 21 846 #define NVIC_PRI33_INTB_S 13 847 #define NVIC_PRI33_INTA_S 5 848 849 //***************************************************************************** 850 // 851 // The following are defines for the bit fields in the NVIC_PRI34 register. 852 // 853 //***************************************************************************** 854 #define NVIC_PRI34_INTD_M 0xE0000000 // Interrupt Priority for Interrupt 855 // [4n+3] 856 #define NVIC_PRI34_INTC_M 0x00E00000 // Interrupt Priority for Interrupt 857 // [4n+2] 858 #define NVIC_PRI34_INTB_M 0x0000E000 // Interrupt Priority for Interrupt 859 // [4n+1] 860 #define NVIC_PRI34_INTA_M 0x000000E0 // Interrupt Priority for Interrupt 861 // [4n] 862 #define NVIC_PRI34_INTD_S 29 863 #define NVIC_PRI34_INTC_S 21 864 #define NVIC_PRI34_INTB_S 13 865 #define NVIC_PRI34_INTA_S 5 866 867 //***************************************************************************** 868 // 869 // The following are defines for the bit fields in the NVIC_CPUID register. 870 // 871 //***************************************************************************** 872 #define NVIC_CPUID_IMP_M 0xFF000000 // Implementer Code 873 #define NVIC_CPUID_IMP_ARM 0x41000000 // ARM 874 #define NVIC_CPUID_VAR_M 0x00F00000 // Variant Number 875 #define NVIC_CPUID_CON_M 0x000F0000 // Constant 876 #define NVIC_CPUID_PARTNO_M 0x0000FFF0 // Part Number 877 #define NVIC_CPUID_PARTNO_CM4 0x0000C240 // Cortex-M4 processor 878 #define NVIC_CPUID_REV_M 0x0000000F // Revision Number 879 880 //***************************************************************************** 881 // 882 // The following are defines for the bit fields in the NVIC_INT_CTRL register. 883 // 884 //***************************************************************************** 885 #define NVIC_INT_CTRL_NMI_SET 0x80000000 // NMI Set Pending 886 #define NVIC_INT_CTRL_PEND_SV 0x10000000 // PendSV Set Pending 887 #define NVIC_INT_CTRL_UNPEND_SV 0x08000000 // PendSV Clear Pending 888 #define NVIC_INT_CTRL_PENDSTSET 0x04000000 // SysTick Set Pending 889 #define NVIC_INT_CTRL_PENDSTCLR 0x02000000 // SysTick Clear Pending 890 #define NVIC_INT_CTRL_ISR_PRE 0x00800000 // Debug Interrupt Handling 891 #define NVIC_INT_CTRL_ISR_PEND 0x00400000 // Interrupt Pending 892 #define NVIC_INT_CTRL_VEC_PEN_M 0x000FF000 // Interrupt Pending Vector Number 893 #define NVIC_INT_CTRL_VEC_PEN_NMI \ 894 0x00002000 // NMI 895 #define NVIC_INT_CTRL_VEC_PEN_HARD \ 896 0x00003000 // Hard fault 897 #define NVIC_INT_CTRL_VEC_PEN_MEM \ 898 0x00004000 // Memory management fault 899 #define NVIC_INT_CTRL_VEC_PEN_BUS \ 900 0x00005000 // Bus fault 901 #define NVIC_INT_CTRL_VEC_PEN_USG \ 902 0x00006000 // Usage fault 903 #define NVIC_INT_CTRL_VEC_PEN_SVC \ 904 0x0000B000 // SVCall 905 #define NVIC_INT_CTRL_VEC_PEN_PNDSV \ 906 0x0000E000 // PendSV 907 #define NVIC_INT_CTRL_VEC_PEN_TICK \ 908 0x0000F000 // SysTick 909 #define NVIC_INT_CTRL_RET_BASE 0x00000800 // Return to Base 910 #define NVIC_INT_CTRL_VEC_ACT_M 0x000000FF // Interrupt Pending Vector Number 911 #define NVIC_INT_CTRL_VEC_ACT_S 0 912 913 //***************************************************************************** 914 // 915 // The following are defines for the bit fields in the NVIC_VTABLE register. 916 // 917 //***************************************************************************** 918 #define NVIC_VTABLE_OFFSET_M 0xFFFFFC00 // Vector Table Offset 919 #define NVIC_VTABLE_OFFSET_S 10 920 921 //***************************************************************************** 922 // 923 // The following are defines for the bit fields in the NVIC_APINT register. 924 // 925 //***************************************************************************** 926 #define NVIC_APINT_VECTKEY_M 0xFFFF0000 // Register Key 927 #define NVIC_APINT_VECTKEY 0x05FA0000 // Vector key 928 #define NVIC_APINT_ENDIANESS 0x00008000 // Data Endianess 929 #define NVIC_APINT_PRIGROUP_M 0x00000700 // Interrupt Priority Grouping 930 #define NVIC_APINT_PRIGROUP_7_1 0x00000000 // Priority group 7.1 split 931 #define NVIC_APINT_PRIGROUP_6_2 0x00000100 // Priority group 6.2 split 932 #define NVIC_APINT_PRIGROUP_5_3 0x00000200 // Priority group 5.3 split 933 #define NVIC_APINT_PRIGROUP_4_4 0x00000300 // Priority group 4.4 split 934 #define NVIC_APINT_PRIGROUP_3_5 0x00000400 // Priority group 3.5 split 935 #define NVIC_APINT_PRIGROUP_2_6 0x00000500 // Priority group 2.6 split 936 #define NVIC_APINT_PRIGROUP_1_7 0x00000600 // Priority group 1.7 split 937 #define NVIC_APINT_PRIGROUP_0_8 0x00000700 // Priority group 0.8 split 938 #define NVIC_APINT_SYSRESETREQ 0x00000004 // System Reset Request 939 #define NVIC_APINT_VECT_CLR_ACT 0x00000002 // Clear Active NMI / Fault 940 #define NVIC_APINT_VECT_RESET 0x00000001 // System Reset 941 942 //***************************************************************************** 943 // 944 // The following are defines for the bit fields in the NVIC_SYS_CTRL register. 945 // 946 //***************************************************************************** 947 #define NVIC_SYS_CTRL_SEVONPEND 0x00000010 // Wake Up on Pending 948 #define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004 // Deep Sleep Enable 949 #define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002 // Sleep on ISR Exit 950 951 //***************************************************************************** 952 // 953 // The following are defines for the bit fields in the NVIC_CFG_CTRL register. 954 // 955 //***************************************************************************** 956 #define NVIC_CFG_CTRL_STKALIGN 0x00000200 // Stack Alignment on Exception 957 // Entry 958 #define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100 // Ignore Bus Fault in NMI and 959 // Fault 960 #define NVIC_CFG_CTRL_DIV0 0x00000010 // Trap on Divide by 0 961 #define NVIC_CFG_CTRL_UNALIGNED 0x00000008 // Trap on Unaligned Access 962 #define NVIC_CFG_CTRL_MAIN_PEND 0x00000002 // Allow Main Interrupt Trigger 963 #define NVIC_CFG_CTRL_BASE_THR 0x00000001 // Thread State Control 964 965 //***************************************************************************** 966 // 967 // The following are defines for the bit fields in the NVIC_SYS_PRI1 register. 968 // 969 //***************************************************************************** 970 #define NVIC_SYS_PRI1_USAGE_M 0x00E00000 // Usage Fault Priority 971 #define NVIC_SYS_PRI1_BUS_M 0x0000E000 // Bus Fault Priority 972 #define NVIC_SYS_PRI1_MEM_M 0x000000E0 // Memory Management Fault Priority 973 #define NVIC_SYS_PRI1_USAGE_S 21 974 #define NVIC_SYS_PRI1_BUS_S 13 975 #define NVIC_SYS_PRI1_MEM_S 5 976 977 //***************************************************************************** 978 // 979 // The following are defines for the bit fields in the NVIC_SYS_PRI2 register. 980 // 981 //***************************************************************************** 982 #define NVIC_SYS_PRI2_SVC_M 0xE0000000 // SVCall Priority 983 #define NVIC_SYS_PRI2_SVC_S 29 984 985 //***************************************************************************** 986 // 987 // The following are defines for the bit fields in the NVIC_SYS_PRI3 register. 988 // 989 //***************************************************************************** 990 #define NVIC_SYS_PRI3_TICK_M 0xE0000000 // SysTick Exception Priority 991 #define NVIC_SYS_PRI3_PENDSV_M 0x00E00000 // PendSV Priority 992 #define NVIC_SYS_PRI3_DEBUG_M 0x000000E0 // Debug Priority 993 #define NVIC_SYS_PRI3_TICK_S 29 994 #define NVIC_SYS_PRI3_PENDSV_S 21 995 #define NVIC_SYS_PRI3_DEBUG_S 5 996 997 //***************************************************************************** 998 // 999 // The following are defines for the bit fields in the NVIC_SYS_HND_CTRL 1000 // register. 1001 // 1002 //***************************************************************************** 1003 #define NVIC_SYS_HND_CTRL_USAGE 0x00040000 // Usage Fault Enable 1004 #define NVIC_SYS_HND_CTRL_BUS 0x00020000 // Bus Fault Enable 1005 #define NVIC_SYS_HND_CTRL_MEM 0x00010000 // Memory Management Fault Enable 1006 #define NVIC_SYS_HND_CTRL_SVC 0x00008000 // SVC Call Pending 1007 #define NVIC_SYS_HND_CTRL_BUSP 0x00004000 // Bus Fault Pending 1008 #define NVIC_SYS_HND_CTRL_MEMP 0x00002000 // Memory Management Fault Pending 1009 #define NVIC_SYS_HND_CTRL_USAGEP \ 1010 0x00001000 // Usage Fault Pending 1011 #define NVIC_SYS_HND_CTRL_TICK 0x00000800 // SysTick Exception Active 1012 #define NVIC_SYS_HND_CTRL_PNDSV 0x00000400 // PendSV Exception Active 1013 #define NVIC_SYS_HND_CTRL_MON 0x00000100 // Debug Monitor Active 1014 #define NVIC_SYS_HND_CTRL_SVCA 0x00000080 // SVC Call Active 1015 #define NVIC_SYS_HND_CTRL_USGA 0x00000008 // Usage Fault Active 1016 #define NVIC_SYS_HND_CTRL_BUSA 0x00000002 // Bus Fault Active 1017 #define NVIC_SYS_HND_CTRL_MEMA 0x00000001 // Memory Management Fault Active 1018 1019 //***************************************************************************** 1020 // 1021 // The following are defines for the bit fields in the NVIC_FAULT_STAT 1022 // register. 1023 // 1024 //***************************************************************************** 1025 #define NVIC_FAULT_STAT_DIV0 0x02000000 // Divide-by-Zero Usage Fault 1026 #define NVIC_FAULT_STAT_UNALIGN 0x01000000 // Unaligned Access Usage Fault 1027 #define NVIC_FAULT_STAT_NOCP 0x00080000 // No Coprocessor Usage Fault 1028 #define NVIC_FAULT_STAT_INVPC 0x00040000 // Invalid PC Load Usage Fault 1029 #define NVIC_FAULT_STAT_INVSTAT 0x00020000 // Invalid State Usage Fault 1030 #define NVIC_FAULT_STAT_UNDEF 0x00010000 // Undefined Instruction Usage 1031 // Fault 1032 #define NVIC_FAULT_STAT_BFARV 0x00008000 // Bus Fault Address Register Valid 1033 #define NVIC_FAULT_STAT_BLSPERR 0x00002000 // Bus Fault on Floating-Point Lazy 1034 // State Preservation 1035 #define NVIC_FAULT_STAT_BSTKE 0x00001000 // Stack Bus Fault 1036 #define NVIC_FAULT_STAT_BUSTKE 0x00000800 // Unstack Bus Fault 1037 #define NVIC_FAULT_STAT_IMPRE 0x00000400 // Imprecise Data Bus Error 1038 #define NVIC_FAULT_STAT_PRECISE 0x00000200 // Precise Data Bus Error 1039 #define NVIC_FAULT_STAT_IBUS 0x00000100 // Instruction Bus Error 1040 #define NVIC_FAULT_STAT_MMARV 0x00000080 // Memory Management Fault Address 1041 // Register Valid 1042 #define NVIC_FAULT_STAT_MLSPERR 0x00000020 // Memory Management Fault on 1043 // Floating-Point Lazy State 1044 // Preservation 1045 #define NVIC_FAULT_STAT_MSTKE 0x00000010 // Stack Access Violation 1046 #define NVIC_FAULT_STAT_MUSTKE 0x00000008 // Unstack Access Violation 1047 #define NVIC_FAULT_STAT_DERR 0x00000002 // Data Access Violation 1048 #define NVIC_FAULT_STAT_IERR 0x00000001 // Instruction Access Violation 1049 1050 //***************************************************************************** 1051 // 1052 // The following are defines for the bit fields in the NVIC_HFAULT_STAT 1053 // register. 1054 // 1055 //***************************************************************************** 1056 #define NVIC_HFAULT_STAT_DBG 0x80000000 // Debug Event 1057 #define NVIC_HFAULT_STAT_FORCED 0x40000000 // Forced Hard Fault 1058 #define NVIC_HFAULT_STAT_VECT 0x00000002 // Vector Table Read Fault 1059 1060 //***************************************************************************** 1061 // 1062 // The following are defines for the bit fields in the NVIC_DEBUG_STAT 1063 // register. 1064 // 1065 //***************************************************************************** 1066 #define NVIC_DEBUG_STAT_EXTRNL 0x00000010 // EDBGRQ asserted 1067 #define NVIC_DEBUG_STAT_VCATCH 0x00000008 // Vector catch 1068 #define NVIC_DEBUG_STAT_DWTTRAP 0x00000004 // DWT match 1069 #define NVIC_DEBUG_STAT_BKPT 0x00000002 // Breakpoint instruction 1070 #define NVIC_DEBUG_STAT_HALTED 0x00000001 // Halt request 1071 1072 //***************************************************************************** 1073 // 1074 // The following are defines for the bit fields in the NVIC_MM_ADDR register. 1075 // 1076 //***************************************************************************** 1077 #define NVIC_MM_ADDR_M 0xFFFFFFFF // Fault Address 1078 #define NVIC_MM_ADDR_S 0 1079 1080 //***************************************************************************** 1081 // 1082 // The following are defines for the bit fields in the NVIC_FAULT_ADDR 1083 // register. 1084 // 1085 //***************************************************************************** 1086 #define NVIC_FAULT_ADDR_M 0xFFFFFFFF // Fault Address 1087 #define NVIC_FAULT_ADDR_S 0 1088 1089 //***************************************************************************** 1090 // 1091 // The following are defines for the bit fields in the NVIC_CPAC register. 1092 // 1093 //***************************************************************************** 1094 #define NVIC_CPAC_CP11_M 0x00C00000 // CP11 Coprocessor Access 1095 // Privilege 1096 #define NVIC_CPAC_CP11_DIS 0x00000000 // Access Denied 1097 #define NVIC_CPAC_CP11_PRIV 0x00400000 // Privileged Access Only 1098 #define NVIC_CPAC_CP11_FULL 0x00C00000 // Full Access 1099 #define NVIC_CPAC_CP10_M 0x00300000 // CP10 Coprocessor Access 1100 // Privilege 1101 #define NVIC_CPAC_CP10_DIS 0x00000000 // Access Denied 1102 #define NVIC_CPAC_CP10_PRIV 0x00100000 // Privileged Access Only 1103 #define NVIC_CPAC_CP10_FULL 0x00300000 // Full Access 1104 1105 //***************************************************************************** 1106 // 1107 // The following are defines for the bit fields in the NVIC_MPU_TYPE register. 1108 // 1109 //***************************************************************************** 1110 #define NVIC_MPU_TYPE_IREGION_M 0x00FF0000 // Number of I Regions 1111 #define NVIC_MPU_TYPE_DREGION_M 0x0000FF00 // Number of D Regions 1112 #define NVIC_MPU_TYPE_SEPARATE 0x00000001 // Separate or Unified MPU 1113 #define NVIC_MPU_TYPE_IREGION_S 16 1114 #define NVIC_MPU_TYPE_DREGION_S 8 1115 1116 //***************************************************************************** 1117 // 1118 // The following are defines for the bit fields in the NVIC_MPU_CTRL register. 1119 // 1120 //***************************************************************************** 1121 #define NVIC_MPU_CTRL_PRIVDEFEN 0x00000004 // MPU Default Region 1122 #define NVIC_MPU_CTRL_HFNMIENA 0x00000002 // MPU Enabled During Faults 1123 #define NVIC_MPU_CTRL_ENABLE 0x00000001 // MPU Enable 1124 1125 //***************************************************************************** 1126 // 1127 // The following are defines for the bit fields in the NVIC_MPU_NUMBER 1128 // register. 1129 // 1130 //***************************************************************************** 1131 #define NVIC_MPU_NUMBER_M 0x00000007 // MPU Region to Access 1132 #define NVIC_MPU_NUMBER_S 0 1133 1134 //***************************************************************************** 1135 // 1136 // The following are defines for the bit fields in the NVIC_MPU_BASE register. 1137 // 1138 //***************************************************************************** 1139 #define NVIC_MPU_BASE_ADDR_M 0xFFFFFFE0 // Base Address Mask 1140 #define NVIC_MPU_BASE_VALID 0x00000010 // Region Number Valid 1141 #define NVIC_MPU_BASE_REGION_M 0x00000007 // Region Number 1142 #define NVIC_MPU_BASE_ADDR_S 5 1143 #define NVIC_MPU_BASE_REGION_S 0 1144 1145 //***************************************************************************** 1146 // 1147 // The following are defines for the bit fields in the NVIC_MPU_ATTR register. 1148 // 1149 //***************************************************************************** 1150 #define NVIC_MPU_ATTR_XN 0x10000000 // Instruction Access Disable 1151 #define NVIC_MPU_ATTR_AP_M 0x07000000 // Access Privilege 1152 #define NVIC_MPU_ATTR_AP_NO_NO 0x00000000 // prv: no access, usr: no access 1153 #define NVIC_MPU_ATTR_AP_RW_NO 0x01000000 // prv: rw, usr: none 1154 #define NVIC_MPU_ATTR_AP_RW_RO 0x02000000 // prv: rw, usr: read-only 1155 #define NVIC_MPU_ATTR_AP_RW_RW 0x03000000 // prv: rw, usr: rw 1156 #define NVIC_MPU_ATTR_AP_RO_NO 0x05000000 // prv: ro, usr: none 1157 #define NVIC_MPU_ATTR_AP_RO_RO 0x06000000 // prv: ro, usr: ro 1158 #define NVIC_MPU_ATTR_TEX_M 0x00380000 // Type Extension Mask 1159 #define NVIC_MPU_ATTR_SHAREABLE 0x00040000 // Shareable 1160 #define NVIC_MPU_ATTR_CACHEABLE 0x00020000 // Cacheable 1161 #define NVIC_MPU_ATTR_BUFFRABLE 0x00010000 // Bufferable 1162 #define NVIC_MPU_ATTR_SRD_M 0x0000FF00 // Subregion Disable Bits 1163 #define NVIC_MPU_ATTR_SRD_0 0x00000100 // Sub-region 0 disable 1164 #define NVIC_MPU_ATTR_SRD_1 0x00000200 // Sub-region 1 disable 1165 #define NVIC_MPU_ATTR_SRD_2 0x00000400 // Sub-region 2 disable 1166 #define NVIC_MPU_ATTR_SRD_3 0x00000800 // Sub-region 3 disable 1167 #define NVIC_MPU_ATTR_SRD_4 0x00001000 // Sub-region 4 disable 1168 #define NVIC_MPU_ATTR_SRD_5 0x00002000 // Sub-region 5 disable 1169 #define NVIC_MPU_ATTR_SRD_6 0x00004000 // Sub-region 6 disable 1170 #define NVIC_MPU_ATTR_SRD_7 0x00008000 // Sub-region 7 disable 1171 #define NVIC_MPU_ATTR_SIZE_M 0x0000003E // Region Size Mask 1172 #define NVIC_MPU_ATTR_SIZE_32B 0x00000008 // Region size 32 bytes 1173 #define NVIC_MPU_ATTR_SIZE_64B 0x0000000A // Region size 64 bytes 1174 #define NVIC_MPU_ATTR_SIZE_128B 0x0000000C // Region size 128 bytes 1175 #define NVIC_MPU_ATTR_SIZE_256B 0x0000000E // Region size 256 bytes 1176 #define NVIC_MPU_ATTR_SIZE_512B 0x00000010 // Region size 512 bytes 1177 #define NVIC_MPU_ATTR_SIZE_1K 0x00000012 // Region size 1 Kbytes 1178 #define NVIC_MPU_ATTR_SIZE_2K 0x00000014 // Region size 2 Kbytes 1179 #define NVIC_MPU_ATTR_SIZE_4K 0x00000016 // Region size 4 Kbytes 1180 #define NVIC_MPU_ATTR_SIZE_8K 0x00000018 // Region size 8 Kbytes 1181 #define NVIC_MPU_ATTR_SIZE_16K 0x0000001A // Region size 16 Kbytes 1182 #define NVIC_MPU_ATTR_SIZE_32K 0x0000001C // Region size 32 Kbytes 1183 #define NVIC_MPU_ATTR_SIZE_64K 0x0000001E // Region size 64 Kbytes 1184 #define NVIC_MPU_ATTR_SIZE_128K 0x00000020 // Region size 128 Kbytes 1185 #define NVIC_MPU_ATTR_SIZE_256K 0x00000022 // Region size 256 Kbytes 1186 #define NVIC_MPU_ATTR_SIZE_512K 0x00000024 // Region size 512 Kbytes 1187 #define NVIC_MPU_ATTR_SIZE_1M 0x00000026 // Region size 1 Mbytes 1188 #define NVIC_MPU_ATTR_SIZE_2M 0x00000028 // Region size 2 Mbytes 1189 #define NVIC_MPU_ATTR_SIZE_4M 0x0000002A // Region size 4 Mbytes 1190 #define NVIC_MPU_ATTR_SIZE_8M 0x0000002C // Region size 8 Mbytes 1191 #define NVIC_MPU_ATTR_SIZE_16M 0x0000002E // Region size 16 Mbytes 1192 #define NVIC_MPU_ATTR_SIZE_32M 0x00000030 // Region size 32 Mbytes 1193 #define NVIC_MPU_ATTR_SIZE_64M 0x00000032 // Region size 64 Mbytes 1194 #define NVIC_MPU_ATTR_SIZE_128M 0x00000034 // Region size 128 Mbytes 1195 #define NVIC_MPU_ATTR_SIZE_256M 0x00000036 // Region size 256 Mbytes 1196 #define NVIC_MPU_ATTR_SIZE_512M 0x00000038 // Region size 512 Mbytes 1197 #define NVIC_MPU_ATTR_SIZE_1G 0x0000003A // Region size 1 Gbytes 1198 #define NVIC_MPU_ATTR_SIZE_2G 0x0000003C // Region size 2 Gbytes 1199 #define NVIC_MPU_ATTR_SIZE_4G 0x0000003E // Region size 4 Gbytes 1200 #define NVIC_MPU_ATTR_ENABLE 0x00000001 // Region Enable 1201 1202 //***************************************************************************** 1203 // 1204 // The following are defines for the bit fields in the NVIC_MPU_BASE1 register. 1205 // 1206 //***************************************************************************** 1207 #define NVIC_MPU_BASE1_ADDR_M 0xFFFFFFE0 // Base Address Mask 1208 #define NVIC_MPU_BASE1_VALID 0x00000010 // Region Number Valid 1209 #define NVIC_MPU_BASE1_REGION_M 0x00000007 // Region Number 1210 #define NVIC_MPU_BASE1_ADDR_S 5 1211 #define NVIC_MPU_BASE1_REGION_S 0 1212 1213 //***************************************************************************** 1214 // 1215 // The following are defines for the bit fields in the NVIC_MPU_ATTR1 register. 1216 // 1217 //***************************************************************************** 1218 #define NVIC_MPU_ATTR1_XN 0x10000000 // Instruction Access Disable 1219 #define NVIC_MPU_ATTR1_AP_M 0x07000000 // Access Privilege 1220 #define NVIC_MPU_ATTR1_TEX_M 0x00380000 // Type Extension Mask 1221 #define NVIC_MPU_ATTR1_SHAREABLE \ 1222 0x00040000 // Shareable 1223 #define NVIC_MPU_ATTR1_CACHEABLE \ 1224 0x00020000 // Cacheable 1225 #define NVIC_MPU_ATTR1_BUFFRABLE \ 1226 0x00010000 // Bufferable 1227 #define NVIC_MPU_ATTR1_SRD_M 0x0000FF00 // Subregion Disable Bits 1228 #define NVIC_MPU_ATTR1_SIZE_M 0x0000003E // Region Size Mask 1229 #define NVIC_MPU_ATTR1_ENABLE 0x00000001 // Region Enable 1230 1231 //***************************************************************************** 1232 // 1233 // The following are defines for the bit fields in the NVIC_MPU_BASE2 register. 1234 // 1235 //***************************************************************************** 1236 #define NVIC_MPU_BASE2_ADDR_M 0xFFFFFFE0 // Base Address Mask 1237 #define NVIC_MPU_BASE2_VALID 0x00000010 // Region Number Valid 1238 #define NVIC_MPU_BASE2_REGION_M 0x00000007 // Region Number 1239 #define NVIC_MPU_BASE2_ADDR_S 5 1240 #define NVIC_MPU_BASE2_REGION_S 0 1241 1242 //***************************************************************************** 1243 // 1244 // The following are defines for the bit fields in the NVIC_MPU_ATTR2 register. 1245 // 1246 //***************************************************************************** 1247 #define NVIC_MPU_ATTR2_XN 0x10000000 // Instruction Access Disable 1248 #define NVIC_MPU_ATTR2_AP_M 0x07000000 // Access Privilege 1249 #define NVIC_MPU_ATTR2_TEX_M 0x00380000 // Type Extension Mask 1250 #define NVIC_MPU_ATTR2_SHAREABLE \ 1251 0x00040000 // Shareable 1252 #define NVIC_MPU_ATTR2_CACHEABLE \ 1253 0x00020000 // Cacheable 1254 #define NVIC_MPU_ATTR2_BUFFRABLE \ 1255 0x00010000 // Bufferable 1256 #define NVIC_MPU_ATTR2_SRD_M 0x0000FF00 // Subregion Disable Bits 1257 #define NVIC_MPU_ATTR2_SIZE_M 0x0000003E // Region Size Mask 1258 #define NVIC_MPU_ATTR2_ENABLE 0x00000001 // Region Enable 1259 1260 //***************************************************************************** 1261 // 1262 // The following are defines for the bit fields in the NVIC_MPU_BASE3 register. 1263 // 1264 //***************************************************************************** 1265 #define NVIC_MPU_BASE3_ADDR_M 0xFFFFFFE0 // Base Address Mask 1266 #define NVIC_MPU_BASE3_VALID 0x00000010 // Region Number Valid 1267 #define NVIC_MPU_BASE3_REGION_M 0x00000007 // Region Number 1268 #define NVIC_MPU_BASE3_ADDR_S 5 1269 #define NVIC_MPU_BASE3_REGION_S 0 1270 1271 //***************************************************************************** 1272 // 1273 // The following are defines for the bit fields in the NVIC_MPU_ATTR3 register. 1274 // 1275 //***************************************************************************** 1276 #define NVIC_MPU_ATTR3_XN 0x10000000 // Instruction Access Disable 1277 #define NVIC_MPU_ATTR3_AP_M 0x07000000 // Access Privilege 1278 #define NVIC_MPU_ATTR3_TEX_M 0x00380000 // Type Extension Mask 1279 #define NVIC_MPU_ATTR3_SHAREABLE \ 1280 0x00040000 // Shareable 1281 #define NVIC_MPU_ATTR3_CACHEABLE \ 1282 0x00020000 // Cacheable 1283 #define NVIC_MPU_ATTR3_BUFFRABLE \ 1284 0x00010000 // Bufferable 1285 #define NVIC_MPU_ATTR3_SRD_M 0x0000FF00 // Subregion Disable Bits 1286 #define NVIC_MPU_ATTR3_SIZE_M 0x0000003E // Region Size Mask 1287 #define NVIC_MPU_ATTR3_ENABLE 0x00000001 // Region Enable 1288 1289 //***************************************************************************** 1290 // 1291 // The following are defines for the bit fields in the NVIC_DBG_CTRL register. 1292 // 1293 //***************************************************************************** 1294 #define NVIC_DBG_CTRL_DBGKEY_M 0xFFFF0000 // Debug key mask 1295 #define NVIC_DBG_CTRL_DBGKEY 0xA05F0000 // Debug key 1296 #define NVIC_DBG_CTRL_S_RESET_ST \ 1297 0x02000000 // Core has reset since last read 1298 #define NVIC_DBG_CTRL_S_RETIRE_ST \ 1299 0x01000000 // Core has executed insruction 1300 // since last read 1301 #define NVIC_DBG_CTRL_S_LOCKUP 0x00080000 // Core is locked up 1302 #define NVIC_DBG_CTRL_S_SLEEP 0x00040000 // Core is sleeping 1303 #define NVIC_DBG_CTRL_S_HALT 0x00020000 // Core status on halt 1304 #define NVIC_DBG_CTRL_S_REGRDY 0x00010000 // Register read/write available 1305 #define NVIC_DBG_CTRL_C_SNAPSTALL \ 1306 0x00000020 // Breaks a stalled load/store 1307 #define NVIC_DBG_CTRL_C_MASKINT 0x00000008 // Mask interrupts when stepping 1308 #define NVIC_DBG_CTRL_C_STEP 0x00000004 // Step the core 1309 #define NVIC_DBG_CTRL_C_HALT 0x00000002 // Halt the core 1310 #define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001 // Enable debug 1311 1312 //***************************************************************************** 1313 // 1314 // The following are defines for the bit fields in the NVIC_DBG_XFER register. 1315 // 1316 //***************************************************************************** 1317 #define NVIC_DBG_XFER_REG_WNR 0x00010000 // Write or not read 1318 #define NVIC_DBG_XFER_REG_SEL_M 0x0000001F // Register 1319 #define NVIC_DBG_XFER_REG_R0 0x00000000 // Register R0 1320 #define NVIC_DBG_XFER_REG_R1 0x00000001 // Register R1 1321 #define NVIC_DBG_XFER_REG_R2 0x00000002 // Register R2 1322 #define NVIC_DBG_XFER_REG_R3 0x00000003 // Register R3 1323 #define NVIC_DBG_XFER_REG_R4 0x00000004 // Register R4 1324 #define NVIC_DBG_XFER_REG_R5 0x00000005 // Register R5 1325 #define NVIC_DBG_XFER_REG_R6 0x00000006 // Register R6 1326 #define NVIC_DBG_XFER_REG_R7 0x00000007 // Register R7 1327 #define NVIC_DBG_XFER_REG_R8 0x00000008 // Register R8 1328 #define NVIC_DBG_XFER_REG_R9 0x00000009 // Register R9 1329 #define NVIC_DBG_XFER_REG_R10 0x0000000A // Register R10 1330 #define NVIC_DBG_XFER_REG_R11 0x0000000B // Register R11 1331 #define NVIC_DBG_XFER_REG_R12 0x0000000C // Register R12 1332 #define NVIC_DBG_XFER_REG_R13 0x0000000D // Register R13 1333 #define NVIC_DBG_XFER_REG_R14 0x0000000E // Register R14 1334 #define NVIC_DBG_XFER_REG_R15 0x0000000F // Register R15 1335 #define NVIC_DBG_XFER_REG_FLAGS 0x00000010 // xPSR/Flags register 1336 #define NVIC_DBG_XFER_REG_MSP 0x00000011 // Main SP 1337 #define NVIC_DBG_XFER_REG_PSP 0x00000012 // Process SP 1338 #define NVIC_DBG_XFER_REG_DSP 0x00000013 // Deep SP 1339 #define NVIC_DBG_XFER_REG_CFBP 0x00000014 // Control/Fault/BasePri/PriMask 1340 1341 //***************************************************************************** 1342 // 1343 // The following are defines for the bit fields in the NVIC_DBG_DATA register. 1344 // 1345 //***************************************************************************** 1346 #define NVIC_DBG_DATA_M 0xFFFFFFFF // Data temporary cache 1347 #define NVIC_DBG_DATA_S 0 1348 1349 //***************************************************************************** 1350 // 1351 // The following are defines for the bit fields in the NVIC_DBG_INT register. 1352 // 1353 //***************************************************************************** 1354 #define NVIC_DBG_INT_HARDERR 0x00000400 // Debug trap on hard fault 1355 #define NVIC_DBG_INT_INTERR 0x00000200 // Debug trap on interrupt errors 1356 #define NVIC_DBG_INT_BUSERR 0x00000100 // Debug trap on bus error 1357 #define NVIC_DBG_INT_STATERR 0x00000080 // Debug trap on usage fault state 1358 #define NVIC_DBG_INT_CHKERR 0x00000040 // Debug trap on usage fault check 1359 #define NVIC_DBG_INT_NOCPERR 0x00000020 // Debug trap on coprocessor error 1360 #define NVIC_DBG_INT_MMERR 0x00000010 // Debug trap on mem manage fault 1361 #define NVIC_DBG_INT_RESET 0x00000008 // Core reset status 1362 #define NVIC_DBG_INT_RSTPENDCLR 0x00000004 // Clear pending core reset 1363 #define NVIC_DBG_INT_RSTPENDING 0x00000002 // Core reset is pending 1364 #define NVIC_DBG_INT_RSTVCATCH 0x00000001 // Reset vector catch 1365 1366 //***************************************************************************** 1367 // 1368 // The following are defines for the bit fields in the NVIC_SW_TRIG register. 1369 // 1370 //***************************************************************************** 1371 #define NVIC_SW_TRIG_INTID_M 0x000000FF // Interrupt ID 1372 #define NVIC_SW_TRIG_INTID_S 0 1373 1374 //***************************************************************************** 1375 // 1376 // The following are defines for the bit fields in the NVIC_FPCC register. 1377 // 1378 //***************************************************************************** 1379 #define NVIC_FPCC_ASPEN 0x80000000 // Automatic State Preservation 1380 // Enable 1381 #define NVIC_FPCC_LSPEN 0x40000000 // Lazy State Preservation Enable 1382 #define NVIC_FPCC_MONRDY 0x00000100 // Monitor Ready 1383 #define NVIC_FPCC_BFRDY 0x00000040 // Bus Fault Ready 1384 #define NVIC_FPCC_MMRDY 0x00000020 // Memory Management Fault Ready 1385 #define NVIC_FPCC_HFRDY 0x00000010 // Hard Fault Ready 1386 #define NVIC_FPCC_THREAD 0x00000008 // Thread Mode 1387 #define NVIC_FPCC_USER 0x00000002 // User Privilege Level 1388 #define NVIC_FPCC_LSPACT 0x00000001 // Lazy State Preservation Active 1389 1390 //***************************************************************************** 1391 // 1392 // The following are defines for the bit fields in the NVIC_FPCA register. 1393 // 1394 //***************************************************************************** 1395 #define NVIC_FPCA_ADDRESS_M 0xFFFFFFF8 // Address 1396 #define NVIC_FPCA_ADDRESS_S 3 1397 1398 //***************************************************************************** 1399 // 1400 // The following are defines for the bit fields in the NVIC_FPDSC register. 1401 // 1402 //***************************************************************************** 1403 #define NVIC_FPDSC_AHP 0x04000000 // AHP Bit Default 1404 #define NVIC_FPDSC_DN 0x02000000 // DN Bit Default 1405 #define NVIC_FPDSC_FZ 0x01000000 // FZ Bit Default 1406 #define NVIC_FPDSC_RMODE_M 0x00C00000 // RMODE Bit Default 1407 #define NVIC_FPDSC_RMODE_RN 0x00000000 // Round to Nearest (RN) mode 1408 #define NVIC_FPDSC_RMODE_RP 0x00400000 // Round towards Plus Infinity (RP) 1409 // mode 1410 #define NVIC_FPDSC_RMODE_RM 0x00800000 // Round towards Minus Infinity 1411 // (RM) mode 1412 #define NVIC_FPDSC_RMODE_RZ 0x00C00000 // Round towards Zero (RZ) mode 1413 1414 #endif // __HW_NVIC_H__ 1415