1 //*****************************************************************************
2 //
3 // startup_gcc.c - Startup code for use with GNU tools.
4 //
5 // Copyright (c) 2013-2017 Texas Instruments Incorporated. All rights reserved.
6 // Software License Agreement
7 //
8 // Texas Instruments (TI) is supplying this software for use solely and
9 // exclusively on TI's microcontroller products. The software is owned by
10 // TI and/or its suppliers, and is protected under applicable copyright
11 // laws. You may not combine this software with "viral" open-source
12 // software in order to form a larger program.
13 //
14 // THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
15 // NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
16 // NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
17 // A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
18 // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
19 // DAMAGES, FOR ANY REASON WHATSOEVER.
20 //
21 // This is part of revision 2.1.4.178 of the DK-TM4C129X Firmware Package.
22 //
23 //*****************************************************************************
24
25 #include <stdint.h>
26 #include "inc/hw_nvic.h"
27 #include "inc/hw_types.h"
28
29 //*****************************************************************************
30 //
31 // Forward declaration of the default fault handlers.
32 //
33 //*****************************************************************************
34 void ResetISR(void);
35 static void NmiSR(void);
36 static void FaultISR(void);
37 static void IntDefaultHandler(void);
38
39 //*****************************************************************************
40 //
41 // The entry point for the application.
42 //
43 //*****************************************************************************
44 extern int main(void);
45
46 extern void SysTick_Handler(void);
47 extern void PendSV_Handler(void);
48 extern void UART0_IRQHandler(void);
49 extern void HardFault_Handler(void);
50 //*****************************************************************************
51 //
52 // Reserve space for the system stack.
53 //
54 //*****************************************************************************
55 static uint32_t pui32Stack[64];
56
57 //*****************************************************************************
58 //
59 // The vector table. Note that the proper constructs must be placed on this to
60 // ensure that it ends up at physical address 0x0000.0000.
61 //
62 //*****************************************************************************
63 __attribute__ ((section(".isr_vector")))
64 void (* const g_pfnVectors[])(void) =
65 {
66 (void (*)(void))((uint32_t)pui32Stack + sizeof(pui32Stack)),
67 // The initial stack pointer
68 ResetISR, // The reset handler
69 NmiSR, // The NMI handler
70 HardFault_Handler, // The hard fault handler
71 IntDefaultHandler, // The MPU fault handler
72 IntDefaultHandler, // The bus fault handler
73 IntDefaultHandler, // The usage fault handler
74 0, // Reserved
75 0, // Reserved
76 0, // Reserved
77 0, // Reserved
78 IntDefaultHandler, // SVCall handler
79 IntDefaultHandler, // Debug monitor handler
80 0, // Reserved
81 PendSV_Handler, // The PendSV handler
82 SysTick_Handler, // The SysTick handler
83 IntDefaultHandler, // GPIO Port A
84 IntDefaultHandler, // GPIO Port B
85 IntDefaultHandler, // GPIO Port C
86 IntDefaultHandler, // GPIO Port D
87 IntDefaultHandler, // GPIO Port E
88 UART0_IRQHandler, // UART0 Rx and Tx
89 IntDefaultHandler, // UART1 Rx and Tx
90 IntDefaultHandler, // SSI0 Rx and Tx
91 IntDefaultHandler, // I2C0 Master and Slave
92 IntDefaultHandler, // PWM Fault
93 IntDefaultHandler, // PWM Generator 0
94 IntDefaultHandler, // PWM Generator 1
95 IntDefaultHandler, // PWM Generator 2
96 IntDefaultHandler, // Quadrature Encoder 0
97 IntDefaultHandler, // ADC Sequence 0
98 IntDefaultHandler, // ADC Sequence 1
99 IntDefaultHandler, // ADC Sequence 2
100 IntDefaultHandler, // ADC Sequence 3
101 IntDefaultHandler, // Watchdog timer
102 IntDefaultHandler, // Timer 0 subtimer A
103 IntDefaultHandler, // Timer 0 subtimer B
104 IntDefaultHandler, // Timer 1 subtimer A
105 IntDefaultHandler, // Timer 1 subtimer B
106 IntDefaultHandler, // Timer 2 subtimer A
107 IntDefaultHandler, // Timer 2 subtimer B
108 IntDefaultHandler, // Analog Comparator 0
109 IntDefaultHandler, // Analog Comparator 1
110 IntDefaultHandler, // Analog Comparator 2
111 IntDefaultHandler, // System Control (PLL, OSC, BO)
112 IntDefaultHandler, // FLASH Control
113 IntDefaultHandler, // GPIO Port F
114 IntDefaultHandler, // GPIO Port G
115 IntDefaultHandler, // GPIO Port H
116 IntDefaultHandler, // UART2 Rx and Tx
117 IntDefaultHandler, // SSI1 Rx and Tx
118 IntDefaultHandler, // Timer 3 subtimer A
119 IntDefaultHandler, // Timer 3 subtimer B
120 IntDefaultHandler, // I2C1 Master and Slave
121 IntDefaultHandler, // CAN0
122 IntDefaultHandler, // CAN1
123 IntDefaultHandler, // Ethernet
124 IntDefaultHandler, // Hibernate
125 IntDefaultHandler, // USB0
126 IntDefaultHandler, // PWM Generator 3
127 IntDefaultHandler, // uDMA Software Transfer
128 IntDefaultHandler, // uDMA Error
129 IntDefaultHandler, // ADC1 Sequence 0
130 IntDefaultHandler, // ADC1 Sequence 1
131 IntDefaultHandler, // ADC1 Sequence 2
132 IntDefaultHandler, // ADC1 Sequence 3
133 IntDefaultHandler, // External Bus Interface 0
134 IntDefaultHandler, // GPIO Port J
135 IntDefaultHandler, // GPIO Port K
136 IntDefaultHandler, // GPIO Port L
137 IntDefaultHandler, // SSI2 Rx and Tx
138 IntDefaultHandler, // SSI3 Rx and Tx
139 IntDefaultHandler, // UART3 Rx and Tx
140 IntDefaultHandler, // UART4 Rx and Tx
141 IntDefaultHandler, // UART5 Rx and Tx
142 IntDefaultHandler, // UART6 Rx and Tx
143 IntDefaultHandler, // UART7 Rx and Tx
144 IntDefaultHandler, // I2C2 Master and Slave
145 IntDefaultHandler, // I2C3 Master and Slave
146 IntDefaultHandler, // Timer 4 subtimer A
147 IntDefaultHandler, // Timer 4 subtimer B
148 IntDefaultHandler, // Timer 5 subtimer A
149 IntDefaultHandler, // Timer 5 subtimer B
150 IntDefaultHandler, // FPU
151 0, // Reserved
152 0, // Reserved
153 IntDefaultHandler, // I2C4 Master and Slave
154 IntDefaultHandler, // I2C5 Master and Slave
155 IntDefaultHandler, // GPIO Port M
156 IntDefaultHandler, // GPIO Port N
157 0, // Reserved
158 IntDefaultHandler, // Tamper
159 IntDefaultHandler, // GPIO Port P (Summary or P0)
160 IntDefaultHandler, // GPIO Port P1
161 IntDefaultHandler, // GPIO Port P2
162 IntDefaultHandler, // GPIO Port P3
163 IntDefaultHandler, // GPIO Port P4
164 IntDefaultHandler, // GPIO Port P5
165 IntDefaultHandler, // GPIO Port P6
166 IntDefaultHandler, // GPIO Port P7
167 IntDefaultHandler, // GPIO Port Q (Summary or Q0)
168 IntDefaultHandler, // GPIO Port Q1
169 IntDefaultHandler, // GPIO Port Q2
170 IntDefaultHandler, // GPIO Port Q3
171 IntDefaultHandler, // GPIO Port Q4
172 IntDefaultHandler, // GPIO Port Q5
173 IntDefaultHandler, // GPIO Port Q6
174 IntDefaultHandler, // GPIO Port Q7
175 IntDefaultHandler, // GPIO Port R
176 IntDefaultHandler, // GPIO Port S
177 IntDefaultHandler, // SHA/MD5 0
178 IntDefaultHandler, // AES 0
179 IntDefaultHandler, // DES3DES 0
180 IntDefaultHandler, // LCD Controller 0
181 IntDefaultHandler, // Timer 6 subtimer A
182 IntDefaultHandler, // Timer 6 subtimer B
183 IntDefaultHandler, // Timer 7 subtimer A
184 IntDefaultHandler, // Timer 7 subtimer B
185 IntDefaultHandler, // I2C6 Master and Slave
186 IntDefaultHandler, // I2C7 Master and Slave
187 IntDefaultHandler, // HIM Scan Matrix Keyboard 0
188 IntDefaultHandler, // One Wire 0
189 IntDefaultHandler, // HIM PS/2 0
190 IntDefaultHandler, // HIM LED Sequencer 0
191 IntDefaultHandler, // HIM Consumer IR 0
192 IntDefaultHandler, // I2C8 Master and Slave
193 IntDefaultHandler, // I2C9 Master and Slave
194 IntDefaultHandler // GPIO Port T
195 };
196
197 //*****************************************************************************
198 //
199 // The following are constructs created by the linker, indicating where the
200 // the "data" and "bss" segments reside in memory. The initializers for the
201 // for the "data" segment resides immediately following the "text" segment.
202 //
203 //*****************************************************************************
204 extern uint32_t _sidata;
205 extern uint32_t _sdata;
206 extern uint32_t _edata;
207 extern uint32_t _sbss;
208 extern uint32_t _ebss;
209
210 //*****************************************************************************
211 //
212 // This is the code that gets called when the processor first starts execution
213 // following a reset event. Only the absolutely necessary set is performed,
214 // after which the application supplied entry() routine is called. Any fancy
215 // actions (such as making decisions based on the reset cause register, and
216 // resetting the bits in that register) are left solely in the hands of the
217 // application.
218 //
219 //*****************************************************************************
ResetISR(void)220 void ResetISR(void)
221 {
222 uint32_t *pui32Src, *pui32Dest;
223
224 //
225 // Copy the data segment initializers from flash to SRAM.
226 //
227 pui32Src = &_sidata;
228 for(pui32Dest = &_sdata; pui32Dest < &_edata; )
229 {
230 *pui32Dest++ = *pui32Src++;
231 }
232
233 //
234 // Zero fill the bss segment.
235 //
236 __asm(" ldr r0, =_sbss\n"
237 " ldr r1, =_ebss\n"
238 " mov r2, #0\n"
239 " .thumb_func\n"
240 "zero_loop:\n"
241 " cmp r0, r1\n"
242 " it lt\n"
243 " strlt r2, [r0], #4\n"
244 " blt zero_loop");
245
246 //
247 // Enable the floating-point unit. This must be done here to handle the
248 // case where main() uses floating-point and the function prologue saves
249 // floating-point registers (which will fault if floating-point is not
250 // enabled). Any configuration of the floating-point unit using DriverLib
251 // APIs must be done here prior to the floating-point unit being enabled.
252 //
253 // Note that this does not use DriverLib since it might not be included in
254 // this project.
255 //
256 HWREG(NVIC_CPAC) = ((HWREG(NVIC_CPAC) &
257 ~(NVIC_CPAC_CP10_M | NVIC_CPAC_CP11_M)) |
258 NVIC_CPAC_CP10_FULL | NVIC_CPAC_CP11_FULL);
259
260 //
261 // Call the application's entry point.
262 //
263 extern int entry(void);
264 entry();
265 }
266
267 //*****************************************************************************
268 //
269 // This is the code that gets called when the processor receives a NMI. This
270 // simply enters an infinite loop, preserving the system state for examination
271 // by a debugger.
272 //
273 //*****************************************************************************
274 static void
NmiSR(void)275 NmiSR(void)
276 {
277 //
278 // Enter an infinite loop.
279 //
280 while(1)
281 {
282 }
283 }
284
285 //*****************************************************************************
286 //
287 // This is the code that gets called when the processor receives a fault
288 // interrupt. This simply enters an infinite loop, preserving the system state
289 // for examination by a debugger.
290 //
291 //*****************************************************************************
292 static void
FaultISR(void)293 FaultISR(void)
294 {
295 //
296 // Enter an infinite loop.
297 //
298 while(1)
299 {
300 }
301 }
302
303 //*****************************************************************************
304 //
305 // This is the code that gets called when the processor receives an unexpected
306 // interrupt. This simply enters an infinite loop, preserving the system state
307 // for examination by a debugger.
308 //
309 //*****************************************************************************
310 static void
IntDefaultHandler(void)311 IntDefaultHandler(void)
312 {
313 //
314 // Go into an infinite loop.
315 //
316 while(1)
317 {
318 }
319 }
320