1 /* 2 * Copyright (c) 2021, Shenzhen Academy of Aerospace Technology 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 * 2021-11-16 Dystopia the first version 9 */ 10 11 #ifndef __COMMON_H__ 12 #define __COMMON_H__ 13 14 #include <c6x.h> 15 #include <cslr_cgem.h> 16 #include <cslr_device.h> 17 #include <cslr_bootcfg.h> 18 #include <cslr_tmr.h> 19 #include <csl_tmr.h> 20 21 /* DSP core clock speed in Hz */ 22 #define DSP_CORE_SPEED_HZ 1000000000 23 24 extern CSL_CgemRegs * gp_cgem_regs; 25 extern CSL_BootcfgRegs * gp_bootcfg_regs; 26 27 /*----------------------Timer plus registers definition----------------*/ 28 typedef struct { 29 volatile unsigned int PID12; 30 volatile unsigned int EMUMGT_CLKSPD; 31 volatile unsigned int GPINT_EN; 32 volatile unsigned int GPDIR_DAT; 33 volatile unsigned int CNTLO; 34 volatile unsigned int CNTHI; 35 volatile unsigned int PRDLO; 36 volatile unsigned int PRDHI; 37 volatile unsigned int TCR; 38 volatile unsigned int TGCR; 39 volatile unsigned int WDTCR; 40 volatile unsigned int TLGC; 41 volatile unsigned int TLMR; 42 volatile unsigned int RELLO; 43 volatile unsigned int RELHI; 44 volatile unsigned int CAPLO; 45 volatile unsigned int CAPHI; 46 volatile unsigned int INTCTL_STAT; 47 volatile unsigned char RSVD0[24]; 48 volatile unsigned int TIMERLO_COMPARE_REG[8]; 49 volatile unsigned char RSVD1[32]; 50 } CSL_TmrPlusRegs; 51 52 #define TMR_TCR_READRSTMODE_HI_SHIFT (26) 53 #define TMR_TCR_CAPEVTMODE_LO_SHIFT (12) 54 #define TMR_TCR_CAPMODE_LO_SHIFT (11) 55 #define TMR_TCR_READRSTMODE_LO_SHIFT (10) 56 57 #define TMR_TCR_READRSTMODE_HI_MASK (1<<26) 58 #define TMR_TCR_CAPEVTMODE_LO_MASK (3<<12) 59 #define TMR_TCR_CAPMODE_LO_MASK (1<<11) 60 #define TMR_TCR_READRSTMODE_LO_MASK (1<<10) 61 62 #define TMR_TGCR_PLUSEN_SHIFT 4 63 #define TMR_TGCR_PLUSEN_MASK (1<<4) 64 65 #define TMR_INTCTLSTAT_EN_ALL_CLR_ALL 0x000F000F 66 67 #define CSL_TMR_WDTCR_WDKEY_CMD1 (0x0000A5C6u) 68 #define CSL_TMR_WDTCR_WDKEY_CMD2 (0x0000DA7Eu) 69 70 #define CSL_TMR_ENAMODE_CONT_RELOAD 3 71 72 extern CSL_TmrPlusRegs * gp_timer0_regs; 73 extern CSL_TmrPlusRegs * gp_timer1_regs; 74 extern CSL_TmrPlusRegs * gp_timer2_regs; 75 extern CSL_TmrPlusRegs * gp_timer3_regs; 76 extern CSL_TmrPlusRegs * gp_timer4_regs; 77 extern CSL_TmrPlusRegs * gp_timer5_regs; 78 extern CSL_TmrPlusRegs * gp_timer6_regs; 79 extern CSL_TmrPlusRegs * gp_timer7_regs; 80 extern CSL_TmrPlusRegs * gp_timer8_regs; 81 extern CSL_TmrPlusRegs * gp_timer_regs[]; 82 83 typedef enum 84 { 85 TIMER_ONE_SHOT_PULSE = 0, /*generate one shot pulse with timer*/ 86 TIMER_PERIODIC_PULSE, /*generate periodic pulse with timer*/ 87 TIMER_PERIODIC_CLOCK, /*generate periodic clock with timer*/ 88 /*generate periodic square wave with period reload feature, the difference 89 between wave and clock is the duty cycle of clock is always 50%*/ 90 TIMER_PERIODIC_WAVE, 91 TIMER_WATCH_DOG /*configure timer as watch dog*/ 92 }TTimerMode; 93 94 typedef struct { 95 int timer_num; /*select one timer*/ 96 TTimerMode timerMode; /*select function of the timer*/ 97 unsigned long long period; /*in the unit of DSP core clock/6*/ 98 unsigned long long reload_period; /*the reload value of period*/ 99 int pulseWidth; /*pulse width between 0~3*/ 100 }Timer64_Config; 101 102 /* Reset a 64-bit timer */ 103 extern void reset_timer(int timer_num); 104 105 /* Initailize a 64-bit timer */ 106 extern void timer64_init(Timer64_Config * tmrCfg); 107 108 extern void keystone_cpu_init(void); 109 110 #endif /* __COMMON_H__ */ 111