1 /* 2 ******************************************************************************* 3 * Copyright(C) NEC Electronics Corporation 2010 4 * All rights reserved by NEC Electronics Corporation. 5 * This program should be used on your own responsibility. 6 * NEC Electronics Corporation assumes no responsibility for any losses 7 * incurred by customers or third parties arising from the use of this file. 8 * 9 * This device driver was created by Applilet3 for V850ES/Jx3 10 * 32-Bit Single-Chip Microcontrollers 11 * Filename: CG_timer.h 12 * Abstract: This file implements device driver for Timer module. 13 * APIlib: Applilet3 for V850ES/Jx3 V2.01 [20 Apr 2010] 14 * Device: uPD70F3746 15 * Compiler: IAR Systems ICCV850 16 * Creation date: 6/26/2010 17 ******************************************************************************* 18 */ 19 20 #ifndef _MDTIMER_ 21 #define _MDTIMER_ 22 /* 23 ******************************************************************************* 24 ** Register bit define 25 ******************************************************************************* 26 */ 27 /* 28 TMP control register 0 (TPnCTL0) 29 */ 30 /* TMP operation control (TPnCE) */ 31 #define _00_TMP_OPERATION_DISABLE 0x00U /* disable internal operating clock operation (asynchronously reset TMPn) */ 32 #define _80_TMP_OPERATION_ENABLE 0x80U /* enable internal operating clock operation */ 33 /* Internal count clock selection (TPnCKS2 - TPnCKS0) */ 34 #define _00_TMP_INTERNAL_CLOCK0 0x00U /* fXX */ 35 #define _01_TMP_INTERNAL_CLOCK1 0x01U /* fXX/2 */ 36 #define _02_TMP_INTERNAL_CLOCK2 0x02U /* fXX/2^2 */ 37 #define _03_TMP_INTERNAL_CLOCK3 0x03U /* fXX/2^3 */ 38 #define _04_TMP_INTERNAL_CLOCK4 0x04U /* fXX/2^4 */ 39 #define _05_TMP_INTERNAL_CLOCK5 0x05U /* fXX/2^5 */ 40 #define _06_TMP_INTERNAL_CLOCK6 0x06U /* fXX/2^6 or fXX/2^8 */ 41 #define _07_TMP_INTERNAL_CLOCK7 0x07U /* fXX/2^7 or fXX/2^9 */ 42 43 /* 44 TMP control register 1 (TPnCTL1) 45 */ 46 /* Software trigger control (TPnEST) */ 47 #define _00_TMP_SOFTTRIGGER_OFF 0x00U /* no operation */ 48 #define _40_TMP_SOFTTRIGGER_ON 0x40U /* in one-shot pulse mode: One-shot pulse software trigger */ 49 /* in external trigger pulse output mode: Pulse output software trigger */ 50 /* Count clock selection (TPnEEE) */ 51 #define _00_TMP_INTERNAL_CLOCK 0x00U /* use the internal clock (clock selected with bits TPnCKS2 to TPnCKS0) */ 52 #define _20_TMP_EXTERNAL_CLOCK 0x20U /* use the external clock from the TIPn0 input pin */ 53 /* Timer mode selection (TPnMD2 - TPnMD0) */ 54 #define _00_TMP_MODE_INTERVAL 0x00U /* interval timer mode */ 55 #define _01_TMP_MODE_EXTERNALCOUNT 0x01U /* external event counter mode */ 56 #define _02_TMP_MODE_EXTERNALTRG 0x02U /* external trigger pulse output mode */ 57 #define _03_TMP_MODE_ONESHOT 0x03U /* one-shot pulse mode */ 58 #define _04_TMP_MODE_PWM 0x04U /* PWM mode */ 59 #define _05_TMP_MODE_FREERUNNING 0x05U /* free-running mode */ 60 #define _06_TMP_MODE_PULSEMEASURE 0x06U /* pulse width measurement mode */ 61 62 /* 63 TMP I/O control register 0 (TPnIOC0) 64 */ 65 /* TOPn0 pin output level setting (TPnOL0) */ 66 #define _00_TMP_OUTPUT0_NORMAL 0x00U /* normal output */ 67 #define _02_TMP_OUTPUT0_INVERTED 0x02U /* inverted output */ 68 /* TOPn0 pin output setting (TPnOE0) */ 69 #define _00_TMP_OUTPUT0_DISABLE 0x00U /* disable timer output */ 70 #define _01_TMP_OUTPUT0_ENABLE 0x01U /* enable timer output (TOPn0 pin outputs pulses) */ 71 /* TOPn1 pin output level setting (TPnOL1) */ 72 #define _00_TMP_OUTPUT1_NORMAL 0x00U /* normal output */ 73 #define _08_TMP_OUTPUT1_INVERTED 0x08U /* inverted output */ 74 /* TOPn1 pin output setting (TPnOE1) */ 75 #define _00_TMP_OUTPUT1_DISABLE 0x00U /* disable timer output */ 76 #define _04_TMP_OUTPUT1_ENABLE 0x04U /* enable timer output (TOPn1 pin outputs pulses) */ 77 78 /* 79 TMP I/O control register 1 (TPnIOC1) 80 */ 81 /* Capture trigger input signal (TIPn1 pin) valid edge setting (TPnIS3,TPnIS2) */ 82 #define _00_TMP_INPUT1_EDGE_NONE 0x00U /* detect no edge (capture operation is invalid) */ 83 #define _04_TMP_INPUT1_EDGE_RISING 0x04U /* detection of rising edge */ 84 #define _08_TMP_INPUT1_EDGE_FALLING 0x08U /* detection of falling edge */ 85 #define _0C_TMP_INPUT1_EDGE_BOTH 0x0CU /* detection of both edges */ 86 /* Capture trigger input signal (TIPn0 pin) valid edge setting (TPnIS1,TPnIS0) */ 87 #define _00_TMP_INPUT0_EDGE_NONE 0x00U /* detect no edge (capture operation is invalid) */ 88 #define _01_TMP_INPUT0_EDGE_RISING 0x01U /* detection of rising edge */ 89 #define _02_TMP_INPUT0_EDGE_FALLING 0x02U /* detection of falling edge */ 90 #define _03_TMP_INPUT0_EDGE_BOTH 0x03U /* detection of both edges */ 91 92 /* 93 TMP I/O control register 2 (TPnIOC2) 94 */ 95 /* External event count input signal (TIPn0 pin) valid edge setting (TPnEES1,TPnEES0) */ 96 #define _00_TMP_EXTCOUNT_EDGE_NONE 0x00U /* detect no edge (external event count is invalid) */ 97 #define _04_TMP_EXTCOUNT_EDGE_RISING 0x04U /* detection of rising edge */ 98 #define _08_TMP_EXTCOUNT_EDGE_FALLING 0x08U /* detection of falling edge */ 99 #define _0C_TMP_EXTCOUNT_EDGE_BOTH 0x0CU /* detection of both edges */ 100 /* External trigger input signal (TIPn0 pin) valid edge setting (TPnETS1,TPnETS0) */ 101 #define _00_TMP_EXTTRIGGER_EDGE_NONE 0x00U /* detect no edge (external trigger is invalid) */ 102 #define _01_TMP_EXTTRIGGER_EDGE_RISING 0x01U /* detection of rising edge */ 103 #define _02_TMP_EXTTRIGGER_EDGE_FALLING 0x02U /* detection of falling edge */ 104 #define _03_TMP_EXTTRIGGER_EDGE_BOTH 0x03U /* detection of both edges */ 105 106 /* 107 TMP option register 0 (TPnOPT0) 108 */ 109 /* TPnCCR1 register capture/compare selection (TPnCCS1) */ 110 #define _00_TMP_CCR1_COMPARE 0x00U /* compare register */ 111 #define _20_TMP_CCR1_CAPTURE 0x20U /* capture register */ 112 /* TPnCCR0 register capture/compare selection (TPnCCS0) */ 113 #define _00_TMP_CCR0_COMPARE 0x00U /* compare register */ 114 #define _10_TMP_CCR0_CAPTURE 0x10U /* capture register */ 115 /* TMPn overflow detection flag (TPnOVF) */ 116 #define _01_TMP_OVERFLOW_OCCUR 0x01U /* overflow occurred */ 117 #define _00_TMP_OVERFLOW_CLEAR 0x00U /* clear overflow */ 118 119 /* 120 TMQ0 control register 0 (TQ0CTL0) 121 */ 122 /* TMQ operation control (TQ0CE) */ 123 #define _00_TMQ_OPERATION_DISABLE 0x00U /* disable internal operating clock operation (asynchronously reset TMQ0) */ 124 #define _80_TMQ_OPERATION_ENABLE 0x80U /* enable internal operating clock operation */ 125 /* Internal count clock selection (TQ0CKS2 - TQ0CKS0) */ 126 #define _00_TMQ_INTERNAL_CLOCK0 0x00U /* fXX */ 127 #define _01_TMQ_INTERNAL_CLOCK1 0x01U /* fXX/2 */ 128 #define _02_TMQ_INTERNAL_CLOCK2 0x02U /* fXX/2^2 */ 129 #define _03_TMQ_INTERNAL_CLOCK3 0x03U /* fXX/2^3 */ 130 #define _04_TMQ_INTERNAL_CLOCK4 0x04U /* fXX/2^4 */ 131 #define _05_TMQ_INTERNAL_CLOCK5 0x05U /* fXX/2^5 */ 132 #define _06_TMQ_INTERNAL_CLOCK6 0x06U /* fXX/2^6 */ 133 #define _07_TMQ_INTERNAL_CLOCK7 0x07U /* fXX/2^7 */ 134 135 /* 136 TMQ0 control register 1 (TQ0CTL1) 137 */ 138 /* Software trigger control (TQ0EST) */ 139 #define _00_TMQ_SOFTTRIGGER_OFF 0x00U /* no operation */ 140 #define _40_TMQ_SOFTTRIGGER_ON 0x40U /* in one-shot pulse mode: One-shot pulse software trigger */ 141 /* in external trigger pulse output mode: Pulse output software trigger */ 142 /* Count clock selection (TQ0EEE) */ 143 #define _00_TMQ_INTERNAL_CLOCK 0x00U /* use the internal clock (clock selected with bits TQ0CKS2 to TQ0CKS0) */ 144 #define _20_TMQ_EXTERNAL_CLOCK 0x20U /* use the external clock from the TIQ00 input pin */ 145 /* Timer mode selection (TQ0MD2 - TQ0MD0) */ 146 #define _00_TMQ_MODE_INTERVAL 0x00U /* interval timer mode */ 147 #define _01_TMQ_MODE_EXTERNALCOUNT 0x01U /* external event counter mode */ 148 #define _02_TMQ_MODE_EXTERNALTRG 0x02U /* external trigger pulse output mode */ 149 #define _03_TMQ_MODE_ONESHOT 0x03U /* one-shot pulse mode */ 150 #define _04_TMQ_MODE_PWM 0x04U /* PWM mode */ 151 #define _05_TMQ_MODE_FREERUNNING 0x05U /* free-running mode */ 152 #define _06_TMQ_MODE_PULSEMEASURE 0x06U /* pulse width measurement mode */ 153 154 /* 155 TMQ0 I/O control register 0 (TQ0IOC0) 156 */ 157 /* TOQ00 pin output level setting (TQ0OL0) */ 158 #define _00_TMQ_OUTPUT0_NORMAL 0x00U /* normal output */ 159 #define _02_TMQ_OUTPUT0_INVERTED 0x02U /* inverted output */ 160 /* TOQ00 pin output setting (TQ0OE0) */ 161 #define _00_TMQ_OUTPUT0_DISABLE 0x00U /* disable timer output */ 162 #define _01_TMQ_OUTPUT0_ENABLE 0x01U /* enable timer output (TOQ00 pin outputs pulses) */ 163 /* TOQ01 pin output level setting (TQ0OL1) */ 164 #define _00_TMQ_OUTPUT1_NORMAL 0x00U /* normal output */ 165 #define _08_TMQ_OUTPUT1_INVERTED 0x08U /* inverted output */ 166 /* TOQ01 pin output setting (TQ0OE1) */ 167 #define _00_TMQ_OUTPUT1_DISABLE 0x00U /* disable timer output */ 168 #define _04_TMQ_OUTPUT1_ENABLE 0x04U /* enable timer output (TOQ01 pin outputs pulses) */ 169 /* TOQ02 pin output level setting (TQ0OL2) */ 170 #define _00_TMQ_OUTPUT2_NORMAL 0x00U /* normal output */ 171 #define _20_TMQ_OUTPUT2_INVERTED 0x20U /* inverted output */ 172 /* TOQ02 pin output setting (TQ0OE2) */ 173 #define _00_TMQ_OUTPUT2_DISABLE 0x00U /* disable timer output */ 174 #define _10_TMQ_OUTPUT2_ENABLE 0x10U /* enable timer output (TOQ02 pin outputs pulses) */ 175 /* TOQ03 pin output level setting (TQ0OL3) */ 176 #define _00_TMQ_OUTPUT3_NORMAL 0x00U /* normal output */ 177 #define _80_TMQ_OUTPUT3_INVERTED 0x80U /* inverted output */ 178 /* TOQ03 pin output setting (TQ0OE3) */ 179 #define _00_TMQ_OUTPUT3_DISABLE 0x00U /* disable timer output */ 180 #define _40_TMQ_OUTPUT3_ENABLE 0x40U /* enable timer output (TOQ03 pin outputs pulses) */ 181 182 /* 183 TMQ0 I/O control register 1 (TQ0IOC1) 184 */ 185 /* Capture trigger input signal (TIQ00 pin) valid edge setting (TQ0IS1,TQ0IS0) */ 186 #define _00_TMQ_INPUT0_EDGE_NONE 0x00U /* detect no edge (capture operation is invalid) */ 187 #define _01_TMQ_INPUT0_EDGE_RISING 0x01U /* detection of rising edge */ 188 #define _02_TMQ_INPUT0_EDGE_FALLING 0x02U /* detection of falling edge */ 189 #define _03_TMQ_INPUT0_EDGE_BOTH 0x03U /* detection of both edges */ 190 /* Capture trigger input signal (TIQ01 pin) valid edge setting (TQ0IS3,TQ0IS2) */ 191 #define _00_TMQ_INPUT1_EDGE_NONE 0x00U /* detect no edge (capture operation is invalid) */ 192 #define _04_TMQ_INPUT1_EDGE_RISING 0x04U /* detection of rising edge */ 193 #define _08_TMQ_INPUT1_EDGE_FALLING 0x08U /* detection of falling edge */ 194 #define _0C_TMQ_INPUT1_EDGE_BOTH 0x0CU /* detection of both edges */ 195 /* Capture trigger input signal (TIQ02 pin) valid edge setting (TQ0IS5,TQ0IS4) */ 196 #define _00_TMQ_INPUT2_EDGE_NONE 0x00U /* detect no edge (capture operation is invalid) */ 197 #define _10_TMQ_INPUT2_EDGE_RISING 0x10U /* detection of rising edge */ 198 #define _20_TMQ_INPUT2_EDGE_FALLING 0x20U /* detection of falling edge */ 199 #define _30_TMQ_INPUT2_EDGE_BOTH 0x30U /* detection of both edges */ 200 /* Capture trigger input signal (TIQ03 pin) valid edge setting (TQ0IS7,TQ0IS6) */ 201 #define _00_TMQ_INPUT3_EDGE_NONE 0x00U /* detect no edge (capture operation is invalid) */ 202 #define _40_TMQ_INPUT3_EDGE_RISING 0x40U /* detection of rising edge */ 203 #define _80_TMQ_INPUT3_EDGE_FALLING 0x80U /* detection of falling edge */ 204 #define _C0_TMQ_INPUT3_EDGE_BOTH 0xC0U /* detection of both edges */ 205 206 /* 207 TMQ0 I/O control register 2 (TQ0IOC2) 208 */ 209 /* External event count input signal (TIQ00 pin) valid edge setting (TQ0EES1,TQ0EES0) */ 210 #define _00_TMQ_EXTCOUNT_EDGE_NONE 0x00U /* detect no edge (external event count is invalid) */ 211 #define _04_TMQ_EXTCOUNT_EDGE_RISING 0x04U /* detection of rising edge */ 212 #define _08_TMQ_EXTCOUNT_EDGE_FALLING 0x08U /* detection of falling edge */ 213 #define _0C_TMQ_EXTCOUNT_EDGE_BOTH 0x0CU /* detection of both edges */ 214 /* External trigger input signal (TIQ00 pin) valid edge setting (TQ0ETS1,TQ0ETS0) */ 215 #define _00_TMQ_EXTTRIGGER_EDGE_NONE 0x00U /* detect no edge (external trigger is invalid) */ 216 #define _01_TMQ_EXTTRIGGER_EDGE_RISING 0x01U /* detection of rising edge */ 217 #define _02_TMQ_EXTTRIGGER_EDGE_FALLING 0x02U /* detection of falling edge */ 218 #define _03_TMQ_EXTTRIGGER_EDGE_BOTH 0x03U /* detection of both edges */ 219 220 /* 221 TMQ0 option register 0 (TQ0OPT0) 222 */ 223 /* TQ0CCR3 register capture/compare selection (TQ0CCS3) */ 224 #define _00_TMQ_CCR3_COMPARE 0x00U /* compare register */ 225 #define _80_TMQ_CCR3_CAPTURE 0x80U /* capture register */ 226 /* TQ0CCR2 register capture/compare selection (TQ0CCS2) */ 227 #define _00_TMQ_CCR2_COMPARE 0x00U /* compare register */ 228 #define _40_TMQ_CCR2_CAPTURE 0x40U /* capture register */ 229 /* TQ0CCR1 register capture/compare selection (TQ0CCS1) */ 230 #define _00_TMQ_CCR1_COMPARE 0x00U /* compare register */ 231 #define _20_TMQ_CCR1_CAPTURE 0x20U /* capture register */ 232 /* TQ0CCR0 register capture/compare selection (TQ0CCS0) */ 233 #define _00_TMQ_CCR0_COMPARE 0x00U /* compare register */ 234 #define _10_TMQ_CCR0_CAPTURE 0x10U /* capture register */ 235 /* TMQ0 overflow detection flag (TQ0OVF) */ 236 #define _01_TMQ_OVERFLOW_OCCUR 0x01U /* overflow occurred */ 237 #define _00_TMQ_OVERFLOW_CLEAR 0x00U /* clear overflow */ 238 239 /* 240 TMM0 control register 0 (TM0CTL0) 241 */ 242 /* TMM0 operation control (TM0CE) */ 243 #define _00_TMM_OPERATION_DISABLE 0x00U /* disable internal operating clock operation (asynchronously reset TMM0) */ 244 #define _80_TMM_OPERATION_ENABLE 0x80U /* enable internal operating clock operation */ 245 /* Internal count clock selection (TM0CKS2 - TM0CKS0) */ 246 #define _00_TMM_INTERNAL_CLOCK0 0x00U /* fXX */ 247 #define _01_TMM_INTERNAL_CLOCK1 0x01U /* fXX/2 */ 248 #define _02_TMM_INTERNAL_CLOCK2 0x02U /* fXX/4 */ 249 #define _03_TMM_INTERNAL_CLOCK3 0x03U /* fXX/64 */ 250 #define _04_TMM_INTERNAL_CLOCK4 0x04U /* fXX/512 */ 251 #define _05_TMM_INTERNAL_CLOCK5 0x05U /* INTWT */ 252 #define _06_TMM_INTERNAL_CLOCK6 0x06U /* fR/8 */ 253 #define _07_TMM_INTERNAL_CLOCK7 0x07U /* fXT */ 254 /* 255 ******************************************************************************* 256 ** Macro define 257 ******************************************************************************* 258 */ 259 /* TMP0 compare register 0 (TP0CCR0)*/ 260 #define _9C3F_TMP0_CCR0_VALUE 0x9C3FU 261 enum TMChannel 262 { 263 TMCHANNEL0, TMCHANNEL1, TMCHANNEL2, TMCHANNEL3 264 }; 265 /* 266 ******************************************************************************* 267 ** Function define 268 ******************************************************************************* 269 */ 270 void TAB0_Init(void); 271 void TAB0_Start(void); 272 void TAB0_Stop(void); 273 MD_STATUS TAB0_ChangeTimerCondition(USHORT *array_reg, UCHAR array_num); 274 __interrupt void MD_INTTP0CC0(void); 275 276 /* Start user code for function. Do not edit comment generated here */ 277 /* End user code. Do not edit comment generated here */ 278 #endif 279