1 #ifndef __UART_H__ 2 #define __UART_H__ 3 4 #define BAUD_RATE 9600 5 6 /* 7 UARTAn control register 0 (UAnCTL0) 8 */ 9 #define _10_UARTA_UAnCTL0_INITIALVALUE 0x10U 10 /* UARTAn operation control (UAnPWR) */ 11 #define _00_UARTA_OPERATION_DISABLE 0x00U /* disable UARTAn operation (UARTAn reset asynchronously) */ 12 #define _80_UARTA_OPERATION_ENABLE 0x80U /* enable UARTAn operation */ 13 /* Transmission operation enable (UAnTXE) */ 14 #define _00_UARTA_TRANSMISSION_DISABLE 0x00U /* disable transmission operation */ 15 #define _40_UARTA_TRANSMISSION_ENABLE 0x40U /* enable transmission operation */ 16 /* Reception operation enable (UAnRXE) */ 17 #define _00_UARTA_RECEPTION_DISABLE 0x00U /* disable reception operation */ 18 #define _20_UARTA_RECEPTION_ENABLE 0x20U /* enable reception operation */ 19 /* Transfer direction selection (UAnDIR) */ 20 #define _00_UARTA_TRANSFDIR_MSB 0x00U /* MSB-first transfer */ 21 #define _10_UARTA_TRANSFDIR_LSB 0x10U /* LSB-first transfer */ 22 /* Parity selection during transmission/reception (UAnPS1,UAnPS0) */ 23 #define _00_UARTA_PARITY_NONE 0x00U /* no parity output/reception with no parity */ 24 #define _04_UARTA_PARITY_ZREO 0x04U /* 0 parity output/reception with 0 parity */ 25 #define _08_UARTA_PARITY_ODD 0x08U /* odd parity output/odd parity check */ 26 #define _0C_UARTA_PARITY_EVEN 0x0CU /* even parity output/even parity check */ 27 /* Specification of data character length of 1 frame of transmit/receive data (UAnCL) */ 28 #define _00_UARTA_DATALENGTH_7BIT 0x00U /* 7 bits */ 29 #define _02_UARTA_DATALENGTH_8BIT 0x02U /* 8 bits */ 30 /* Specification of length of stop bit for transmit data (UAnSL) */ 31 #define _00_UARTA_STOPLENGTH_1BIT 0x00U /* 1 bit */ 32 #define _01_UARTA_STOPLENGTH_2BIT 0x01U /* 2 bits */ 33 34 /* 35 UARTAn base clock selects register (UAnCTL1) 36 */ 37 /* UAnCTL1 register (UAnCKS3 - UAnCKS0) */ 38 #define _00_UARTA_BASECLK_FXX_2 0x00U /* fXX/2 */ 39 #define _01_UARTA_BASECLK_FXX_4 0x01U /* fXX/2^2 */ 40 #define _02_UARTA_BASECLK_FXX_8 0x02U /* fXX/2^3 */ 41 #define _03_UARTA_BASECLK_FXX_16 0x03U /* fXX/2^4 */ 42 #define _04_UARTA_BASECLK_FXX_32 0x04U /* fXX/2^5 */ 43 #define _05_UARTA_BASECLK_FXX_64 0x05U /* fXX/2^6 */ 44 #define _06_UARTA_BASECLK_FXX_128 0x06U /* fXX/2^7 */ 45 #define _07_UARTA_BASECLK_FXX_256 0x07U /* fXX/2^8 */ 46 #define _08_UARTA_BASECLK_FXX_512 0x08U /* fXX/2^9 */ 47 #define _09_UARTA_BASECLK_FXX_1024 0x09U /* fXX/2^10 */ 48 #define _0A_UARTA_BASECLK_FXX_2048 0x0AU /* fXX/2^11 */ 49 #define _0B_UARTA_BASECLK_FXX_4096 0x0BU /* fXX/2^12 */ 50 51 /* 52 UARTAn option control register 0 (UAnOPT0) 53 */ 54 #define _14_UARTA_UAnOPT0_INITIALVALUE 0x14U 55 /* Transmit data level bit(UAnTDL) */ 56 #define _00_UARTA_TRAN_DATALEVEL_NORMAL 0x00U /* normal output of transfer data */ 57 #define _02_UARTA_TRAN_DATALEVEL_INVERTED 0x02U /* inverted output of transfer data */ 58 /* Receive data level bit(UAnRDL) */ 59 #define _00_UARTA_REC_DATALEVEL_NORMAL 0x00U /* normal input of transfer data */ 60 #define _01_UARTA_REC_DATALEVEL_INVERTED 0x01U /* inverted input of transfer data */ 61 62 /* 63 CSIBn control register 0 (CBnCTL0) 64 */ 65 /* Specification of CSIBn operation disable/enable (CBnPWR)*/ 66 #define _00_CSIB_OPERATION_DISABLE 0x00U /* disable CSIBn operation and reset the CBnSTR register */ 67 #define _80_CSIB_OPERATION_ENABLE 0x80U /* enable CSIBn operation */ 68 /* Specification of transmit operation disable/enable (CBnTXE)*/ 69 #define _00_CSIB_TRANSMIT_DISABLE 0x00U /* disable transmit operation */ 70 #define _40_CSIB_TRANSMIT_ENABLE 0x40U /* enable transmit operation */ 71 /* Specification of receive operation disable/enable (CBnRXE)*/ 72 #define _00_CSIB_RECEIVE_DISABLE 0x00U /* disable receive operation */ 73 #define _20_CSIB_RECEIVE_ENABLE 0x20U /* enable receive operation */ 74 /* Specification of transfer direction mode (MSB/LSB) (CBnDIR) */ 75 #define _00_CSIB_DATA_MSB 0x00U /* MSB first */ 76 #define _10_CSIB_DATA_LSB 0x10U /* LSB first */ 77 /* Transfer mode specification (CBnTMS) */ 78 #define _00_CSIB_MODE_SINGLE 0x00U /* single transfer mode */ 79 #define _02_CSIB_MODE_CONTINUOUS 0x02U /* continuous transfer mode */ 80 /* Specification of start transfer disable/enable (CBnSCE) */ 81 #define _00_CSIB_STARTTRG_INVALID 0x00U /* communication start trigger invalid */ 82 #define _01_CSIB_STARTTRG_VALID 0x01U /* communication start trigger valid */ 83 84 /* 85 CSIBn control register 1 (CBnCTL1) 86 */ 87 /* Specification of data transmission/reception timing in relation to SCKBn (CBnCKP, CBnDAP) */ 88 #define _00_CSIB_DATA_TIMING1 0x00U /* communication type 1 */ 89 #define _08_CSIB_DATA_TIMING2 0x08U /* communication type 2 */ 90 #define _10_CSIB_DATA_TIMING3 0x10U /* communication type 3 */ 91 #define _18_CSIB_DATA_TIMING4 0x18U /* communication type 4 */ 92 /* Specification of input clock (CBnCKS2 - CBnCKS0) */ 93 #define _00_CSIB_CLOCK_1 0x00U /* fXX /2 */ 94 #define _01_CSIB_CLOCK_2 0x01U /* fXX/4 */ 95 #define _02_CSIB_CLOCK_3 0x02U /* fXX /8 */ 96 #define _03_CSIB_CLOCK_4 0x03U /* fXX /16 */ 97 #define _04_CSIB_CLOCK_5 0x04U /* fXX /32 */ 98 #define _05_CSIB_CLOCK_6 0x05U /* fXX /64 */ 99 #define _06_CSIB_CLOCK_7 0x06U /* fBRGm */ 100 #define _07_CSIB_CLOCK_EXT 0x07U /* external clock SCKBn */ 101 102 /* 103 CSIBn control register 2 (CBnCTL2) 104 */ 105 /* Serial register bit length (CBnCL3,CBnCL2,CBnCL1,CBnCL0) */ 106 #define _00_CSIB_DATA_LENGTH_8 0x00U /* 8 bits */ 107 #define _01_CSIB_DATA_LENGTH_9 0x01U /* 9 bits */ 108 #define _02_CSIB_DATA_LENGTH_10 0x02U /* 10 bits */ 109 #define _03_CSIB_DATA_LENGTH_11 0x03U /* 11 bits */ 110 #define _04_CSIB_DATA_LENGTH_12 0x04U /* 12 bits */ 111 #define _05_CSIB_DATA_LENGTH_13 0x05U /* 13 bits */ 112 #define _06_CSIB_DATA_LENGTH_14 0x06U /* 14 bits */ 113 #define _07_CSIB_DATA_LENGTH_15 0x07U /* 15 bits */ 114 #define _08_CSIB_DATA_LENGTH_16 0x08U /* 16 bits */ 115 116 /* 117 CSIBn status register (CBnSTR) 118 */ 119 /* Communication status flag (CBnTSF) */ 120 #define _00_CSIB_COMMUNICATION_STOP 0x00U /* communication stopped */ 121 #define _80_CSIB_COMMUNICATING 0x80U /* communicating */ 122 /* Overrun error flag (CBnOVE) */ 123 #define _00_CSIB_OVERRUN_NONE 0x00U /* no overrun */ 124 #define _01_CSIB_OVERRUN 0x01U /* overrun */ 125 126 /* 127 BRGm prescaler mode registers (PRSMm) 128 */ 129 /* Baud rate output(BGCEm) */ 130 #define _00_CSIB_FBRGM_DISABLE 0x00U /* baudrate output disabled */ 131 #define _10_CSIB_FBRGM_ENABLE 0x10U /* baudrate output enabled */ 132 /* Input clock selection (BGCSm1,BGCSm0) */ 133 #define _00_CSIB_FBGCS_0 0x00U /* fXX */ 134 #define _01_CSIB_FBGCS_1 0x01U /* fXX/2 */ 135 #define _02_CSIB_FBGCS_2 0x02U /* fXX/4 */ 136 #define _03_CSIB_FBGCS_3 0x03U /* fXX/8 */ 137 #define CB4RIC UA0RIC 138 #define CB4TIC UA0TIC 139 #define CB0RIC IICIC1 140 141 /* 142 IIC control register (IICCn) 143 */ 144 /* IIC operation enable (IICEn) */ 145 #define _80_IIC_OPERATION 0x80U 146 #define _00_IIC_OPERATION_DISABLE 0x00U /* stop operation */ 147 #define _80_IIC_OPERATION_ENABLE 0x80U /* enable operation */ 148 /* Exit from communications (LRELn) */ 149 #define _40_IIC_COMMUNICATION 0x40U 150 #define _00_IIC_COMMUNICATION_NORMAL 0x00U /* normal operation */ 151 #define _40_IIC_COMMUNICATION_EXIT 0x40U /* exit from current communication */ 152 /* Wait cancellation (WRELn) */ 153 #define _20_IIC_WAITCANCEL 0x20U 154 #define _00_IIC_WAIT_NOTCANCEL 0x00U /* do not cancel wait */ 155 #define _20_IIC_WAIT_CANCEL 0x20U /* cancel wait */ 156 /* Generation of interrupt when stop condition (SPIEn) */ 157 #define _10_IIC_STOPINT 0x10U 158 #define _00_IIC_STOPINT_DISABLE 0x00U /* disable */ 159 #define _10_IIC_STOPINT_ENABLE 0x10U /* enable */ 160 /* Wait and interrupt generation (WTIMn) */ 161 #define _08_IIC_WAITINT 0x08U 162 #define _00_IIC_WAITINT_CLK8FALLING 0x00U /* generate at the eighth clock falling edge */ 163 #define _08_IIC_WAITINT_CLK9FALLING 0x08U /* generated at the ninth clock falling edge */ 164 /* Acknowledgement control (ACKEn) */ 165 #define _04_IIC_ACK 0x04 166 #define _00_IIC_ACK_DISABLE 0x00U /* disable acknowledgement */ 167 #define _04_IIC_ACK_ENABLE 0x04U /* enable acknowledgement */ 168 /* Start condition trigger (STTn) */ 169 #define _02_IIC_STARTCONDITION 0x02U 170 #define _00_IIC_START_NOTGENERATE 0x00U /* do not generate start condition */ 171 #define _02_IIC_START_GENERATE 0x02U /* generate start condition */ 172 /* Stop condition trigger (SPTn) */ 173 #define _01_IIC_STOPCONDITION 0x01U 174 #define _00_IIC_STOP_NOTGENERATE 0x00U /* do not generate stop condition */ 175 #define _01_IIC_STOP_GENERATE 0x01U /* generate stop condition */ 176 177 /* 178 IIC Status Register (IICSn) 179 */ 180 /* Master device status (MSTSn) */ 181 #define _80_IIC_MASTERSTATUS 0x80U 182 #define _00_IIC_STATUS_NOTMASTER 0x00U /* slave device status or communication standby status */ 183 #define _80_IIC_STATUS_MASTER 0x80U /* master device communication status */ 184 /* Detection of arbitration loss (ALDn) */ 185 #define _40_IIC_ARBITRATION 0x40U 186 #define _00_IIC_ARBITRATION_NO 0x00U /* arbitration win or no arbitration */ 187 #define _40_IIC_ARBITRATION_LOSS 0x40U /* arbitration loss */ 188 /* Detection of extension code reception (EXCn) */ 189 #define _20_IIC_EXTENSIONCODE 0x20U 190 #define _00_IIC_EXTCODE_NOT 0x00U /* extension code not received */ 191 #define _20_IIC_EXTCODE_RECEIVED 0x20U /* extension code received */ 192 /* Detection of matching addresses (COIn) */ 193 #define _10_IIC_ADDRESSMATCH 0x10U 194 #define _00_IIC_ADDRESS_NOTMATCH 0x00U /* addresses do not match */ 195 #define _10_IIC_ADDRESS_MATCH 0x10U /* addresses match */ 196 /* Detection of transmit/receive status (TRCn) */ 197 #define _08_IIC_STATUS 0x08U 198 #define _00_IIC_STATUS_RECEIVE 0x00U /* receive status */ 199 #define _08_IIC_STATUS_TRANSMIT 0x08U /* transmit status */ 200 /* Detection of acknowledge signal (ACKDn) */ 201 #define _04_IIC_ACKDETECTION 0x04U 202 #define _00_IIC_ACK_NOTDETECTED 0x00U /* ACK signal was not detected */ 203 #define _04_IIC_ACK_DETECTED 0x04U /* ACK signal was detected */ 204 /* Detection of start condition (STDn) */ 205 #define _02_IIC_STARTDETECTION 0x02U 206 #define _00_IIC_START_NOTDETECTED 0x00U /* start condition not detected */ 207 #define _02_IIC_START_DETECTED 0x02U /* start condition detected */ 208 /* Detection of stop condition (SPDn) */ 209 #define _01_IIC_STOPDETECTION 0x01U 210 #define _00_IIC_STOP_NOTDETECTED 0x00U /* stop condition not detected */ 211 #define _01_IIC_STOP_DETECTED 0x01U /* stop condition detected */ 212 213 /* 214 IIC Flag Register (IICFn) 215 */ 216 /* STTn clear flag (STCFn) */ 217 #define _80_IIC_STARTFLAG 0x80U 218 #define _00_IIC_STARTFLAG_GENERATE 0x00U /* generate start condition */ 219 #define _80_IIC_STARTFLAG_UNSUCCESSFUL 0x80U /* start condition generation unsuccessful */ 220 /* IIC bus status flag (IICBSYn) */ 221 #define _40_IIC_BUSSTATUS 0x40U 222 #define _00_IIC_BUS_RELEASE 0x00U /* bus release status */ 223 #define _40_IIC_BUS_COMMUNICATION 0x40U /* bus communication status */ 224 /* Initial start enable trigger (STCENn) */ 225 #define _02_IIC_STARTWITHSTOP 0x02U 226 #define _00_IIC_START_WITHSTOP 0x00U /* generation of a start condition upon detection of a stop condition */ 227 #define _02_IIC_START_WITHOUTSTOP 0x02U /* generation of a start condition without detecting a stop condition */ 228 /* Communication reservation function disable bit (IICRSVn) */ 229 #define _01_IIC_RESERVATION 0x01U 230 #define _00_IIC_RESERVATION_ENABLE 0x00U /* enable communication reservation */ 231 #define _01_IIC_RESERVATION_DISABLE 0x01U /* disable communication reservation */ 232 233 /* 234 IIC clock selection register (IICCLn) 235 */ 236 #define _00_IICCL_INITIALVALUE 0x00U 237 /* Detection of SCL0n pin level (CLDn) */ 238 #define _20_IIC_SCLLEVEL 0x20U 239 #define _00_IIC_SCL_LOW 0x00U /* clock line at low level */ 240 #define _20_IIC_SCL_HIGH 0x20U /* clock line at high level */ 241 /* Detection of SDA0 pin level (DADn) */ 242 #define _10_IIC_SDALEVEL 0x10U 243 #define _00_IIC_SDA_LOW 0x00U /* data line at low level */ 244 #define _10_IIC_SDA_HIGH 0x10U /* data line at high level */ 245 /* Operation mode switching (SMCn) */ 246 #define _08_IIC_OPERATIONMODE 0x08U 247 #define _00_IIC_MODE_STANDARD 0x00U /* operates in standard mode */ 248 #define _08_IIC_MODE_HIGHSPEED 0x08U /* operates in high-speed mode */ 249 /* Digital filter operation control (DFCn) */ 250 #define _04_IIC_DIGITALFILTER 0x04U 251 #define _00_IIC_FILTER_OFF 0x00U /* digital filter off */ 252 #define _04_IIC_FILTER_ON 0x04U /* digital filter on */ 253 /* Operation mode switching (CLn1, CLn0) */ 254 #define _03_IIC_CLOCKSELECTION 0x03U 255 /* Combine of (CLn1, CLn0)*/ 256 #define _00_IIC_CLOCK0 0x00U 257 #define _01_IIC_CLOCK1 0x01U 258 #define _02_IIC_CLOCK2 0x02U 259 #define _03_IIC_CLOCK3 0x03U 260 261 /* 262 IIC division clock select register (OCKSn) 263 */ 264 #define _10_IIC_SELECTED0 0x10U 265 #define _11_IIC_SELECTED1 0x11U 266 #define _12_IIC_SELECTED2 0x12U 267 #define _13_IIC_SELECTED3 0x13U 268 #define _18_IIC_SELECTED4 0x18U 269 270 /* 271 IIC function expansion register 0 (IICXn) 272 */ 273 /* IIC clock expension (CLXn) */ 274 #define _01_IIC_CLOCKEXPENSION 0x01U 275 #define _00_IIC_EXPENSION0 0x00U 276 #define _01_IIC_EXPENSION1 0x01U 277 #define _80_ADDRESS_COMPLETE 0x80U 278 #define _00_IIC_MASTER_FLAG_CLEAR 0x00U 279 #define IICIC2 UA1RIC 280 #define IICIC0 UA2RIC 281 /* 282 ******************************************************************************* 283 ** Macro define 284 ******************************************************************************* 285 */ 286 /* Selection of 8-bit counter output clock (UA1BRS7~UA1BRS0) */ 287 #define _D0_UARTA1_BASECLK_DIVISION 0xD0U /* 4 ~ 255 */ //9600 288 #define _11_UARTA1_BASECLK_DIVISION 0x11U /* 4 ~ 255 */ //115200 289 enum TransferMode 290 { 291 SEND, RECEIVE 292 }; 293 294 void rt_hw_uart_init(void); 295 296 #endif 297