1 /********************************** (C) COPYRIGHT *******************************
2 * File Name : ch32f20x_dma.c
3 * Author : WCH
4 * Version : V1.0.0
5 * Date : 2021/08/08
6 * Description : This file provides all the DMA firmware functions.
7 *******************************************************************************/
8 #include "ch32f20x_dma.h"
9 #include "ch32f20x_rcc.h"
10
11 /* DMA1 Channelx interrupt pending bit masks */
12 #define DMA1_Channel1_IT_Mask ((uint32_t)(DMA_GIF1 | DMA_TCIF1 | DMA_HTIF1 | DMA_TEIF1))
13 #define DMA1_Channel2_IT_Mask ((uint32_t)(DMA_GIF2 | DMA_TCIF2 | DMA_HTIF2 | DMA_TEIF2))
14 #define DMA1_Channel3_IT_Mask ((uint32_t)(DMA_GIF3 | DMA_TCIF3 | DMA_HTIF3 | DMA_TEIF3))
15 #define DMA1_Channel4_IT_Mask ((uint32_t)(DMA_GIF4 | DMA_TCIF4 | DMA_HTIF4 | DMA_TEIF4))
16 #define DMA1_Channel5_IT_Mask ((uint32_t)(DMA_GIF5 | DMA_TCIF5 | DMA_HTIF5 | DMA_TEIF5))
17 #define DMA1_Channel6_IT_Mask ((uint32_t)(DMA_GIF6 | DMA_TCIF6 | DMA_HTIF6 | DMA_TEIF6))
18 #define DMA1_Channel7_IT_Mask ((uint32_t)(DMA_GIF7 | DMA_TCIF7 | DMA_HTIF7 | DMA_TEIF7))
19
20 /* DMA2 Channelx interrupt pending bit masks */
21 #define DMA2_Channel1_IT_Mask ((uint32_t)(DMA_GIF1 | DMA_TCIF1 | DMA_HTIF1 | DMA_TEIF1))
22 #define DMA2_Channel2_IT_Mask ((uint32_t)(DMA_GIF2 | DMA_TCIF2 | DMA_HTIF2 | DMA_TEIF2))
23 #define DMA2_Channel3_IT_Mask ((uint32_t)(DMA_GIF3 | DMA_TCIF3 | DMA_HTIF3 | DMA_TEIF3))
24 #define DMA2_Channel4_IT_Mask ((uint32_t)(DMA_GIF4 | DMA_TCIF4 | DMA_HTIF4 | DMA_TEIF4))
25 #define DMA2_Channel5_IT_Mask ((uint32_t)(DMA_GIF5 | DMA_TCIF5 | DMA_HTIF5 | DMA_TEIF5))
26 #define DMA2_Channel6_IT_Mask ((uint32_t)(DMA_GIF6 | DMA_TCIF6 | DMA_HTIF6 | DMA_TEIF6))
27 #define DMA2_Channel7_IT_Mask ((uint32_t)(DMA_GIF7 | DMA_TCIF7 | DMA_HTIF7 | DMA_TEIF7))
28 #define DMA2_Channel8_IT_Mask ((uint32_t)(DMA_GIF8 | DMA_TCIF8 | DMA_HTIF8 | DMA_TEIF8))
29 #define DMA2_Channel9_IT_Mask ((uint32_t)(DMA_GIF9 | DMA_TCIF9 | DMA_HTIF9 | DMA_TEIF9))
30 #define DMA2_Channel10_IT_Mask ((uint32_t)(DMA_GIF10 | DMA_TCIF10 | DMA_HTIF10 | DMA_TEIF10))
31 #define DMA2_Channel11_IT_Mask ((uint32_t)(DMA_GIF11 | DMA_TCIF11 | DMA_HTIF11 | DMA_TEIF11))
32
33 /* DMA2 FLAG mask */
34 #define FLAG_Mask ((uint32_t)0x10000000)
35 #define DMA2_EXTEN_FLAG_Mask ((uint32_t)0x20000000)
36
37 /* DMA registers Masks */
38 #define CFGR_CLEAR_Mask ((uint32_t)0xFFFF800F)
39
40
41 /********************************************************************************
42 * Function Name : DMA_DeInit
43 * Description : Deinitializes the DMAy Channelx registers to their default reset
44 * values.
45 * Input : DMAy_Channelx:here y can be 1 or 2 to select the DMA and x can be
46 * 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the
47 * DMA Channel.
48 * Return : None
49 *********************************************************************************/
DMA_DeInit(DMA_Channel_TypeDef * DMAy_Channelx)50 void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx)
51 {
52 DMAy_Channelx->CFGR &= (uint16_t)(~DMA_CFGR1_EN);
53 DMAy_Channelx->CFGR = 0;
54 DMAy_Channelx->CNTR = 0;
55 DMAy_Channelx->PADDR = 0;
56 DMAy_Channelx->MADDR = 0;
57 if (DMAy_Channelx == DMA1_Channel1)
58 {
59 DMA1->INTFCR |= DMA1_Channel1_IT_Mask;
60 }
61 else if (DMAy_Channelx == DMA1_Channel2)
62 {
63 DMA1->INTFCR |= DMA1_Channel2_IT_Mask;
64 }
65 else if (DMAy_Channelx == DMA1_Channel3)
66 {
67 DMA1->INTFCR |= DMA1_Channel3_IT_Mask;
68 }
69 else if (DMAy_Channelx == DMA1_Channel4)
70 {
71 DMA1->INTFCR |= DMA1_Channel4_IT_Mask;
72 }
73 else if (DMAy_Channelx == DMA1_Channel5)
74 {
75 DMA1->INTFCR |= DMA1_Channel5_IT_Mask;
76 }
77 else if (DMAy_Channelx == DMA1_Channel6)
78 {
79 DMA1->INTFCR |= DMA1_Channel6_IT_Mask;
80 }
81 else if (DMAy_Channelx == DMA1_Channel7)
82 {
83 DMA1->INTFCR |= DMA1_Channel7_IT_Mask;
84 }
85 else if (DMAy_Channelx == DMA2_Channel1)
86 {
87 DMA2->INTFCR |= DMA2_Channel1_IT_Mask;
88 }
89 else if (DMAy_Channelx == DMA2_Channel2)
90 {
91 DMA2->INTFCR |= DMA2_Channel2_IT_Mask;
92 }
93 else if (DMAy_Channelx == DMA2_Channel3)
94 {
95 DMA2->INTFCR |= DMA2_Channel3_IT_Mask;
96 }
97 else if (DMAy_Channelx == DMA2_Channel4)
98 {
99 DMA2->INTFCR |= DMA2_Channel4_IT_Mask;
100 }
101 else if (DMAy_Channelx == DMA2_Channel5)
102 {
103 DMA2->INTFCR |= DMA2_Channel5_IT_Mask;
104 }
105 else if (DMAy_Channelx == DMA2_Channel6)
106 {
107 DMA2->INTFCR |= DMA2_Channel6_IT_Mask;
108 }
109 else if (DMAy_Channelx == DMA2_Channel7)
110 {
111 DMA2->INTFCR |= DMA2_Channel7_IT_Mask;
112 }
113 else if (DMAy_Channelx == DMA2_Channel8)
114 {
115 DMA2_EXTEN->INTFCR |= DMA2_Channel8_IT_Mask;
116 }
117 else if (DMAy_Channelx == DMA2_Channel9)
118 {
119 DMA2_EXTEN->INTFCR |= DMA2_Channel9_IT_Mask;
120 }
121 else if (DMAy_Channelx == DMA2_Channel10)
122 {
123 DMA2_EXTEN->INTFCR |= DMA2_Channel10_IT_Mask;
124 }
125 else if (DMAy_Channelx == DMA2_Channel11)
126 {
127 DMA2_EXTEN->INTFCR |= DMA2_Channel11_IT_Mask;
128 }
129
130 }
131
132
133 /********************************************************************************
134 * Function Name : DMA_Init
135 * Description : Initializes the DMAy Channelx according to the specified
136 * parameters in the DMA_InitStruct.
137 * Input : DMAy_Channelx:here y can be 1 or 2 to select the DMA and x can be
138 * 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the
139 * DMA Channel.
140 * DMA_InitStruct:pointer to a DMA_InitTypeDef structure that
141 * contains the configuration information for the
142 * specified DMA Channel.
143 * Return : None
144 *********************************************************************************/
DMA_Init(DMA_Channel_TypeDef * DMAy_Channelx,DMA_InitTypeDef * DMA_InitStruct)145 void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct)
146 {
147 uint32_t tmpreg = 0;
148
149 tmpreg = DMAy_Channelx->CFGR;
150 tmpreg &= CFGR_CLEAR_Mask;
151 tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode |
152 DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc |
153 DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize |
154 DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M;
155
156 DMAy_Channelx->CFGR = tmpreg;
157 DMAy_Channelx->CNTR = DMA_InitStruct->DMA_BufferSize;
158 DMAy_Channelx->PADDR = DMA_InitStruct->DMA_PeripheralBaseAddr;
159 DMAy_Channelx->MADDR = DMA_InitStruct->DMA_MemoryBaseAddr;
160 }
161
162
163 /********************************************************************************
164 * Function Name : DMA_StructInit
165 * Description : Fills each DMA_InitStruct member with its default value.
166 * Input : DMA_InitStruct : pointer to a DMA_InitTypeDef structure which will
167 * 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the
168 * be initialized.
169 * Return : None
170 *********************************************************************************/
DMA_StructInit(DMA_InitTypeDef * DMA_InitStruct)171 void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct)
172 {
173 DMA_InitStruct->DMA_PeripheralBaseAddr = 0;
174 DMA_InitStruct->DMA_MemoryBaseAddr = 0;
175 DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC;
176 DMA_InitStruct->DMA_BufferSize = 0;
177 DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable;
178 DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable;
179 DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
180 DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
181 DMA_InitStruct->DMA_Mode = DMA_Mode_Normal;
182 DMA_InitStruct->DMA_Priority = DMA_Priority_Low;
183 DMA_InitStruct->DMA_M2M = DMA_M2M_Disable;
184 }
185
186
187 /********************************************************************************
188 * Function Name : DMA_Cmd
189 * Description : Enables or disables the specified DMAy Channelx.
190 * Input : DMAy_Channelx: where y can be 1 or 2 to select the DMA and x can
191 * be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select
192 * the DMA Channel.
193 * NewState : new state of the DMAy Channelx(ENABLE or DISABLE).
194 * Return : None
195 *********************************************************************************/
DMA_Cmd(DMA_Channel_TypeDef * DMAy_Channelx,FunctionalState NewState)196 void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState)
197 {
198 if (NewState != DISABLE)
199 {
200 DMAy_Channelx->CFGR |= DMA_CFGR1_EN;
201 }
202 else
203 {
204 DMAy_Channelx->CFGR &= (uint16_t)(~DMA_CFGR1_EN);
205 }
206 }
207
208 /********************************************************************************
209 * Function Name : DMA_ITConfig
210 * Description : Enables or disables the specified DMAy Channelx interrupts.
211 * Input : DMAy_Channelx: where y can be 1 or 2 to select the DMA and x can
212 * be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select
213 * the DMA Channel.
214 * DMA_IT : specifies the DMA interrupts sources to be enabled
215 * or disabled.
216 * DMA_IT_TC : Transfer complete interrupt mask
217 * DMA_IT_HT : Half transfer interrupt mask
218 * DMA_IT_TE : Transfer error interrupt mask
219 * NewState : new state of the DMAy Channelx(ENABLE or DISABLE).
220 * Return : None
221 *********************************************************************************/
DMA_ITConfig(DMA_Channel_TypeDef * DMAy_Channelx,uint32_t DMA_IT,FunctionalState NewState)222 void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState)
223 {
224 if (NewState != DISABLE)
225 {
226 DMAy_Channelx->CFGR |= DMA_IT;
227 }
228 else
229 {
230 DMAy_Channelx->CFGR &= ~DMA_IT;
231 }
232 }
233
234 /********************************************************************************
235 * Function Name : DMA_SetCurrDataCounter
236 * Description : Sets the number of data units in the current DMAy Channelx transfer.
237 * Input : DMAy_Channelx: where y can be 1 or 2 to select the DMA and x can
238 * be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select
239 * the DMA Channel.
240 * DataNumber : The number of data units in the current DMAy Channelx
241 * transfer.
242 * Return : None
243 *********************************************************************************/
DMA_SetCurrDataCounter(DMA_Channel_TypeDef * DMAy_Channelx,uint16_t DataNumber)244 void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber)
245 {
246 DMAy_Channelx->CNTR = DataNumber;
247 }
248
249 /********************************************************************************
250 * Function Name : DMA_GetCurrDataCounter
251 * Description : Returns the number of remaining data units in the current DMAy Channelx transfer.
252 * Input : DMAy_Channelx: where y can be 1 or 2 to select the DMA and x can
253 * be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select
254 * the DMA Channel.
255 * Return : DataNumber : The number of remaining data units in the current
256 * DMAy Channelx transfer.
257 *********************************************************************************/
DMA_GetCurrDataCounter(DMA_Channel_TypeDef * DMAy_Channelx)258 uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx)
259 {
260 return ((uint16_t)(DMAy_Channelx->CNTR));
261 }
262
263
264 /********************************************************************************
265 * Function Name : DMA_GetFlagStatus
266 * Description : Checks whether the specified DMAy Channelx flag is set or not.
267 * Input : DMAy_FLAG: specifies the flag to check.
268 * DMA1_FLAG_GL1: DMA1 Channel1 global flag.
269 * DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
270 * DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
271 * DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.
272 * DMA1_FLAG_GL2: DMA1 Channel2 global flag.
273 * DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
274 * DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
275 * DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.
276 * DMA1_FLAG_GL3: DMA1 Channel3 global flag.
277 * DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
278 * DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
279 * DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.
280 * DMA1_FLAG_GL4: DMA1 Channel4 global flag.
281 * DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
282 * DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
283 * DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.
284 * DMA1_FLAG_GL5: DMA1 Channel5 global flag.
285 * DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
286 * DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
287 * DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
288 * DMA1_FLAG_GL6: DMA1 Channel6 global flag.
289 * DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.
290 * DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.
291 * DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.
292 * DMA1_FLAG_GL7: DMA1 Channel7 global flag.
293 * DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.
294 * DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.
295 * DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.
296 * DMA2_FLAG_GL1: DMA2 Channel1 global flag.
297 * DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag.
298 * DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag.
299 * DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag.
300 * DMA2_FLAG_GL2: DMA2 Channel2 global flag.
301 * DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag.
302 * DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag.
303 * DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag.
304 * DMA2_FLAG_GL3: DMA2 Channel3 global flag.
305 * DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag.
306 * DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag.
307 * DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag.
308 * DMA2_FLAG_GL4: DMA2 Channel4 global flag.
309 * DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag.
310 * DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag.
311 * DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag.
312 * DMA2_FLAG_GL5: DMA2 Channel5 global flag.
313 * DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag.
314 * DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag.
315 * DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag.
316 * DMA2_FLAG_GL6: DMA2 Channel6 global flag.
317 * DMA2_FLAG_TC6: DMA2 Channel6 transfer complete flag.
318 * DMA2_FLAG_HT6: DMA2 Channel6 half transfer flag.
319 * DMA2_FLAG_TE6: DMA2 Channel6 transfer error flag.
320 * DMA2_FLAG_GL7: DMA2 Channel7 global flag.
321 * DMA2_FLAG_TC7: DMA2 Channel7 transfer complete flag.
322 * DMA2_FLAG_HT7: DMA2 Channel7 half transfer flag.
323 * DMA2_FLAG_TE7: DMA2 Channel7 transfer error flag.
324 * DMA2_FLAG_GL8: DMA2 Channel8 global flag.
325 * DMA2_FLAG_TC8: DMA2 Channel8 transfer complete flag.
326 * DMA2_FLAG_HT8: DMA2 Channel8 half transfer flag.
327 * DMA2_FLAG_TE8: DMA2 Channel8 transfer error flag.
328 * DMA2_FLAG_GL9: DMA2 Channel9 global flag.
329 * DMA2_FLAG_TC9: DMA2 Channel9 transfer complete flag.
330 * DMA2_FLAG_HT9: DMA2 Channel9 half transfer flag.
331 * DMA2_FLAG_TE9: DMA2 Channel9 transfer error flag.
332 * DMA2_FLAG_GL10: DMA2 Channel10 global flag.
333 * DMA2_FLAG_TC10: DMA2 Channel10 transfer complete flag.
334 * DMA2_FLAG_HT10: DMA2 Channel10 half transfer flag.
335 * DMA2_FLAG_TE10: DMA2 Channel10 transfer error flag.
336 * DMA2_FLAG_GL11: DMA2 Channel11 global flag.
337 * DMA2_FLAG_TC11: DMA2 Channel11 transfer complete flag.
338 * DMA2_FLAG_HT11: DMA2 Channel11 half transfer flag.
339 * DMA2_FLAG_TE11: DMA2 Channel11 transfer error flag.
340 * Return : The new state of DMAy_FLAG (SET or RESET).
341 *********************************************************************************/
DMA_GetFlagStatus(uint32_t DMAy_FLAG)342 FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG)
343 {
344 FlagStatus bitstatus = RESET;
345 uint32_t tmpreg = 0;
346
347 if ((DMAy_FLAG & FLAG_Mask) == FLAG_Mask)
348 {
349 tmpreg = DMA2->INTFR ;
350 }
351 else if((DMAy_FLAG & DMA2_EXTEN_FLAG_Mask) == DMA2_EXTEN_FLAG_Mask)
352 {
353 tmpreg = DMA2_EXTEN->INTFR;
354 }
355 else
356 {
357 tmpreg = DMA1->INTFR ;
358 }
359
360 if ((tmpreg & DMAy_FLAG) != (uint32_t)RESET)
361 {
362 bitstatus = SET;
363 }
364 else
365 {
366 bitstatus = RESET;
367 }
368
369 return bitstatus;
370 }
371
372
373 /********************************************************************************
374 * Function Name : DMA_ClearFlag
375 * Description : Clears the DMAy Channelx's pending flags.
376 * Input : DMAy_FLAG: specifies the flag to check.
377 * DMA1_FLAG_GL1: DMA1 Channel1 global flag.
378 * DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
379 * DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
380 * DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.
381 * DMA1_FLAG_GL2: DMA1 Channel2 global flag.
382 * DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
383 * DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
384 * DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.
385 * DMA1_FLAG_GL3: DMA1 Channel3 global flag.
386 * DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
387 * DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
388 * DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.
389 * DMA1_FLAG_GL4: DMA1 Channel4 global flag.
390 * DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
391 * DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
392 * DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.
393 * DMA1_FLAG_GL5: DMA1 Channel5 global flag.
394 * DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
395 * DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
396 * DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
397 * DMA1_FLAG_GL6: DMA1 Channel6 global flag.
398 * DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.
399 * DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.
400 * DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.
401 * DMA1_FLAG_GL7: DMA1 Channel7 global flag.
402 * DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.
403 * DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.
404 * DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.
405 * DMA2_FLAG_GL1: DMA2 Channel1 global flag.
406 * DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag.
407 * DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag.
408 * DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag.
409 * DMA2_FLAG_GL2: DMA2 Channel2 global flag.
410 * DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag.
411 * DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag.
412 * DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag.
413 * DMA2_FLAG_GL3: DMA2 Channel3 global flag.
414 * DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag.
415 * DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag.
416 * DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag.
417 * DMA2_FLAG_GL4: DMA2 Channel4 global flag.
418 * DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag.
419 * DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag.
420 * DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag.
421 * DMA2_FLAG_GL5: DMA2 Channel5 global flag.
422 * DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag.
423 * DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag.
424 * DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag.
425 * DMA2_FLAG_GL6: DMA2 Channel6 global flag.
426 * DMA2_FLAG_TC6: DMA2 Channel6 transfer complete flag.
427 * DMA2_FLAG_HT6: DMA2 Channel6 half transfer flag.
428 * DMA2_FLAG_TE6: DMA2 Channel6 transfer error flag.
429 * DMA2_FLAG_GL7: DMA2 Channel7 global flag.
430 * DMA2_FLAG_TC7: DMA2 Channel7 transfer complete flag.
431 * DMA2_FLAG_HT7: DMA2 Channel7 half transfer flag.
432 * DMA2_FLAG_TE7: DMA2 Channel7 transfer error flag.
433 * DMA2_FLAG_GL8: DMA2 Channel8 global flag.
434 * DMA2_FLAG_TC8: DMA2 Channel8 transfer complete flag.
435 * DMA2_FLAG_HT8: DMA2 Channel8 half transfer flag.
436 * DMA2_FLAG_TE8: DMA2 Channel8 transfer error flag.
437 * DMA2_FLAG_GL9: DMA2 Channel9 global flag.
438 * DMA2_FLAG_TC9: DMA2 Channel9 transfer complete flag.
439 * DMA2_FLAG_HT9: DMA2 Channel9 half transfer flag.
440 * DMA2_FLAG_TE9: DMA2 Channel9 transfer error flag.
441 * DMA2_FLAG_GL10: DMA2 Channel10 global flag.
442 * DMA2_FLAG_TC10: DMA2 Channel10 transfer complete flag.
443 * DMA2_FLAG_HT10: DMA2 Channel10 half transfer flag.
444 * DMA2_FLAG_TE10: DMA2 Channel10 transfer error flag.
445 * DMA2_FLAG_GL11: DMA2 Channel11 global flag.
446 * DMA2_FLAG_TC11: DMA2 Channel11 transfer complete flag.
447 * DMA2_FLAG_HT11: DMA2 Channel11 half transfer flag.
448 * DMA2_FLAG_TE11: DMA2 Channel11 transfer error flag.
449 * Return : None
450 *********************************************************************************/
DMA_ClearFlag(uint32_t DMAy_FLAG)451 void DMA_ClearFlag(uint32_t DMAy_FLAG)
452 {
453 if ((DMAy_FLAG & FLAG_Mask) == FLAG_Mask)
454 {
455 DMA2->INTFCR = DMAy_FLAG;
456 }
457 else if((DMAy_FLAG & DMA2_EXTEN_FLAG_Mask) == DMA2_EXTEN_FLAG_Mask)
458 {
459 DMA2_EXTEN->INTFCR = DMAy_FLAG;
460 }
461 else
462 {
463 DMA1->INTFCR = DMAy_FLAG;
464 }
465 }
466
467 /********************************************************************************
468 * Function Name : DMA_GetITStatus
469 * Description : Checks whether the specified DMAy Channelx interrupt has occurred
470 * or not.
471 * Input : DMAy_IT: specifies the DMAy interrupt source to check.
472 * DMA1_IT_GL1: DMA1 Channel1 global flag.
473 * DMA1_IT_TC1: DMA1 Channel1 transfer complete flag.
474 * DMA1_IT_HT1: DMA1 Channel1 half transfer flag.
475 * DMA1_IT_TE1: DMA1 Channel1 transfer error flag.
476 * DMA1_IT_GL2: DMA1 Channel2 global flag.
477 * DMA1_IT_TC2: DMA1 Channel2 transfer complete flag.
478 * DMA1_IT_HT2: DMA1 Channel2 half transfer flag.
479 * DMA1_IT_TE2: DMA1 Channel2 transfer error flag.
480 * DMA1_IT_GL3: DMA1 Channel3 global flag.
481 * DMA1_IT_TC3: DMA1 Channel3 transfer complete flag.
482 * DMA1_IT_HT3: DMA1 Channel3 half transfer flag.
483 * DMA1_IT_TE3: DMA1 Channel3 transfer error flag.
484 * DMA1_IT_GL4: DMA1 Channel4 global flag.
485 * DMA1_IT_TC4: DMA1 Channel4 transfer complete flag.
486 * DMA1_IT_HT4: DMA1 Channel4 half transfer flag.
487 * DMA1_IT_TE4: DMA1 Channel4 transfer error flag.
488 * DMA1_IT_GL5: DMA1 Channel5 global flag.
489 * DMA1_IT_TC5: DMA1 Channel5 transfer complete flag.
490 * DMA1_IT_HT5: DMA1 Channel5 half transfer flag.
491 * DMA1_IT_TE5: DMA1 Channel5 transfer error flag.
492 * DMA1_IT_GL6: DMA1 Channel6 global flag.
493 * DMA1_IT_TC6: DMA1 Channel6 transfer complete flag.
494 * DMA1_IT_HT6: DMA1 Channel6 half transfer flag.
495 * DMA1_IT_TE6: DMA1 Channel6 transfer error flag.
496 * DMA1_IT_GL7: DMA1 Channel7 global flag.
497 * DMA1_IT_TC7: DMA1 Channel7 transfer complete flag.
498 * DMA1_IT_HT7: DMA1 Channel7 half transfer flag.
499 * DMA1_IT_TE7: DMA1 Channel7 transfer error flag.
500 * DMA2_IT_GL1: DMA2 Channel1 global flag.
501 * DMA2_IT_TC1: DMA2 Channel1 transfer complete flag.
502 * DMA2_IT_HT1: DMA2 Channel1 half transfer flag.
503 * DMA2_IT_TE1: DMA2 Channel1 transfer error flag.
504 * DMA2_IT_GL2: DMA2 Channel2 global flag.
505 * DMA2_IT_TC2: DMA2 Channel2 transfer complete flag.
506 * DMA2_IT_HT2: DMA2 Channel2 half transfer flag.
507 * DMA2_IT_TE2: DMA2 Channel2 transfer error flag.
508 * DMA2_IT_GL3: DMA2 Channel3 global flag.
509 * DMA2_IT_TC3: DMA2 Channel3 transfer complete flag.
510 * DMA2_IT_HT3: DMA2 Channel3 half transfer flag.
511 * DMA2_IT_TE3: DMA2 Channel3 transfer error flag.
512 * DMA2_IT_GL4: DMA2 Channel4 global flag.
513 * DMA2_IT_TC4: DMA2 Channel4 transfer complete flag.
514 * DMA2_IT_HT4: DMA2 Channel4 half transfer flag.
515 * DMA2_IT_TE4: DMA2 Channel4 transfer error flag.
516 * DMA2_IT_GL5: DMA2 Channel5 global flag.
517 * DMA2_IT_TC5: DMA2 Channel5 transfer complete flag.
518 * DMA2_IT_HT5: DMA2 Channel5 half transfer flag.
519 * DMA2_IT_TE5: DMA2 Channel5 transfer error flag.
520 * DMA2_IT_GL6: DMA2 Channel6 global flag.
521 * DMA2_IT_TC6: DMA2 Channel6 transfer complete flag.
522 * DMA2_IT_HT6: DMA2 Channel6 half transfer flag.
523 * DMA2_IT_TE6: DMA2 Channel6 transfer error flag.
524 * DMA2_IT_GL7: DMA2 Channel7 global flag.
525 * DMA2_IT_TC7: DMA2 Channel7 transfer complete flag.
526 * DMA2_IT_HT7: DMA2 Channel7 half transfer flag.
527 * DMA2_IT_TE7: DMA2 Channel7 transfer error flag.
528 * DMA2_IT_GL8: DMA2 Channel8 global flag.
529 * DMA2_IT_TC8: DMA2 Channel8 transfer complete flag.
530 * DMA2_IT_HT8: DMA2 Channel8 half transfer flag.
531 * DMA2_IT_TE8: DMA2 Channel8 transfer error flag.
532 * DMA2_IT_GL9: DMA2 Channel9 global flag.
533 * DMA2_IT_TC9: DMA2 Channel9 transfer complete flag.
534 * DMA2_IT_HT9: DMA2 Channel9 half transfer flag.
535 * DMA2_IT_TE9: DMA2 Channel9 transfer error flag.
536 * DMA2_IT_GL10: DMA2 Channel10 global flag.
537 * DMA2_IT_TC10: DMA2 Channel10 transfer complete flag.
538 * DMA2_IT_HT10: DMA2 Channel10 half transfer flag.
539 * DMA2_IT_TE10: DMA2 Channel10 transfer error flag.
540 * DMA2_IT_GL11: DMA2 Channel11 global flag.
541 * DMA2_IT_TC11: DMA2 Channel11 transfer complete flag.
542 * DMA2_IT_HT11: DMA2 Channel11 half transfer flag.
543 * DMA2_IT_TE11: DMA2 Channel11 transfer error flag.
544 * Return : The new state of DMAy_IT (SET or RESET).
545 *********************************************************************************/
DMA_GetITStatus(uint32_t DMAy_IT)546 ITStatus DMA_GetITStatus(uint32_t DMAy_IT)
547 {
548 ITStatus bitstatus = RESET;
549 uint32_t tmpreg = 0;
550
551 if ((DMAy_IT & FLAG_Mask) == FLAG_Mask)
552 {
553 tmpreg = DMA2->INTFR;
554 }
555 else if((DMAy_IT & DMA2_EXTEN_FLAG_Mask) == DMA2_EXTEN_FLAG_Mask)
556 {
557 tmpreg = DMA2_EXTEN->INTFR;
558 }
559 else
560 {
561 tmpreg = DMA1->INTFR;
562 }
563
564 if ((tmpreg & DMAy_IT) != (uint32_t)RESET)
565 {
566 bitstatus = SET;
567 }
568 else
569 {
570 bitstatus = RESET;
571 }
572 return bitstatus;
573 }
574
575
576 /********************************************************************************
577 * Function Name : DMA_ClearITPendingBit
578 * Description : Clears the DMAy Channelx's interrupt pending bits.
579 * Input : DMAy_IT: specifies the DMAy interrupt source to clear.
580 * DMA1_IT_GL1: DMA1 Channel1 global flag.
581 * DMA1_IT_TC1: DMA1 Channel1 transfer complete flag.
582 * DMA1_IT_HT1: DMA1 Channel1 half transfer flag.
583 * DMA1_IT_TE1: DMA1 Channel1 transfer error flag.
584 * DMA1_IT_GL2: DMA1 Channel2 global flag.
585 * DMA1_IT_TC2: DMA1 Channel2 transfer complete flag.
586 * DMA1_IT_HT2: DMA1 Channel2 half transfer flag.
587 * DMA1_IT_TE2: DMA1 Channel2 transfer error flag.
588 * DMA1_IT_GL3: DMA1 Channel3 global flag.
589 * DMA1_IT_TC3: DMA1 Channel3 transfer complete flag.
590 * DMA1_IT_HT3: DMA1 Channel3 half transfer flag.
591 * DMA1_IT_TE3: DMA1 Channel3 transfer error flag.
592 * DMA1_IT_GL4: DMA1 Channel4 global flag.
593 * DMA1_IT_TC4: DMA1 Channel4 transfer complete flag.
594 * DMA1_IT_HT4: DMA1 Channel4 half transfer flag.
595 * DMA1_IT_TE4: DMA1 Channel4 transfer error flag.
596 * DMA1_IT_GL5: DMA1 Channel5 global flag.
597 * DMA1_IT_TC5: DMA1 Channel5 transfer complete flag.
598 * DMA1_IT_HT5: DMA1 Channel5 half transfer flag.
599 * DMA1_IT_TE5: DMA1 Channel5 transfer error flag.
600 * DMA1_IT_GL6: DMA1 Channel6 global flag.
601 * DMA1_IT_TC6: DMA1 Channel6 transfer complete flag.
602 * DMA1_IT_HT6: DMA1 Channel6 half transfer flag.
603 * DMA1_IT_TE6: DMA1 Channel6 transfer error flag.
604 * DMA1_IT_GL7: DMA1 Channel7 global flag.
605 * DMA1_IT_TC7: DMA1 Channel7 transfer complete flag.
606 * DMA1_IT_HT7: DMA1 Channel7 half transfer flag.
607 * DMA1_IT_TE7: DMA1 Channel7 transfer error flag.
608 * DMA2_IT_GL1: DMA2 Channel1 global flag.
609 * DMA2_IT_TC1: DMA2 Channel1 transfer complete flag.
610 * DMA2_IT_HT1: DMA2 Channel1 half transfer flag.
611 * DMA2_IT_TE1: DMA2 Channel1 transfer error flag.
612 * DMA2_IT_GL2: DMA2 Channel2 global flag.
613 * DMA2_IT_TC2: DMA2 Channel2 transfer complete flag.
614 * DMA2_IT_HT2: DMA2 Channel2 half transfer flag.
615 * DMA2_IT_TE2: DMA2 Channel2 transfer error flag.
616 * DMA2_IT_GL3: DMA2 Channel3 global flag.
617 * DMA2_IT_TC3: DMA2 Channel3 transfer complete flag.
618 * DMA2_IT_HT3: DMA2 Channel3 half transfer flag.
619 * DMA2_IT_TE3: DMA2 Channel3 transfer error flag.
620 * DMA2_IT_GL4: DMA2 Channel4 global flag.
621 * DMA2_IT_TC4: DMA2 Channel4 transfer complete flag.
622 * DMA2_IT_HT4: DMA2 Channel4 half transfer flag.
623 * DMA2_IT_TE4: DMA2 Channel4 transfer error flag.
624 * DMA2_IT_GL5: DMA2 Channel5 global flag.
625 * DMA2_IT_TC5: DMA2 Channel5 transfer complete flag.
626 * DMA2_IT_HT5: DMA2 Channel5 half transfer flag.
627 * DMA2_IT_TE5: DMA2 Channel5 transfer error flag.
628 * DMA2_IT_GL6: DMA2 Channel6 global flag.
629 * DMA2_IT_TC6: DMA2 Channel6 transfer complete flag.
630 * DMA2_IT_HT6: DMA2 Channel6 half transfer flag.
631 * DMA2_IT_TE6: DMA2 Channel6 transfer error flag.
632 * DMA2_IT_GL7: DMA2 Channel7 global flag.
633 * DMA2_IT_TC7: DMA2 Channel7 transfer complete flag.
634 * DMA2_IT_HT7: DMA2 Channel7 half transfer flag.
635 * DMA2_IT_TE7: DMA2 Channel7 transfer error flag.
636 * DMA2_IT_GL8: DMA2 Channel8 global flag.
637 * DMA2_IT_TC8: DMA2 Channel8 transfer complete flag.
638 * DMA2_IT_HT8: DMA2 Channel8 half transfer flag.
639 * DMA2_IT_TE8: DMA2 Channel8 transfer error flag.
640 * DMA2_IT_GL9: DMA2 Channel9 global flag.
641 * DMA2_IT_TC9: DMA2 Channel9 transfer complete flag.
642 * DMA2_IT_HT9: DMA2 Channel9 half transfer flag.
643 * DMA2_IT_TE9: DMA2 Channel9 transfer error flag.
644 * DMA2_IT_GL11: DMA2 Channel10 global flag.
645 * DMA2_IT_TC11: DMA2 Channel10 transfer complete flag.
646 * DMA2_IT_HT11: DMA2 Channel10 half transfer flag.
647 * DMA2_IT_TE11: DMA2 Channel10 transfer error flag.
648 * DMA2_IT_GL11: DMA2 Channel11 global flag.
649 * DMA2_IT_TC11: DMA2 Channel11 transfer complete flag.
650 * DMA2_IT_HT11: DMA2 Channel11 half transfer flag.
651 * DMA2_IT_TE11: DMA2 Channel11 transfer error flag.
652 * Return : None
653 *********************************************************************************/
DMA_ClearITPendingBit(uint32_t DMAy_IT)654 void DMA_ClearITPendingBit(uint32_t DMAy_IT)
655 {
656 if ((DMAy_IT & FLAG_Mask) == FLAG_Mask)
657 {
658 DMA2->INTFCR = DMAy_IT;
659 }
660 else if((DMAy_IT & DMA2_EXTEN_FLAG_Mask) == DMA2_EXTEN_FLAG_Mask)
661 {
662 DMA2_EXTEN->INTFCR = DMAy_IT;
663 }
664 else
665 {
666 DMA1->INTFCR = DMAy_IT;
667 }
668 }
669
670