1 /* 2 * Copyright (c) 2006-2021, RT-Thread Development Team 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 * 2021-08-10 charlown first version 9 */ 10 11 #ifndef __BOARD_H__ 12 #define __BOARD_H__ 13 14 #include "ch32f10x.h" 15 16 #ifdef __cplusplus 17 extern "C" { 18 #endif 19 20 21 #define CH32_FLASH_START_ADRESS ((uint32_t)0x08000000) 22 #define FLASH_PAGE_SIZE (64) 23 #define CH32_FLASH_SIZE (1024 * 1024) 24 #define CH32_FLASH_END_ADDRESS ((uint32_t)(CH32_FLASH_START_ADRESS + CH32_FLASH_SIZE)) 25 26 #define CH32_SRAM_SIZE 20 27 #define CH32_SRAM_END (0x20000000 + CH32_SRAM_SIZE * 1024) 28 29 #if defined(__ARMCC_VERSION) 30 extern int Image$$RW_IRAM1$$ZI$$Limit; 31 #define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit) 32 #elif __ICCARM__ 33 #pragma section="CSTACK" 34 #define HEAP_BEGIN (__segment_end("CSTACK")) 35 #else 36 extern int __bss_end; 37 #define HEAP_BEGIN ((void *)&__bss_end) 38 #endif 39 40 #define HEAP_END CH32_SRAM_END 41 42 #ifdef __cplusplus 43 } 44 #endif 45 46 47 rt_uint32_t ch32_get_sysclock_frequency(void); 48 49 #ifdef BSP_USING_UART 50 void ch32f1_usart_clock_and_io_init(USART_TypeDef* usartx); 51 #endif 52 53 #ifdef BSP_USING_SPI 54 void ch32f1_spi_clock_and_io_init(SPI_TypeDef* spix); 55 rt_uint32_t ch32f1_spi_clock_get(SPI_TypeDef* spix); 56 #endif 57 58 #ifdef BSP_USING_HWI2C 59 void ch32f1_i2c_clock_and_io_init(I2C_TypeDef* i2cx); 60 void ch32f1_i2c_config(I2C_TypeDef* i2cx); 61 #endif 62 63 #ifdef BSP_USING_TIM 64 void ch32f1_tim_clock_init(TIM_TypeDef *timx); 65 rt_uint32_t ch32f1_tim_clock_get(TIM_TypeDef *timx); 66 67 #ifdef BSP_USING_HWTIMER 68 struct rt_hwtimer_info* ch32f1_hwtimer_info_config_get(TIM_TypeDef *timx); 69 #endif 70 71 #ifdef BSP_USING_PWM 72 void ch32f1_pwm_io_init(TIM_TypeDef *timx, rt_uint8_t channel); 73 #endif 74 #endif 75 76 77 78 #endif /* __BOARD_H__ */ 79