1 /********************************** (C) COPYRIGHT *******************************
2 * File Name : system_ch32f20x.c
3 * Author : WCH
4 * Version : V1.0.0
5 * Date : 2021/08/08
6 * Description : CH32F20x Device Peripheral Access Layer System Source File.
7 * For HSE = 8Mhz
8 *********************************************************************************/
9 #include "ch32f20x.h"
10
11 /*
12 * Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after
13 * reset the HSI is used as SYSCLK source).
14 * If none of the define below is enabled, the HSI is used as System clock source.
15 */
16 // #define SYSCLK_FREQ_HSE HSE_VALUE
17 /* #define SYSCLK_FREQ_24MHz 24000000 */
18 //#define SYSCLK_FREQ_48MHz 48000000
19 /* #define SYSCLK_FREQ_56MHz 56000000 */
20 #define SYSCLK_FREQ_72MHz 72000000
21 //#define SYSCLK_FREQ_96MHz 96000000
22 //#define SYSCLK_FREQ_120MHz 120000000
23 //#define SYSCLK_FREQ_144MHz 144000000
24
25 /* Clock Definitions */
26 #ifdef SYSCLK_FREQ_HSE
27 uint32_t SystemCoreClock = SYSCLK_FREQ_HSE; /* System Clock Frequency (Core Clock) */
28 #elif defined SYSCLK_FREQ_24MHz
29 uint32_t SystemCoreClock = SYSCLK_FREQ_24MHz; /* System Clock Frequency (Core Clock) */
30 #elif defined SYSCLK_FREQ_48MHz
31 uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz; /* System Clock Frequency (Core Clock) */
32 #elif defined SYSCLK_FREQ_56MHz
33 uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz; /* System Clock Frequency (Core Clock) */
34 #elif defined SYSCLK_FREQ_72MHz
35 uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz; /* System Clock Frequency (Core Clock) */
36
37 #elif defined SYSCLK_FREQ_96MHz
38 uint32_t SystemCoreClock = SYSCLK_FREQ_96MHz; /* System Clock Frequency (Core Clock) */
39 #elif defined SYSCLK_FREQ_120MHz
40 uint32_t SystemCoreClock = SYSCLK_FREQ_120MHz; /* System Clock Frequency (Core Clock) */
41 #elif defined SYSCLK_FREQ_144MHz
42 uint32_t SystemCoreClock = SYSCLK_FREQ_144MHz; /* System Clock Frequency (Core Clock) */
43
44 #else /* HSI Selected as System Clock source */
45 uint32_t SystemCoreClock = HSI_VALUE; /* System Clock Frequency (Core Clock) */
46 #endif
47
48 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
49
50
51 /* system_private_function_proto_types */
52 static void SetSysClock(void);
53
54 #ifdef SYSCLK_FREQ_HSE
55 static void SetSysClockToHSE(void);
56 #elif defined SYSCLK_FREQ_24MHz
57 static void SetSysClockTo24(void);
58 #elif defined SYSCLK_FREQ_48MHz
59 static void SetSysClockTo48(void);
60 #elif defined SYSCLK_FREQ_56MHz
61 static void SetSysClockTo56(void);
62 #elif defined SYSCLK_FREQ_72MHz
63 static void SetSysClockTo72(void);
64
65 #elif defined SYSCLK_FREQ_96MHz
66 static void SetSysClockTo96(void);
67 #elif defined SYSCLK_FREQ_120MHz
68 static void SetSysClockTo120(void);
69 #elif defined SYSCLK_FREQ_144MHz
70 static void SetSysClockTo144(void);
71
72 #endif
73
74
75 /******************************************************************************************
76 * Function Name : SystemInit
77 * Description : Setup the microcontroller system Initialize the Embedded Flash Interface,
78 * the PLL and update the SystemCoreClock variable.
79 * Input : None
80 * Return : None
81 *******************************************************************************************/
SystemInit(void)82 void SystemInit (void)
83 {
84 RCC->CTLR |= (uint32_t)0x00000001;
85 RCC->CFGR0 &= (uint32_t)0xF8FF0000;
86 RCC->CTLR &= (uint32_t)0xFEF6FFFF;
87 RCC->CTLR &= (uint32_t)0xFFFBFFFF;
88 RCC->CFGR0 &= (uint32_t)0xFF80FFFF;
89 RCC->INTR = 0x009F0000;
90 SetSysClock();
91 }
92
93
94 /******************************************************************************************
95 * Function Name : SystemCoreClockUpdate
96 * Description : Update SystemCoreClock variable according to Clock Register Values.
97 * Input : None
98 * Return : None
99 *******************************************************************************************/
SystemCoreClockUpdate(void)100 void SystemCoreClockUpdate (void)
101 {
102 uint32_t tmp = 0, pllmull = 0, pllsource = 0, Pll_6_5 = 0;
103
104 tmp = RCC->CFGR0 & RCC_SWS;
105
106 switch (tmp)
107 {
108 case 0x00:
109 SystemCoreClock = HSI_VALUE;
110 break;
111 case 0x04:
112 SystemCoreClock = HSE_VALUE;
113 break;
114 case 0x08:
115 pllmull = RCC->CFGR0 & RCC_PLLMULL;
116 pllsource = RCC->CFGR0 & RCC_PLLSRC;
117 pllmull = ( pllmull >> 18) + 2;
118
119 if(((*(uint32_t*)0x1FFFF70C) & (1<<14)) != (1<<14)){ /* for other CH32F20x */
120 if(pllmull == 17) pllmull = 18;
121 }
122 else{ /* for CH32F207 */
123 if(pllmull == 2) pllmull = 18;
124 if(pllmull == 15){
125 pllmull = 13; /* *6.5 */
126 Pll_6_5 = 1;
127 }
128 if(pllmull == 16) pllmull = 15;
129 if(pllmull == 17) pllmull = 16;
130 }
131
132 if (pllsource == 0x00)
133 {
134 SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
135 }
136 else
137 {
138 if ((RCC->CFGR0 & RCC_PLLXTPRE) != (uint32_t)RESET)
139 {
140 SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
141 }
142 else
143 {
144 SystemCoreClock = HSE_VALUE * pllmull;
145 }
146 }
147
148 if(Pll_6_5 == 1) SystemCoreClock = (SystemCoreClock / 2);
149
150 break;
151 default:
152 SystemCoreClock = HSI_VALUE;
153 break;
154 }
155
156 tmp = AHBPrescTable[((RCC->CFGR0 & RCC_HPRE) >> 4)];
157 SystemCoreClock >>= tmp;
158 }
159
160
161 /******************************************************************************************
162 * Function Name : SetSysClock
163 * Description : Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
164 * Input : None
165 * Return : None
166 *******************************************************************************************/
SetSysClock(void)167 static void SetSysClock(void)
168 {
169 #ifdef SYSCLK_FREQ_HSE
170 SetSysClockToHSE();
171 #elif defined SYSCLK_FREQ_24MHz
172 SetSysClockTo24();
173 #elif defined SYSCLK_FREQ_48MHz
174 SetSysClockTo48();
175 #elif defined SYSCLK_FREQ_56MHz
176 SetSysClockTo56();
177 #elif defined SYSCLK_FREQ_72MHz
178 SetSysClockTo72();
179
180 #elif defined SYSCLK_FREQ_96MHz
181 SetSysClockTo96();
182 #elif defined SYSCLK_FREQ_120MHz
183 SetSysClockTo120();
184 #elif defined SYSCLK_FREQ_144MHz
185 SetSysClockTo144();
186
187
188 #endif
189
190 /* If none of the define above is enabled, the HSI is used as System clock
191 * source (default after reset)
192 */
193 }
194
195
196 #ifdef SYSCLK_FREQ_HSE
197
198 /******************************************************************************************
199 * Function Name : SetSysClockToHSE
200 * Description : Sets HSE as System clock source and configure HCLK, PCLK2 and PCLK1 prescalers.
201 * Input : None
202 * Return : None
203 *******************************************************************************************/
SetSysClockToHSE(void)204 static void SetSysClockToHSE(void)
205 {
206 __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
207
208
209 RCC->CTLR |= ((uint32_t)RCC_HSEON);
210
211 /* Wait till HSE is ready and if Time out is reached exit */
212 do
213 {
214 HSEStatus = RCC->CTLR & RCC_HSERDY;
215 StartUpCounter++;
216 } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
217
218 if ((RCC->CTLR & RCC_HSERDY) != RESET)
219 {
220 HSEStatus = (uint32_t)0x01;
221 }
222 else
223 {
224 HSEStatus = (uint32_t)0x00;
225 }
226
227 if (HSEStatus == (uint32_t)0x01)
228 {
229 FLASH->ACTLR |= FLASH_ACTLR_PRFTBE;
230 /* Flash 0 wait state */
231 FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY);
232 FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_0;
233
234 /* HCLK = SYSCLK */
235 RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
236 /* PCLK2 = HCLK */
237 RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
238 /* PCLK1 = HCLK */
239 RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV1;
240
241 /* Select HSE as system clock source */
242 RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
243 RCC->CFGR0 |= (uint32_t)RCC_SW_HSE;
244
245 /* Wait till HSE is used as system clock source */
246 while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x04)
247 {
248 }
249 }
250 else
251 {
252 /* If HSE fails to start-up, the application will have wrong clock
253 * configuration. User can add here some code to deal with this error
254 */
255 }
256 }
257
258 #elif defined SYSCLK_FREQ_24MHz
259
260 /******************************************************************************************
261 * Function Name : SetSysClockTo24
262 * Description : Sets System clock frequency to 24MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
263 * Input : None
264 * Return : None
265 *******************************************************************************************/
SetSysClockTo24(void)266 static void SetSysClockTo24(void)
267 {
268 __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
269
270 RCC->CTLR |= ((uint32_t)RCC_HSEON);
271
272 /* Wait till HSE is ready and if Time out is reached exit */
273 do
274 {
275 HSEStatus = RCC->CTLR & RCC_HSERDY;
276 StartUpCounter++;
277 } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
278
279 if ((RCC->CTLR & RCC_HSERDY) != RESET)
280 {
281 HSEStatus = (uint32_t)0x01;
282 }
283 else
284 {
285 HSEStatus = (uint32_t)0x00;
286 }
287 if (HSEStatus == (uint32_t)0x01)
288 {
289 /* Enable Prefetch Buffer */
290 FLASH->ACTLR |= FLASH_ACTLR_PRFTBE;
291
292 /* Flash 0 wait state */
293 FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY);
294 FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_0;
295
296 /* HCLK = SYSCLK */
297 RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
298 /* PCLK2 = HCLK */
299 RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
300 /* PCLK1 = HCLK */
301 RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV1;
302
303 RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
304
305 if(((*(uint32_t*)0x1FFFF70C) & (1<<14)) != (1<<14)){
306 RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL3);
307 }
308 else{
309 RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL3_EXTEN);
310 }
311 /* Enable PLL */
312 RCC->CTLR |= RCC_PLLON;
313
314 /* Wait till PLL is ready */
315 while((RCC->CTLR & RCC_PLLRDY) == 0)
316 {
317 }
318 /* Select PLL as system clock source */
319 RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
320 RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
321 /* Wait till PLL is used as system clock source */
322 while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
323 {
324 }
325 }
326 else
327 {
328 /* If HSE fails to start-up, the application will have wrong clock
329 * configuration. User can add here some code to deal with this error
330 */
331 }
332 }
333
334 #elif defined SYSCLK_FREQ_48MHz
335
336 /******************************************************************************************
337 * Function Name : SetSysClockTo48
338 * Description : Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
339 * Input : None
340 * Return : None
341 *******************************************************************************************/
SetSysClockTo48(void)342 static void SetSysClockTo48(void)
343 {
344 __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
345
346
347 RCC->CTLR |= ((uint32_t)RCC_HSEON);
348 /* Wait till HSE is ready and if Time out is reached exit */
349 do
350 {
351 HSEStatus = RCC->CTLR & RCC_HSERDY;
352 StartUpCounter++;
353 } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
354
355 if ((RCC->CTLR & RCC_HSERDY) != RESET)
356 {
357 HSEStatus = (uint32_t)0x01;
358 }
359 else
360 {
361 HSEStatus = (uint32_t)0x00;
362 }
363
364 if (HSEStatus == (uint32_t)0x01)
365 {
366 /* Enable Prefetch Buffer */
367 FLASH->ACTLR |= FLASH_ACTLR_PRFTBE;
368
369 /* Flash 1 wait state */
370 FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY);
371 FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_1;
372
373 /* HCLK = SYSCLK */
374 RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
375 /* PCLK2 = HCLK */
376 RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
377 /* PCLK1 = HCLK */
378 RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
379
380 /* PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
381 RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
382
383 if(((*(uint32_t*)0x1FFFF70C) & (1<<14)) != (1<<14)){
384 RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL6);
385 }
386 else{
387 RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL6_EXTEN);
388 }
389
390 /* Enable PLL */
391 RCC->CTLR |= RCC_PLLON;
392 /* Wait till PLL is ready */
393 while((RCC->CTLR & RCC_PLLRDY) == 0)
394 {
395 }
396 /* Select PLL as system clock source */
397 RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
398 RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
399 /* Wait till PLL is used as system clock source */
400 while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
401 {
402 }
403 }
404 else
405 {
406 /*
407 * If HSE fails to start-up, the application will have wrong clock
408 * configuration. User can add here some code to deal with this error
409 */
410 }
411 }
412
413 #elif defined SYSCLK_FREQ_56MHz
414
415 /******************************************************************************************
416 * Function Name : SetSysClockTo56
417 * Description : Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
418 * Input : None
419 * Return : None
420 *******************************************************************************************/
SetSysClockTo56(void)421 static void SetSysClockTo56(void)
422 {
423 __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
424
425 RCC->CTLR |= ((uint32_t)RCC_HSEON);
426
427 /* Wait till HSE is ready and if Time out is reached exit */
428 do
429 {
430 HSEStatus = RCC->CTLR & RCC_HSERDY;
431 StartUpCounter++;
432 } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
433
434 if ((RCC->CTLR & RCC_HSERDY) != RESET)
435 {
436 HSEStatus = (uint32_t)0x01;
437 }
438 else
439 {
440 HSEStatus = (uint32_t)0x00;
441 }
442
443 if (HSEStatus == (uint32_t)0x01)
444 {
445 /* Enable Prefetch Buffer */
446 FLASH->ACTLR |= FLASH_ACTLR_PRFTBE;
447
448 /* Flash 2 wait state */
449 FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY);
450 FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_2;
451
452 /* HCLK = SYSCLK */
453 RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
454 /* PCLK2 = HCLK */
455 RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
456 /* PCLK1 = HCLK */
457 RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
458
459 /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
460 RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
461
462 if(((*(uint32_t*)0x1FFFF70C) & (1<<14)) != (1<<14)){
463 RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL7);
464 }
465 else{
466 RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL7_EXTEN);
467 }
468
469 /* Enable PLL */
470 RCC->CTLR |= RCC_PLLON;
471 /* Wait till PLL is ready */
472 while((RCC->CTLR & RCC_PLLRDY) == 0)
473 {
474 }
475
476 /* Select PLL as system clock source */
477 RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
478 RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
479 /* Wait till PLL is used as system clock source */
480 while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
481 {
482 }
483 }
484 else
485 {
486 /*
487 * If HSE fails to start-up, the application will have wrong clock
488 * configuration. User can add here some code to deal with this error
489 */
490 }
491 }
492
493 #elif defined SYSCLK_FREQ_72MHz
494
495 /******************************************************************************************
496 * Function Name : SetSysClockTo72
497 * Description : Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
498 * Input : None
499 * Return : None
500 *******************************************************************************************/
SetSysClockTo72(void)501 static void SetSysClockTo72(void)
502 {
503 __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
504
505 RCC->CTLR |= ((uint32_t)RCC_HSEON);
506
507 /* Wait till HSE is ready and if Time out is reached exit */
508 do
509 {
510 HSEStatus = RCC->CTLR & RCC_HSERDY;
511 StartUpCounter++;
512 } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
513
514 if ((RCC->CTLR & RCC_HSERDY) != RESET)
515 {
516 HSEStatus = (uint32_t)0x01;
517 }
518 else
519 {
520 HSEStatus = (uint32_t)0x00;
521 }
522
523 if (HSEStatus == (uint32_t)0x01)
524 {
525 /* Enable Prefetch Buffer */
526 FLASH->ACTLR |= FLASH_ACTLR_PRFTBE;
527
528 /* Flash 2 wait state */
529 FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY);
530 FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_2;
531
532 /* HCLK = SYSCLK */
533 RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
534 /* PCLK2 = HCLK */
535 RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
536 /* PCLK1 = HCLK */
537 RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
538
539 /* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
540 RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE |
541 RCC_PLLMULL));
542
543 if(((*(uint32_t*)0x1FFFF70C) & (1<<14)) != (1<<14)){
544 RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL9);
545 }
546 else{
547 RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL9_EXTEN);
548 }
549
550 /* Enable PLL */
551 RCC->CTLR |= RCC_PLLON;
552 /* Wait till PLL is ready */
553 while((RCC->CTLR & RCC_PLLRDY) == 0)
554 {
555 }
556 /* Select PLL as system clock source */
557 RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
558 RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
559 /* Wait till PLL is used as system clock source */
560 while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
561 {
562 }
563 }
564 else
565 {
566 /*
567 * If HSE fails to start-up, the application will have wrong clock
568 * configuration. User can add here some code to deal with this error
569 */
570 }
571 }
572
573
574 #elif defined SYSCLK_FREQ_96MHz
575
576 /******************************************************************************************
577 * Function Name : SetSysClockTo96
578 * Description : Sets System clock frequency to 96MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
579 * Input : None
580 * Return : None
581 *******************************************************************************************/
SetSysClockTo96(void)582 static void SetSysClockTo96(void)
583 {
584 __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
585
586 RCC->CTLR |= ((uint32_t)RCC_HSEON);
587
588 /* Wait till HSE is ready and if Time out is reached exit */
589 do
590 {
591 HSEStatus = RCC->CTLR & RCC_HSERDY;
592 StartUpCounter++;
593 } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
594
595 if ((RCC->CTLR & RCC_HSERDY) != RESET)
596 {
597 HSEStatus = (uint32_t)0x01;
598 }
599 else
600 {
601 HSEStatus = (uint32_t)0x00;
602 }
603
604 if (HSEStatus == (uint32_t)0x01)
605 {
606 /* Enable Prefetch Buffer */
607 FLASH->ACTLR |= FLASH_ACTLR_PRFTBE;
608
609 /* Flash 2 wait state */
610 FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY);
611 FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_2;
612
613 /* HCLK = SYSCLK */
614 RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
615 /* PCLK2 = HCLK */
616 RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
617 /* PCLK1 = HCLK */
618 RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
619
620 /* PLL configuration: PLLCLK = HSE * 12 = 96 MHz */
621 RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE |
622 RCC_PLLMULL));
623
624 if(((*(uint32_t*)0x1FFFF70C) & (1<<14)) != (1<<14)){
625 RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL12);
626 }
627 else{
628 RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL12_EXTEN);
629 }
630
631 /* Enable PLL */
632 RCC->CTLR |= RCC_PLLON;
633 /* Wait till PLL is ready */
634 while((RCC->CTLR & RCC_PLLRDY) == 0)
635 {
636 }
637 /* Select PLL as system clock source */
638 RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
639 RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
640 /* Wait till PLL is used as system clock source */
641 while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
642 {
643 }
644 }
645 else
646 {
647 /*
648 * If HSE fails to start-up, the application will have wrong clock
649 * configuration. User can add here some code to deal with this error
650 */
651 }
652 }
653
654
655 #elif defined SYSCLK_FREQ_120MHz
656
657 /******************************************************************************************
658 * Function Name : SetSysClockTo120
659 * Description : Sets System clock frequency to 120MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
660 * Input : None
661 * Return : None
662 *******************************************************************************************/
SetSysClockTo120(void)663 static void SetSysClockTo120(void)
664 {
665 __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
666
667 RCC->CTLR |= ((uint32_t)RCC_HSEON);
668
669 /* Wait till HSE is ready and if Time out is reached exit */
670 do
671 {
672 HSEStatus = RCC->CTLR & RCC_HSERDY;
673 StartUpCounter++;
674 } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
675
676 if ((RCC->CTLR & RCC_HSERDY) != RESET)
677 {
678 HSEStatus = (uint32_t)0x01;
679 }
680 else
681 {
682 HSEStatus = (uint32_t)0x00;
683 }
684
685 if (HSEStatus == (uint32_t)0x01)
686 {
687 /* Enable Prefetch Buffer */
688 FLASH->ACTLR |= FLASH_ACTLR_PRFTBE;
689
690 /* Flash 2 wait state */
691 FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY);
692 FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_2;
693
694 /* HCLK = SYSCLK */
695 RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
696 /* PCLK2 = HCLK */
697 RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
698 /* PCLK1 = HCLK */
699 RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
700
701 /* PLL configuration: PLLCLK = HSE * 15 = 120 MHz */
702 RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE |
703 RCC_PLLMULL));
704
705 if(((*(uint32_t*)0x1FFFF70C) & (1<<14)) != (1<<14)){
706 RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL15);
707 }
708 else{
709 RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL15_EXTEN);
710 }
711
712 /* Enable PLL */
713 RCC->CTLR |= RCC_PLLON;
714 /* Wait till PLL is ready */
715 while((RCC->CTLR & RCC_PLLRDY) == 0)
716 {
717 }
718 /* Select PLL as system clock source */
719 RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
720 RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
721 /* Wait till PLL is used as system clock source */
722 while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
723 {
724 }
725 }
726 else
727 {
728 /*
729 * If HSE fails to start-up, the application will have wrong clock
730 * configuration. User can add here some code to deal with this error
731 */
732 }
733 }
734
735
736 #elif defined SYSCLK_FREQ_144MHz
737
738 /******************************************************************************************
739 * Function Name : SetSysClockTo144
740 * Description : Sets System clock frequency to 144MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
741 * Input : None
742 * Return : None
743 *******************************************************************************************/
SetSysClockTo144(void)744 static void SetSysClockTo144(void)
745 {
746 __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
747
748 RCC->CTLR |= ((uint32_t)RCC_HSEON);
749
750 /* Wait till HSE is ready and if Time out is reached exit */
751 do
752 {
753 HSEStatus = RCC->CTLR & RCC_HSERDY;
754 StartUpCounter++;
755 } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
756
757 if ((RCC->CTLR & RCC_HSERDY) != RESET)
758 {
759 HSEStatus = (uint32_t)0x01;
760 }
761 else
762 {
763 HSEStatus = (uint32_t)0x00;
764 }
765
766 if (HSEStatus == (uint32_t)0x01)
767 {
768 /* Enable Prefetch Buffer */
769 FLASH->ACTLR |= FLASH_ACTLR_PRFTBE;
770
771 /* Flash 2 wait state */
772 FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY);
773 FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_2;
774
775 /* HCLK = SYSCLK */
776 RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
777 /* PCLK2 = HCLK */
778 RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
779 /* PCLK1 = HCLK */
780 RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
781
782 /* PLL configuration: PLLCLK = HSE * 18 = 144 MHz */
783 RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE |
784 RCC_PLLMULL));
785
786 if(((*(uint32_t*)0x1FFFF70C) & (1<<14)) != (1<<14)){
787 RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL18);
788 }
789 else{
790 RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL18_EXTEN);
791 }
792
793 /* Enable PLL */
794 RCC->CTLR |= RCC_PLLON;
795 /* Wait till PLL is ready */
796 while((RCC->CTLR & RCC_PLLRDY) == 0)
797 {
798 }
799 /* Select PLL as system clock source */
800 RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
801 RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
802 /* Wait till PLL is used as system clock source */
803 while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
804 {
805 }
806 }
807 else
808 {
809 /*
810 * If HSE fails to start-up, the application will have wrong clock
811 * configuration. User can add here some code to deal with this error
812 */
813 }
814 }
815
816
817
818
819 #endif
820