1 /********************************** (C) COPYRIGHT  *******************************
2  * File Name          : ch32v10x_rcc.h
3  * Author             : WCH
4  * Version            : V1.0.0
5  * Date               : 2020/04/30
6  * Description        : This file provides all the RCC firmware functions.
7  * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
8  * SPDX-License-Identifier: Apache-2.0
9  *******************************************************************************/
10 #ifndef __CH32V10x_RCC_H
11 #define __CH32V10x_RCC_H
12 
13 #ifdef __cplusplus
14 extern "C" {
15 #endif
16 
17 #include "ch32v10x.h"
18 
19 /* RCC_Exported_Types */
20 typedef struct
21 {
22     uint32_t SYSCLK_Frequency; /* returns SYSCLK clock frequency expressed in Hz */
23     uint32_t HCLK_Frequency;   /* returns HCLK clock frequency expressed in Hz */
24     uint32_t PCLK1_Frequency;  /* returns PCLK1 clock frequency expressed in Hz */
25     uint32_t PCLK2_Frequency;  /* returns PCLK2 clock frequency expressed in Hz */
26     uint32_t ADCCLK_Frequency; /* returns ADCCLK clock frequency expressed in Hz */
27 } RCC_ClocksTypeDef;
28 
29 /* HSE_configuration */
30 #define RCC_HSE_OFF                      ((uint32_t)0x00000000)
31 #define RCC_HSE_ON                       ((uint32_t)0x00010000)
32 #define RCC_HSE_Bypass                   ((uint32_t)0x00040000)
33 
34 /* PLL_entry_clock_source */
35 #define RCC_PLLSource_HSI_Div2           ((uint32_t)0x00000000)
36 #define RCC_PLLSource_HSE_Div1           ((uint32_t)0x00010000)
37 #define RCC_PLLSource_HSE_Div2           ((uint32_t)0x00030000)
38 
39 /* PLL_multiplication_factor */
40 #define RCC_PLLMul_2                     ((uint32_t)0x00000000)
41 #define RCC_PLLMul_3                     ((uint32_t)0x00040000)
42 #define RCC_PLLMul_4                     ((uint32_t)0x00080000)
43 #define RCC_PLLMul_5                     ((uint32_t)0x000C0000)
44 #define RCC_PLLMul_6                     ((uint32_t)0x00100000)
45 #define RCC_PLLMul_7                     ((uint32_t)0x00140000)
46 #define RCC_PLLMul_8                     ((uint32_t)0x00180000)
47 #define RCC_PLLMul_9                     ((uint32_t)0x001C0000)
48 #define RCC_PLLMul_10                    ((uint32_t)0x00200000)
49 #define RCC_PLLMul_11                    ((uint32_t)0x00240000)
50 #define RCC_PLLMul_12                    ((uint32_t)0x00280000)
51 #define RCC_PLLMul_13                    ((uint32_t)0x002C0000)
52 #define RCC_PLLMul_14                    ((uint32_t)0x00300000)
53 #define RCC_PLLMul_15                    ((uint32_t)0x00340000)
54 #define RCC_PLLMul_16                    ((uint32_t)0x00380000)
55 
56 /* System_clock_source */
57 #define RCC_SYSCLKSource_HSI             ((uint32_t)0x00000000)
58 #define RCC_SYSCLKSource_HSE             ((uint32_t)0x00000001)
59 #define RCC_SYSCLKSource_PLLCLK          ((uint32_t)0x00000002)
60 
61 /* AHB_clock_source */
62 #define RCC_SYSCLK_Div1                  ((uint32_t)0x00000000)
63 #define RCC_SYSCLK_Div2                  ((uint32_t)0x00000080)
64 #define RCC_SYSCLK_Div4                  ((uint32_t)0x00000090)
65 #define RCC_SYSCLK_Div8                  ((uint32_t)0x000000A0)
66 #define RCC_SYSCLK_Div16                 ((uint32_t)0x000000B0)
67 #define RCC_SYSCLK_Div64                 ((uint32_t)0x000000C0)
68 #define RCC_SYSCLK_Div128                ((uint32_t)0x000000D0)
69 #define RCC_SYSCLK_Div256                ((uint32_t)0x000000E0)
70 #define RCC_SYSCLK_Div512                ((uint32_t)0x000000F0)
71 
72 /* APB1_APB2_clock_source */
73 #define RCC_HCLK_Div1                    ((uint32_t)0x00000000)
74 #define RCC_HCLK_Div2                    ((uint32_t)0x00000400)
75 #define RCC_HCLK_Div4                    ((uint32_t)0x00000500)
76 #define RCC_HCLK_Div8                    ((uint32_t)0x00000600)
77 #define RCC_HCLK_Div16                   ((uint32_t)0x00000700)
78 
79 /* RCC_Interrupt_source */
80 #define RCC_IT_LSIRDY                    ((uint8_t)0x01)
81 #define RCC_IT_LSERDY                    ((uint8_t)0x02)
82 #define RCC_IT_HSIRDY                    ((uint8_t)0x04)
83 #define RCC_IT_HSERDY                    ((uint8_t)0x08)
84 #define RCC_IT_PLLRDY                    ((uint8_t)0x10)
85 #define RCC_IT_CSS                       ((uint8_t)0x80)
86 
87 /* USB_Device_clock_source */
88 #define RCC_USBCLKSource_PLLCLK_1Div5    ((uint8_t)0x00)
89 #define RCC_USBCLKSource_PLLCLK_Div1     ((uint8_t)0x01)
90 
91 /* ADC_clock_source */
92 #define RCC_PCLK2_Div2                   ((uint32_t)0x00000000)
93 #define RCC_PCLK2_Div4                   ((uint32_t)0x00004000)
94 #define RCC_PCLK2_Div6                   ((uint32_t)0x00008000)
95 #define RCC_PCLK2_Div8                   ((uint32_t)0x0000C000)
96 
97 /* LSE_configuration */
98 #define RCC_LSE_OFF                      ((uint8_t)0x00)
99 #define RCC_LSE_ON                       ((uint8_t)0x01)
100 #define RCC_LSE_Bypass                   ((uint8_t)0x04)
101 
102 /* RTC_clock_source */
103 #define RCC_RTCCLKSource_LSE             ((uint32_t)0x00000100)
104 #define RCC_RTCCLKSource_LSI             ((uint32_t)0x00000200)
105 #define RCC_RTCCLKSource_HSE_Div128      ((uint32_t)0x00000300)
106 
107 /* AHB_peripheral */
108 #define RCC_AHBPeriph_DMA1               ((uint32_t)0x00000001)
109 #define RCC_AHBPeriph_DMA2               ((uint32_t)0x00000002)
110 #define RCC_AHBPeriph_SRAM               ((uint32_t)0x00000004)
111 #define RCC_AHBPeriph_FLITF              ((uint32_t)0x00000010)
112 #define RCC_AHBPeriph_CRC                ((uint32_t)0x00000040)
113 #define RCC_AHBPeriph_FSMC               ((uint32_t)0x00000100)
114 #define RCC_AHBPeriph_SDIO               ((uint32_t)0x00000400)
115 #define RCC_AHBPeriph_USBHD              ((uint32_t)0x00001000)
116 
117 /* APB2_peripheral */
118 #define RCC_APB2Periph_AFIO              ((uint32_t)0x00000001)
119 #define RCC_APB2Periph_GPIOA             ((uint32_t)0x00000004)
120 #define RCC_APB2Periph_GPIOB             ((uint32_t)0x00000008)
121 #define RCC_APB2Periph_GPIOC             ((uint32_t)0x00000010)
122 #define RCC_APB2Periph_GPIOD             ((uint32_t)0x00000020)
123 #define RCC_APB2Periph_GPIOE             ((uint32_t)0x00000040)
124 #define RCC_APB2Periph_GPIOF             ((uint32_t)0x00000080)
125 #define RCC_APB2Periph_GPIOG             ((uint32_t)0x00000100)
126 #define RCC_APB2Periph_ADC1              ((uint32_t)0x00000200)
127 #define RCC_APB2Periph_ADC2              ((uint32_t)0x00000400)
128 #define RCC_APB2Periph_TIM1              ((uint32_t)0x00000800)
129 #define RCC_APB2Periph_SPI1              ((uint32_t)0x00001000)
130 #define RCC_APB2Periph_TIM8              ((uint32_t)0x00002000)
131 #define RCC_APB2Periph_USART1            ((uint32_t)0x00004000)
132 #define RCC_APB2Periph_ADC3              ((uint32_t)0x00008000)
133 #define RCC_APB2Periph_TIM15             ((uint32_t)0x00010000)
134 #define RCC_APB2Periph_TIM16             ((uint32_t)0x00020000)
135 #define RCC_APB2Periph_TIM17             ((uint32_t)0x00040000)
136 #define RCC_APB2Periph_TIM9              ((uint32_t)0x00080000)
137 #define RCC_APB2Periph_TIM10             ((uint32_t)0x00100000)
138 #define RCC_APB2Periph_TIM11             ((uint32_t)0x00200000)
139 
140 /* APB1_peripheral */
141 #define RCC_APB1Periph_TIM2              ((uint32_t)0x00000001)
142 #define RCC_APB1Periph_TIM3              ((uint32_t)0x00000002)
143 #define RCC_APB1Periph_TIM4              ((uint32_t)0x00000004)
144 #define RCC_APB1Periph_TIM5              ((uint32_t)0x00000008)
145 #define RCC_APB1Periph_TIM6              ((uint32_t)0x00000010)
146 #define RCC_APB1Periph_TIM7              ((uint32_t)0x00000020)
147 #define RCC_APB1Periph_TIM12             ((uint32_t)0x00000040)
148 #define RCC_APB1Periph_TIM13             ((uint32_t)0x00000080)
149 #define RCC_APB1Periph_TIM14             ((uint32_t)0x00000100)
150 #define RCC_APB1Periph_WWDG              ((uint32_t)0x00000800)
151 #define RCC_APB1Periph_SPI2              ((uint32_t)0x00004000)
152 #define RCC_APB1Periph_SPI3              ((uint32_t)0x00008000)
153 #define RCC_APB1Periph_USART2            ((uint32_t)0x00020000)
154 #define RCC_APB1Periph_USART3            ((uint32_t)0x00040000)
155 #define RCC_APB1Periph_UART4             ((uint32_t)0x00080000)
156 #define RCC_APB1Periph_UART5             ((uint32_t)0x00100000)
157 #define RCC_APB1Periph_I2C1              ((uint32_t)0x00200000)
158 #define RCC_APB1Periph_I2C2              ((uint32_t)0x00400000)
159 #define RCC_APB1Periph_USB               ((uint32_t)0x00800000)
160 #define RCC_APB1Periph_CAN1              ((uint32_t)0x02000000)
161 #define RCC_APB1Periph_CAN2              ((uint32_t)0x04000000)
162 #define RCC_APB1Periph_BKP               ((uint32_t)0x08000000)
163 #define RCC_APB1Periph_PWR               ((uint32_t)0x10000000)
164 #define RCC_APB1Periph_DAC               ((uint32_t)0x20000000)
165 #define RCC_APB1Periph_CEC               ((uint32_t)0x40000000)
166 
167 /* Clock_source_to_output_on_MCO_pin */
168 #define RCC_MCO_NoClock                  ((uint8_t)0x00)
169 #define RCC_MCO_SYSCLK                   ((uint8_t)0x04)
170 #define RCC_MCO_HSI                      ((uint8_t)0x05)
171 #define RCC_MCO_HSE                      ((uint8_t)0x06)
172 #define RCC_MCO_PLLCLK_Div2              ((uint8_t)0x07)
173 
174 /* RCC_Flag */
175 #define RCC_FLAG_HSIRDY                  ((uint8_t)0x21)
176 #define RCC_FLAG_HSERDY                  ((uint8_t)0x31)
177 #define RCC_FLAG_PLLRDY                  ((uint8_t)0x39)
178 #define RCC_FLAG_LSERDY                  ((uint8_t)0x41)
179 #define RCC_FLAG_LSIRDY                  ((uint8_t)0x61)
180 #define RCC_FLAG_PINRST                  ((uint8_t)0x7A)
181 #define RCC_FLAG_PORRST                  ((uint8_t)0x7B)
182 #define RCC_FLAG_SFTRST                  ((uint8_t)0x7C)
183 #define RCC_FLAG_IWDGRST                 ((uint8_t)0x7D)
184 #define RCC_FLAG_WWDGRST                 ((uint8_t)0x7E)
185 #define RCC_FLAG_LPWRRST                 ((uint8_t)0x7F)
186 
187 /* SysTick_clock_source */
188 #define SysTick_CLKSource_HCLK_Div8      ((uint32_t)0xFFFFFFFB)
189 #define SysTick_CLKSource_HCLK           ((uint32_t)0x00000004)
190 
191 void        RCC_DeInit(void);
192 void        RCC_HSEConfig(uint32_t RCC_HSE);
193 ErrorStatus RCC_WaitForHSEStartUp(void);
194 void        RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);
195 void        RCC_HSICmd(FunctionalState NewState);
196 void        RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul);
197 void        RCC_PLLCmd(FunctionalState NewState);
198 void        RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);
199 uint8_t     RCC_GetSYSCLKSource(void);
200 void        RCC_HCLKConfig(uint32_t RCC_SYSCLK);
201 void        RCC_PCLK1Config(uint32_t RCC_HCLK);
202 void        RCC_PCLK2Config(uint32_t RCC_HCLK);
203 void        RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);
204 void        RCC_USBCLKConfig(uint32_t RCC_USBCLKSource);
205 void        RCC_ADCCLKConfig(uint32_t RCC_PCLK2);
206 void        RCC_LSEConfig(uint8_t RCC_LSE);
207 void        RCC_LSICmd(FunctionalState NewState);
208 void        RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);
209 void        RCC_RTCCLKCmd(FunctionalState NewState);
210 void        RCC_GetClocksFreq(RCC_ClocksTypeDef *RCC_Clocks);
211 void        RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
212 void        RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
213 void        RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
214 void        RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
215 void        RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
216 void        RCC_BackupResetCmd(FunctionalState NewState);
217 void        RCC_ClockSecuritySystemCmd(FunctionalState NewState);
218 void        RCC_MCOConfig(uint8_t RCC_MCO);
219 FlagStatus  RCC_GetFlagStatus(uint8_t RCC_FLAG);
220 void        RCC_ClearFlag(void);
221 ITStatus    RCC_GetITStatus(uint8_t RCC_IT);
222 void        RCC_ClearITPendingBit(uint8_t RCC_IT);
223 
224 #ifdef __cplusplus
225 }
226 #endif
227 
228 #endif /* __CH32V10x_RCC_H */
229