1 /********************************** (C) COPYRIGHT ******************************* 2 * File Name : ch32v10x_tim.h 3 * Author : WCH 4 * Version : V1.0.0 5 * Date : 2020/04/30 6 * Description : This file contains all the functions prototypes for the 7 * TIM firmware library. 8 * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 9 * SPDX-License-Identifier: Apache-2.0 10 *******************************************************************************/ 11 #ifndef __CH32V10x_TIM_H 12 #define __CH32V10x_TIM_H 13 14 #ifdef __cplusplus 15 extern "C" { 16 #endif 17 18 #include "ch32v10x.h" 19 20 /* TIM Time Base Init structure definition */ 21 typedef struct 22 { 23 uint16_t TIM_Prescaler; /* Specifies the prescaler value used to divide the TIM clock. 24 This parameter can be a number between 0x0000 and 0xFFFF */ 25 26 uint16_t TIM_CounterMode; /* Specifies the counter mode. 27 This parameter can be a value of @ref TIM_Counter_Mode */ 28 29 uint16_t TIM_Period; /* Specifies the period value to be loaded into the active 30 Auto-Reload Register at the next update event. 31 This parameter must be a number between 0x0000 and 0xFFFF. */ 32 33 uint16_t TIM_ClockDivision; /* Specifies the clock division. 34 This parameter can be a value of @ref TIM_Clock_Division_CKD */ 35 36 uint8_t TIM_RepetitionCounter; /* Specifies the repetition counter value. Each time the RCR downcounter 37 reaches zero, an update event is generated and counting restarts 38 from the RCR value (N). 39 This means in PWM mode that (N+1) corresponds to: 40 - the number of PWM periods in edge-aligned mode 41 - the number of half PWM period in center-aligned mode 42 This parameter must be a number between 0x00 and 0xFF. 43 @note This parameter is valid only for TIM1 and TIM8. */ 44 } TIM_TimeBaseInitTypeDef; 45 46 /* TIM Output Compare Init structure definition */ 47 typedef struct 48 { 49 uint16_t TIM_OCMode; /* Specifies the TIM mode. 50 This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ 51 52 uint16_t TIM_OutputState; /* Specifies the TIM Output Compare state. 53 This parameter can be a value of @ref TIM_Output_Compare_state */ 54 55 uint16_t TIM_OutputNState; /* Specifies the TIM complementary Output Compare state. 56 This parameter can be a value of @ref TIM_Output_Compare_N_state 57 @note This parameter is valid only for TIM1 and TIM8. */ 58 59 uint16_t TIM_Pulse; /* Specifies the pulse value to be loaded into the Capture Compare Register. 60 This parameter can be a number between 0x0000 and 0xFFFF */ 61 62 uint16_t TIM_OCPolarity; /* Specifies the output polarity. 63 This parameter can be a value of @ref TIM_Output_Compare_Polarity */ 64 65 uint16_t TIM_OCNPolarity; /* Specifies the complementary output polarity. 66 This parameter can be a value of @ref TIM_Output_Compare_N_Polarity 67 @note This parameter is valid only for TIM1 and TIM8. */ 68 69 uint16_t TIM_OCIdleState; /* Specifies the TIM Output Compare pin state during Idle state. 70 This parameter can be a value of @ref TIM_Output_Compare_Idle_State 71 @note This parameter is valid only for TIM1 and TIM8. */ 72 73 uint16_t TIM_OCNIdleState; /* Specifies the TIM Output Compare pin state during Idle state. 74 This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State 75 @note This parameter is valid only for TIM1 and TIM8. */ 76 } TIM_OCInitTypeDef; 77 78 /* TIM Input Capture Init structure definition */ 79 typedef struct 80 { 81 uint16_t TIM_Channel; /* Specifies the TIM channel. 82 This parameter can be a value of @ref TIM_Channel */ 83 84 uint16_t TIM_ICPolarity; /* Specifies the active edge of the input signal. 85 This parameter can be a value of @ref TIM_Input_Capture_Polarity */ 86 87 uint16_t TIM_ICSelection; /* Specifies the input. 88 This parameter can be a value of @ref TIM_Input_Capture_Selection */ 89 90 uint16_t TIM_ICPrescaler; /* Specifies the Input Capture Prescaler. 91 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ 92 93 uint16_t TIM_ICFilter; /* Specifies the input capture filter. 94 This parameter can be a number between 0x0 and 0xF */ 95 } TIM_ICInitTypeDef; 96 97 /* BDTR structure definition */ 98 typedef struct 99 { 100 uint16_t TIM_OSSRState; /* Specifies the Off-State selection used in Run mode. 101 This parameter can be a value of @ref OSSR_Off_State_Selection_for_Run_mode_state */ 102 103 uint16_t TIM_OSSIState; /* Specifies the Off-State used in Idle state. 104 This parameter can be a value of @ref OSSI_Off_State_Selection_for_Idle_mode_state */ 105 106 uint16_t TIM_LOCKLevel; /* Specifies the LOCK level parameters. 107 This parameter can be a value of @ref Lock_level */ 108 109 uint16_t TIM_DeadTime; /* Specifies the delay time between the switching-off and the 110 switching-on of the outputs. 111 This parameter can be a number between 0x00 and 0xFF */ 112 113 uint16_t TIM_Break; /* Specifies whether the TIM Break input is enabled or not. 114 This parameter can be a value of @ref Break_Input_enable_disable */ 115 116 uint16_t TIM_BreakPolarity; /* Specifies the TIM Break Input pin polarity. 117 This parameter can be a value of @ref Break_Polarity */ 118 119 uint16_t TIM_AutomaticOutput; /* Specifies whether the TIM Automatic Output feature is enabled or not. 120 This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ 121 } TIM_BDTRInitTypeDef; 122 123 /* TIM_Output_Compare_and_PWM_modes */ 124 #define TIM_OCMode_Timing ((uint16_t)0x0000) 125 #define TIM_OCMode_Active ((uint16_t)0x0010) 126 #define TIM_OCMode_Inactive ((uint16_t)0x0020) 127 #define TIM_OCMode_Toggle ((uint16_t)0x0030) 128 #define TIM_OCMode_PWM1 ((uint16_t)0x0060) 129 #define TIM_OCMode_PWM2 ((uint16_t)0x0070) 130 131 /* TIM_One_Pulse_Mode */ 132 #define TIM_OPMode_Single ((uint16_t)0x0008) 133 #define TIM_OPMode_Repetitive ((uint16_t)0x0000) 134 135 /* TIM_Channel */ 136 #define TIM_Channel_1 ((uint16_t)0x0000) 137 #define TIM_Channel_2 ((uint16_t)0x0004) 138 #define TIM_Channel_3 ((uint16_t)0x0008) 139 #define TIM_Channel_4 ((uint16_t)0x000C) 140 141 /* TIM_Clock_Division_CKD */ 142 #define TIM_CKD_DIV1 ((uint16_t)0x0000) 143 #define TIM_CKD_DIV2 ((uint16_t)0x0100) 144 #define TIM_CKD_DIV4 ((uint16_t)0x0200) 145 146 /* TIM_Counter_Mode */ 147 #define TIM_CounterMode_Up ((uint16_t)0x0000) 148 #define TIM_CounterMode_Down ((uint16_t)0x0010) 149 #define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020) 150 #define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040) 151 #define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060) 152 153 /* TIM_Output_Compare_Polarity */ 154 #define TIM_OCPolarity_High ((uint16_t)0x0000) 155 #define TIM_OCPolarity_Low ((uint16_t)0x0002) 156 157 /* TIM_Output_Compare_N_Polarity */ 158 #define TIM_OCNPolarity_High ((uint16_t)0x0000) 159 #define TIM_OCNPolarity_Low ((uint16_t)0x0008) 160 161 /* TIM_Output_Compare_state */ 162 #define TIM_OutputState_Disable ((uint16_t)0x0000) 163 #define TIM_OutputState_Enable ((uint16_t)0x0001) 164 165 /* TIM_Output_Compare_N_state */ 166 #define TIM_OutputNState_Disable ((uint16_t)0x0000) 167 #define TIM_OutputNState_Enable ((uint16_t)0x0004) 168 169 /* TIM_Capture_Compare_state */ 170 #define TIM_CCx_Enable ((uint16_t)0x0001) 171 #define TIM_CCx_Disable ((uint16_t)0x0000) 172 173 /* TIM_Capture_Compare_N_state */ 174 #define TIM_CCxN_Enable ((uint16_t)0x0004) 175 #define TIM_CCxN_Disable ((uint16_t)0x0000) 176 177 /* Break_Input_enable_disable */ 178 #define TIM_Break_Enable ((uint16_t)0x1000) 179 #define TIM_Break_Disable ((uint16_t)0x0000) 180 181 /* Break_Polarity */ 182 #define TIM_BreakPolarity_Low ((uint16_t)0x0000) 183 #define TIM_BreakPolarity_High ((uint16_t)0x2000) 184 185 /* TIM_AOE_Bit_Set_Reset */ 186 #define TIM_AutomaticOutput_Enable ((uint16_t)0x4000) 187 #define TIM_AutomaticOutput_Disable ((uint16_t)0x0000) 188 189 /* Lock_level */ 190 #define TIM_LOCKLevel_OFF ((uint16_t)0x0000) 191 #define TIM_LOCKLevel_1 ((uint16_t)0x0100) 192 #define TIM_LOCKLevel_2 ((uint16_t)0x0200) 193 #define TIM_LOCKLevel_3 ((uint16_t)0x0300) 194 195 /* OSSI_Off_State_Selection_for_Idle_mode_state */ 196 #define TIM_OSSIState_Enable ((uint16_t)0x0400) 197 #define TIM_OSSIState_Disable ((uint16_t)0x0000) 198 199 /* OSSR_Off_State_Selection_for_Run_mode_state */ 200 #define TIM_OSSRState_Enable ((uint16_t)0x0800) 201 #define TIM_OSSRState_Disable ((uint16_t)0x0000) 202 203 /* TIM_Output_Compare_Idle_State */ 204 #define TIM_OCIdleState_Set ((uint16_t)0x0100) 205 #define TIM_OCIdleState_Reset ((uint16_t)0x0000) 206 207 /* TIM_Output_Compare_N_Idle_State */ 208 #define TIM_OCNIdleState_Set ((uint16_t)0x0200) 209 #define TIM_OCNIdleState_Reset ((uint16_t)0x0000) 210 211 /* TIM_Input_Capture_Polarity */ 212 #define TIM_ICPolarity_Rising ((uint16_t)0x0000) 213 #define TIM_ICPolarity_Falling ((uint16_t)0x0002) 214 #define TIM_ICPolarity_BothEdge ((uint16_t)0x000A) 215 216 /* TIM_Input_Capture_Selection */ 217 #define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /* TIM Input 1, 2, 3 or 4 is selected to be \ 218 connected to IC1, IC2, IC3 or IC4, respectively */ 219 #define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /* TIM Input 1, 2, 3 or 4 is selected to be \ 220 connected to IC2, IC1, IC4 or IC3, respectively. */ 221 #define TIM_ICSelection_TRC ((uint16_t)0x0003) /* TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */ 222 223 /* TIM_Input_Capture_Prescaler */ 224 #define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /* Capture performed each time an edge is detected on the capture input. */ 225 #define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /* Capture performed once every 2 events. */ 226 #define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /* Capture performed once every 4 events. */ 227 #define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /* Capture performed once every 8 events. */ 228 229 /* TIM_interrupt_sources */ 230 #define TIM_IT_Update ((uint16_t)0x0001) 231 #define TIM_IT_CC1 ((uint16_t)0x0002) 232 #define TIM_IT_CC2 ((uint16_t)0x0004) 233 #define TIM_IT_CC3 ((uint16_t)0x0008) 234 #define TIM_IT_CC4 ((uint16_t)0x0010) 235 #define TIM_IT_COM ((uint16_t)0x0020) 236 #define TIM_IT_Trigger ((uint16_t)0x0040) 237 #define TIM_IT_Break ((uint16_t)0x0080) 238 239 /* TIM_DMA_Base_address */ 240 #define TIM_DMABase_CR1 ((uint16_t)0x0000) 241 #define TIM_DMABase_CR2 ((uint16_t)0x0001) 242 #define TIM_DMABase_SMCR ((uint16_t)0x0002) 243 #define TIM_DMABase_DIER ((uint16_t)0x0003) 244 #define TIM_DMABase_SR ((uint16_t)0x0004) 245 #define TIM_DMABase_EGR ((uint16_t)0x0005) 246 #define TIM_DMABase_CCMR1 ((uint16_t)0x0006) 247 #define TIM_DMABase_CCMR2 ((uint16_t)0x0007) 248 #define TIM_DMABase_CCER ((uint16_t)0x0008) 249 #define TIM_DMABase_CNT ((uint16_t)0x0009) 250 #define TIM_DMABase_PSC ((uint16_t)0x000A) 251 #define TIM_DMABase_ARR ((uint16_t)0x000B) 252 #define TIM_DMABase_RCR ((uint16_t)0x000C) 253 #define TIM_DMABase_CCR1 ((uint16_t)0x000D) 254 #define TIM_DMABase_CCR2 ((uint16_t)0x000E) 255 #define TIM_DMABase_CCR3 ((uint16_t)0x000F) 256 #define TIM_DMABase_CCR4 ((uint16_t)0x0010) 257 #define TIM_DMABase_BDTR ((uint16_t)0x0011) 258 #define TIM_DMABase_DCR ((uint16_t)0x0012) 259 260 /* TIM_DMA_Burst_Length */ 261 #define TIM_DMABurstLength_1Transfer ((uint16_t)0x0000) 262 #define TIM_DMABurstLength_2Transfers ((uint16_t)0x0100) 263 #define TIM_DMABurstLength_3Transfers ((uint16_t)0x0200) 264 #define TIM_DMABurstLength_4Transfers ((uint16_t)0x0300) 265 #define TIM_DMABurstLength_5Transfers ((uint16_t)0x0400) 266 #define TIM_DMABurstLength_6Transfers ((uint16_t)0x0500) 267 #define TIM_DMABurstLength_7Transfers ((uint16_t)0x0600) 268 #define TIM_DMABurstLength_8Transfers ((uint16_t)0x0700) 269 #define TIM_DMABurstLength_9Transfers ((uint16_t)0x0800) 270 #define TIM_DMABurstLength_10Transfers ((uint16_t)0x0900) 271 #define TIM_DMABurstLength_11Transfers ((uint16_t)0x0A00) 272 #define TIM_DMABurstLength_12Transfers ((uint16_t)0x0B00) 273 #define TIM_DMABurstLength_13Transfers ((uint16_t)0x0C00) 274 #define TIM_DMABurstLength_14Transfers ((uint16_t)0x0D00) 275 #define TIM_DMABurstLength_15Transfers ((uint16_t)0x0E00) 276 #define TIM_DMABurstLength_16Transfers ((uint16_t)0x0F00) 277 #define TIM_DMABurstLength_17Transfers ((uint16_t)0x1000) 278 #define TIM_DMABurstLength_18Transfers ((uint16_t)0x1100) 279 280 /* TIM_DMA_sources */ 281 #define TIM_DMA_Update ((uint16_t)0x0100) 282 #define TIM_DMA_CC1 ((uint16_t)0x0200) 283 #define TIM_DMA_CC2 ((uint16_t)0x0400) 284 #define TIM_DMA_CC3 ((uint16_t)0x0800) 285 #define TIM_DMA_CC4 ((uint16_t)0x1000) 286 #define TIM_DMA_COM ((uint16_t)0x2000) 287 #define TIM_DMA_Trigger ((uint16_t)0x4000) 288 289 /* TIM_External_Trigger_Prescaler */ 290 #define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000) 291 #define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000) 292 #define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000) 293 #define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000) 294 295 /* TIM_Internal_Trigger_Selection */ 296 #define TIM_TS_ITR0 ((uint16_t)0x0000) 297 #define TIM_TS_ITR1 ((uint16_t)0x0010) 298 #define TIM_TS_ITR2 ((uint16_t)0x0020) 299 #define TIM_TS_ITR3 ((uint16_t)0x0030) 300 #define TIM_TS_TI1F_ED ((uint16_t)0x0040) 301 #define TIM_TS_TI1FP1 ((uint16_t)0x0050) 302 #define TIM_TS_TI2FP2 ((uint16_t)0x0060) 303 #define TIM_TS_ETRF ((uint16_t)0x0070) 304 305 /* TIM_TIx_External_Clock_Source */ 306 #define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050) 307 #define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060) 308 #define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040) 309 310 /* TIM_External_Trigger_Polarity */ 311 #define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000) 312 #define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000) 313 314 /* TIM_Prescaler_Reload_Mode */ 315 #define TIM_PSCReloadMode_Update ((uint16_t)0x0000) 316 #define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001) 317 318 /* TIM_Forced_Action */ 319 #define TIM_ForcedAction_Active ((uint16_t)0x0050) 320 #define TIM_ForcedAction_InActive ((uint16_t)0x0040) 321 322 /* TIM_Encoder_Mode */ 323 #define TIM_EncoderMode_TI1 ((uint16_t)0x0001) 324 #define TIM_EncoderMode_TI2 ((uint16_t)0x0002) 325 #define TIM_EncoderMode_TI12 ((uint16_t)0x0003) 326 327 /* TIM_Event_Source */ 328 #define TIM_EventSource_Update ((uint16_t)0x0001) 329 #define TIM_EventSource_CC1 ((uint16_t)0x0002) 330 #define TIM_EventSource_CC2 ((uint16_t)0x0004) 331 #define TIM_EventSource_CC3 ((uint16_t)0x0008) 332 #define TIM_EventSource_CC4 ((uint16_t)0x0010) 333 #define TIM_EventSource_COM ((uint16_t)0x0020) 334 #define TIM_EventSource_Trigger ((uint16_t)0x0040) 335 #define TIM_EventSource_Break ((uint16_t)0x0080) 336 337 /* TIM_Update_Source */ 338 #define TIM_UpdateSource_Global ((uint16_t)0x0000) /* Source of update is the counter overflow/underflow \ 339 or the setting of UG bit, or an update generation \ 340 through the slave mode controller. */ 341 #define TIM_UpdateSource_Regular ((uint16_t)0x0001) /* Source of update is counter overflow/underflow. */ 342 343 /* TIM_Output_Compare_Preload_State */ 344 #define TIM_OCPreload_Enable ((uint16_t)0x0008) 345 #define TIM_OCPreload_Disable ((uint16_t)0x0000) 346 347 /* TIM_Output_Compare_Fast_State */ 348 #define TIM_OCFast_Enable ((uint16_t)0x0004) 349 #define TIM_OCFast_Disable ((uint16_t)0x0000) 350 351 /* TIM_Output_Compare_Clear_State */ 352 #define TIM_OCClear_Enable ((uint16_t)0x0080) 353 #define TIM_OCClear_Disable ((uint16_t)0x0000) 354 355 /* TIM_Trigger_Output_Source */ 356 #define TIM_TRGOSource_Reset ((uint16_t)0x0000) 357 #define TIM_TRGOSource_Enable ((uint16_t)0x0010) 358 #define TIM_TRGOSource_Update ((uint16_t)0x0020) 359 #define TIM_TRGOSource_OC1 ((uint16_t)0x0030) 360 #define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040) 361 #define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050) 362 #define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060) 363 #define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070) 364 365 /* TIM_Slave_Mode */ 366 #define TIM_SlaveMode_Reset ((uint16_t)0x0004) 367 #define TIM_SlaveMode_Gated ((uint16_t)0x0005) 368 #define TIM_SlaveMode_Trigger ((uint16_t)0x0006) 369 #define TIM_SlaveMode_External1 ((uint16_t)0x0007) 370 371 /* TIM_Master_Slave_Mode */ 372 #define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080) 373 #define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000) 374 375 /* TIM_Flags */ 376 #define TIM_FLAG_Update ((uint16_t)0x0001) 377 #define TIM_FLAG_CC1 ((uint16_t)0x0002) 378 #define TIM_FLAG_CC2 ((uint16_t)0x0004) 379 #define TIM_FLAG_CC3 ((uint16_t)0x0008) 380 #define TIM_FLAG_CC4 ((uint16_t)0x0010) 381 #define TIM_FLAG_COM ((uint16_t)0x0020) 382 #define TIM_FLAG_Trigger ((uint16_t)0x0040) 383 #define TIM_FLAG_Break ((uint16_t)0x0080) 384 #define TIM_FLAG_CC1OF ((uint16_t)0x0200) 385 #define TIM_FLAG_CC2OF ((uint16_t)0x0400) 386 #define TIM_FLAG_CC3OF ((uint16_t)0x0800) 387 #define TIM_FLAG_CC4OF ((uint16_t)0x1000) 388 389 /* TIM_Legacy */ 390 #define TIM_DMABurstLength_1Byte TIM_DMABurstLength_1Transfer 391 #define TIM_DMABurstLength_2Bytes TIM_DMABurstLength_2Transfers 392 #define TIM_DMABurstLength_3Bytes TIM_DMABurstLength_3Transfers 393 #define TIM_DMABurstLength_4Bytes TIM_DMABurstLength_4Transfers 394 #define TIM_DMABurstLength_5Bytes TIM_DMABurstLength_5Transfers 395 #define TIM_DMABurstLength_6Bytes TIM_DMABurstLength_6Transfers 396 #define TIM_DMABurstLength_7Bytes TIM_DMABurstLength_7Transfers 397 #define TIM_DMABurstLength_8Bytes TIM_DMABurstLength_8Transfers 398 #define TIM_DMABurstLength_9Bytes TIM_DMABurstLength_9Transfers 399 #define TIM_DMABurstLength_10Bytes TIM_DMABurstLength_10Transfers 400 #define TIM_DMABurstLength_11Bytes TIM_DMABurstLength_11Transfers 401 #define TIM_DMABurstLength_12Bytes TIM_DMABurstLength_12Transfers 402 #define TIM_DMABurstLength_13Bytes TIM_DMABurstLength_13Transfers 403 #define TIM_DMABurstLength_14Bytes TIM_DMABurstLength_14Transfers 404 #define TIM_DMABurstLength_15Bytes TIM_DMABurstLength_15Transfers 405 #define TIM_DMABurstLength_16Bytes TIM_DMABurstLength_16Transfers 406 #define TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers 407 #define TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers 408 409 void TIM_DeInit(TIM_TypeDef *TIMx); 410 void TIM_TimeBaseInit(TIM_TypeDef *TIMx, TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct); 411 void TIM_OC1Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct); 412 void TIM_OC2Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct); 413 void TIM_OC3Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct); 414 void TIM_OC4Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct); 415 void TIM_ICInit(TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct); 416 void TIM_PWMIConfig(TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct); 417 void TIM_BDTRConfig(TIM_TypeDef *TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct); 418 void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct); 419 void TIM_OCStructInit(TIM_OCInitTypeDef *TIM_OCInitStruct); 420 void TIM_ICStructInit(TIM_ICInitTypeDef *TIM_ICInitStruct); 421 void TIM_BDTRStructInit(TIM_BDTRInitTypeDef *TIM_BDTRInitStruct); 422 void TIM_Cmd(TIM_TypeDef *TIMx, FunctionalState NewState); 423 void TIM_CtrlPWMOutputs(TIM_TypeDef *TIMx, FunctionalState NewState); 424 void TIM_ITConfig(TIM_TypeDef *TIMx, uint16_t TIM_IT, FunctionalState NewState); 425 void TIM_GenerateEvent(TIM_TypeDef *TIMx, uint16_t TIM_EventSource); 426 void TIM_DMAConfig(TIM_TypeDef *TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength); 427 void TIM_DMACmd(TIM_TypeDef *TIMx, uint16_t TIM_DMASource, FunctionalState NewState); 428 void TIM_InternalClockConfig(TIM_TypeDef *TIMx); 429 void TIM_ITRxExternalClockConfig(TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource); 430 void TIM_TIxExternalClockConfig(TIM_TypeDef *TIMx, uint16_t TIM_TIxExternalCLKSource, 431 uint16_t TIM_ICPolarity, uint16_t ICFilter); 432 void TIM_ETRClockMode1Config(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, 433 uint16_t ExtTRGFilter); 434 void TIM_ETRClockMode2Config(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, 435 uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter); 436 void TIM_ETRConfig(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, 437 uint16_t ExtTRGFilter); 438 void TIM_PrescalerConfig(TIM_TypeDef *TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode); 439 void TIM_CounterModeConfig(TIM_TypeDef *TIMx, uint16_t TIM_CounterMode); 440 void TIM_SelectInputTrigger(TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource); 441 void TIM_EncoderInterfaceConfig(TIM_TypeDef *TIMx, uint16_t TIM_EncoderMode, 442 uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity); 443 void TIM_ForcedOC1Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction); 444 void TIM_ForcedOC2Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction); 445 void TIM_ForcedOC3Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction); 446 void TIM_ForcedOC4Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction); 447 void TIM_ARRPreloadConfig(TIM_TypeDef *TIMx, FunctionalState NewState); 448 void TIM_SelectCOM(TIM_TypeDef *TIMx, FunctionalState NewState); 449 void TIM_SelectCCDMA(TIM_TypeDef *TIMx, FunctionalState NewState); 450 void TIM_CCPreloadControl(TIM_TypeDef *TIMx, FunctionalState NewState); 451 void TIM_OC1PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload); 452 void TIM_OC2PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload); 453 void TIM_OC3PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload); 454 void TIM_OC4PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload); 455 void TIM_OC1FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast); 456 void TIM_OC2FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast); 457 void TIM_OC3FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast); 458 void TIM_OC4FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast); 459 void TIM_ClearOC1Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear); 460 void TIM_ClearOC2Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear); 461 void TIM_ClearOC3Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear); 462 void TIM_ClearOC4Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear); 463 void TIM_OC1PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity); 464 void TIM_OC1NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity); 465 void TIM_OC2PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity); 466 void TIM_OC2NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity); 467 void TIM_OC3PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity); 468 void TIM_OC3NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity); 469 void TIM_OC4PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity); 470 void TIM_CCxCmd(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx); 471 void TIM_CCxNCmd(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN); 472 void TIM_SelectOCxM(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode); 473 void TIM_UpdateDisableConfig(TIM_TypeDef *TIMx, FunctionalState NewState); 474 void TIM_UpdateRequestConfig(TIM_TypeDef *TIMx, uint16_t TIM_UpdateSource); 475 void TIM_SelectHallSensor(TIM_TypeDef *TIMx, FunctionalState NewState); 476 void TIM_SelectOnePulseMode(TIM_TypeDef *TIMx, uint16_t TIM_OPMode); 477 void TIM_SelectOutputTrigger(TIM_TypeDef *TIMx, uint16_t TIM_TRGOSource); 478 void TIM_SelectSlaveMode(TIM_TypeDef *TIMx, uint16_t TIM_SlaveMode); 479 void TIM_SelectMasterSlaveMode(TIM_TypeDef *TIMx, uint16_t TIM_MasterSlaveMode); 480 void TIM_SetCounter(TIM_TypeDef *TIMx, uint16_t Counter); 481 void TIM_SetAutoreload(TIM_TypeDef *TIMx, uint16_t Autoreload); 482 void TIM_SetCompare1(TIM_TypeDef *TIMx, uint16_t Compare1); 483 void TIM_SetCompare2(TIM_TypeDef *TIMx, uint16_t Compare2); 484 void TIM_SetCompare3(TIM_TypeDef *TIMx, uint16_t Compare3); 485 void TIM_SetCompare4(TIM_TypeDef *TIMx, uint16_t Compare4); 486 void TIM_SetIC1Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC); 487 void TIM_SetIC2Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC); 488 void TIM_SetIC3Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC); 489 void TIM_SetIC4Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC); 490 void TIM_SetClockDivision(TIM_TypeDef *TIMx, uint16_t TIM_CKD); 491 uint16_t TIM_GetCapture1(TIM_TypeDef *TIMx); 492 uint16_t TIM_GetCapture2(TIM_TypeDef *TIMx); 493 uint16_t TIM_GetCapture3(TIM_TypeDef *TIMx); 494 uint16_t TIM_GetCapture4(TIM_TypeDef *TIMx); 495 uint16_t TIM_GetCounter(TIM_TypeDef *TIMx); 496 uint16_t TIM_GetPrescaler(TIM_TypeDef *TIMx); 497 FlagStatus TIM_GetFlagStatus(TIM_TypeDef *TIMx, uint16_t TIM_FLAG); 498 void TIM_ClearFlag(TIM_TypeDef *TIMx, uint16_t TIM_FLAG); 499 ITStatus TIM_GetITStatus(TIM_TypeDef *TIMx, uint16_t TIM_IT); 500 void TIM_ClearITPendingBit(TIM_TypeDef *TIMx, uint16_t TIM_IT); 501 502 #ifdef __cplusplus 503 } 504 #endif 505 506 #endif /*__CH32V10x_TIM_H */ 507