1 /* 2 * Copyright (c) 2006-2023, RT-Thread Development Team 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 * 2022-07-15 Emuzit first version 9 */ 10 #ifndef __CH56X_TIMER_H__ 11 #define __CH56X_TIMER_H__ 12 13 #include "soc.h" 14 15 #ifdef __cplusplus 16 extern "C" { 17 #endif 18 19 union _timer_ctrl_mod 20 { 21 uint8_t reg; 22 struct 23 { 24 uint8_t mode_in : 1; // B.0 : RW, timer mode setting 25 uint8_t all_clear : 1; // B.1 : RW, clear FIFO/count/int-flag 26 uint8_t count_en : 1; // B.2 : RW, enable timer module 27 uint8_t out_en : 1; // B.3 : RW, timer output enable 28 uint8_t out_polar : 1; // B.4 : RW, output polarity for PWM mode 29 uint8_t resv_5 : 1; 30 uint8_t pwm_repeat : 2; // B.7-6 : RW, PWM repeat count, 1/4/8/16 31 }; 32 struct 33 { 34 uint8_t stuff_0 : 6; 35 uint8_t cap_edge : 2; // B.7-6 : RW, capture edge mode 36 }; 37 }; 38 #define RB_TMR_MODE_IN 0x01 39 #define RB_TMR_ALL_CLEAR 0x02 40 #define RB_TMR_COUNT_EN 0x04 41 #define RB_TMR_OUT_EN 0x08 42 #define RB_TMR_OUT_POLAR 0x10 43 #define RB_TMR_CAP_COUNT 0x10 44 #define RB_TMR_PWM_REPEAT 0xc0 45 #define RB_TMR_CAP_EDGE 0xc0 46 47 #define TMR_MODE_TIMER_PWM 0 48 #define TMR_MODE_CAP_COUNT 1 49 #define TMR_PWM_REPEAT_1 0 50 #define TMR_PWM_REPEAT_4 1 51 #define TMR_PWM_REPEAT_8 2 52 #define TMR_PWM_REPEAT_16 3 53 #define TMR_CAP_EDGE_NONE 0 54 #define TMR_CAP_EDGE_BOTH 1 55 #define TMR_CAP_EDGE_F2F 2 56 #define TMR_CAP_EDGE_R2R 3 57 58 union _timer_ctrl_dma 59 { 60 uint8_t reg; 61 struct 62 { 63 uint8_t dma_enable : 1; // B.0 : RW, enable DMA 64 uint8_t resv_1 : 1; 65 uint8_t dma_loop : 1; // B.2 : RW, enable DMA address looping 66 uint8_t resv_3 : 5; 67 }; 68 }; 69 #define RB_TMR_DMA_ENABLE 0x01 70 #define RB_TMR_DMA_LOOP 0x04 71 72 union _timer_interrupt 73 { 74 uint8_t reg; 75 struct 76 { 77 uint8_t cyc_end : 1; // B.0 78 uint8_t data_act : 1; // B.1 79 uint8_t fifo_hf : 1; // B.2 80 uint8_t dma_end : 1; // B.3 81 uint8_t fifo_ov : 1; // B.4 82 uint8_t resv_5 : 3; 83 }; 84 }; 85 #define RB_TMR_IX_MASK 0x1f 86 #define RB_TMR_IE_CYC_END 0x01 // RW, enable interrupt for timer capture count timeout or PWM cycle end 87 #define RB_TMR_IE_DATA_ACT 0x02 // RW, enable interrupt for timer capture input action or PWM trigger 88 #define RB_TMR_IE_FIFO_HF 0x04 // RW, enable interrupt for timer FIFO half (capture fifo >=4 or PWM fifo <=3) 89 #define RB_TMR_IE_DMA_END 0x08 // RW, enable interrupt for timer1/2 DMA completion 90 #define RB_TMR_IE_FIFO_OV 0x10 // RW, enable interrupt for timer FIFO overflow 91 92 #define RB_TMR_IF_CYC_END 0x01 // RW1, interrupt flag for timer capture count timeout or PWM cycle end 93 #define RB_TMR_IF_DATA_ACT 0x02 // RW1, interrupt flag for timer capture input action or PWM trigger 94 #define RB_TMR_IF_FIFO_HF 0x04 // RW1, interrupt flag for timer FIFO half (capture fifo >=4 or PWM fifo <=3) 95 #define RB_TMR_IF_DMA_END 0x08 // RW1, interrupt flag for timer1/2 DMA completion 96 #define RB_TMR_IF_FIFO_OV 0x10 // RW1, interrupt flag for timer FIFO overflow 97 98 /* 99 * 0x00 R8_TMRx_CTRL_MOD: mode setting register 100 * 0x01 R8_TMRx_CTRL_DMA: DMA control register 101 * 0x02 R8_TMRx_INTER_EN: interrupt enable register 102 * 0x06 R8_TMRx_INT_FLAG: interrupt flag register 103 * 0x07 R8_TMRx_FIFO_COUNT: RO, FIFO count register 104 * 0x08 R32_TMRx_COUNT: RO, timer current count register 105 * 0x0c R32_TMRx_CNT_END: RW, timer count end register 106 * 0x10 R32_TMRx_FIFO: RO/WO, FIFO data register, LSB 26 bits 107 * 0x14 R32_TMRx_DMA_NOW: RW, DMA buffer current address, LSB 18 bits 108 * 0x18 R32_TMRx_DMA_BEG: RW, DMA buffer begin address, LSB 18 bits 109 * 0x1c R32_TMRx_DMA_END: RW, DMA buffer end address (exclusive), LSB 18 bits 110 * 111 * Note: DMA related registers (0x10,0x14,0x18,0x1c) are TMR1/2 only 112 * 113 * CAVEAT: gcc (as of 8.2.0) tends to read 32-bit word for bit field test. 114 * Be careful for those with side effect for read. 115 */ 116 struct timer_registers 117 { 118 union _timer_ctrl_mod CTRL_MOD; 119 union _timer_ctrl_dma CTRL_DMA; 120 union _timer_interrupt INTER_EN; 121 uint8_t resv_3[3]; 122 union _timer_interrupt INT_FLAG; 123 uint8_t FIFO_COUNT; 124 uint32_t COUNT; 125 uint32_t CNT_END; 126 uint32_t FIFO; 127 uint32_t DMA_NOW; 128 uint32_t DMA_BEG; 129 uint32_t DMA_END; 130 } __packed; 131 132 CHECK_STRUCT_SIZE(struct timer_registers, 0x20); 133 134 #ifdef __cplusplus 135 } 136 #endif 137 138 #endif 139