1 /*
2 * Copyright (c) 2006-2023, RT-Thread Development Team
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Change Logs:
7 * Date Author Notes
8 * 2022-07-15 Emuzit first version
9 */
10 #include <rthw.h>
11 #include <ipc/completion.h>
12 #include <ipc/dataqueue.h>
13 #ifdef RT_USING_SERIAL_V2
14 #include <drivers/dev_serial_v2.h>
15 #else
16 #include <drivers/dev_serial.h>
17 #endif
18 #include <drivers/dev_pin.h>
19 #include "ch56x_sys.h"
20 #include "ch56x_uart.h"
21 #include "isr_sp.h"
22
23 #if !defined(BSP_USING_UART0) && !defined(BSP_USING_UART1) && \
24 !defined(BSP_USING_UART2) && !defined(BSP_USING_UART3)
25 #error "Please define at least one UARTx"
26 #endif
27
28 /* Type of irqn/rxd_pin/txd_pin are per uart driver perspective
29 * to save some space, still compatible to RT api call, anyway.
30 */
31 struct serial_device
32 {
33 struct rt_serial_device parent;
34 volatile struct uart_registers *reg_base;
35 uint8_t irqn;
36 uint8_t resv;
37 uint8_t rxd_pin;
38 uint8_t txd_pin;
39 char *name;
40 };
41
42 #ifdef BSP_USING_UART0
43 static struct serial_device serial_device_0 =
44 {
45 .reg_base = (struct uart_registers *)UART0_REG_BASE,
46 .irqn = UART0_IRQn,
47 #ifndef BSP_USING_UART0_PIN_ALT
48 .rxd_pin = UART_RXD0_PIN,
49 .txd_pin = UART_TXD0_PIN,
50 #else
51 .rxd_pin = UART_RXD0_ALT,
52 .txd_pin = UART_TXD0_ALT,
53 #endif
54 .name = "uart0",
55 };
56 #endif
57
58 #ifdef BSP_USING_UART1
59 static struct serial_device serial_device_1 =
60 {
61 .reg_base = (struct uart_registers *)UART1_REG_BASE,
62 .irqn = UART1_IRQn,
63 .rxd_pin = UART_RXD1_PIN,
64 .txd_pin = UART_TXD1_PIN,
65 .name = "uart1",
66 };
67 #endif
68
69 #ifdef BSP_USING_UART2
70 static struct serial_device serial_device_2 =
71 {
72 .reg_base = (struct uart_registers *)UART2_REG_BASE,
73 .irqn = UART2_IRQn,
74 .rxd_pin = UART_RXD2_PIN,
75 .txd_pin = UART_TXD2_PIN,
76 .name = "uart2",
77 };
78 #endif
79
80 #ifdef BSP_USING_UART3
81 static struct serial_device serial_device_3 =
82 {
83 .reg_base = (struct uart_registers *)UART3_REG_BASE,
84 .irqn = UART3_IRQn,
85 .rxd_pin = UART_RXD3_PIN,
86 .txd_pin = UART_TXD3_PIN,
87 .name = "uart3",
88 };
89 #endif
90
uart_configure(struct rt_serial_device * serial,struct serial_configure * cfg)91 static rt_err_t uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
92 {
93 struct serial_device *serial_device = (struct serial_device *)serial;
94 volatile struct uart_registers *uxreg = serial_device->reg_base;
95
96 union _uart_fcr fcr;
97 union _uart_lcr lcr;
98 uint32_t x;
99
100 x = 10 * sys_hclk_get() / 8 / cfg->baud_rate;
101 x = (x + 5) / 10;
102 uxreg->DL = x;
103 uxreg->DIV = 1;
104
105 lcr.reg = 0;
106 switch (cfg->data_bits)
107 {
108 case DATA_BITS_5:
109 lcr.word_sz = LCR_DATA_BITS_5;
110 break;
111 case DATA_BITS_6:
112 lcr.word_sz = LCR_DATA_BITS_6;
113 break;
114 case DATA_BITS_7:
115 lcr.word_sz = LCR_DATA_BITS_7;
116 break;
117 case DATA_BITS_8:
118 default:
119 lcr.word_sz = LCR_DATA_BITS_8;
120 break;
121 }
122
123 switch (cfg->stop_bits)
124 {
125 case STOP_BITS_2:
126 lcr.stop_bit = LCR_STOP_BITS_2;
127 break;
128 case STOP_BITS_1:
129 default:
130 lcr.stop_bit = LCR_STOP_BITS_1;
131 break;
132 }
133
134 switch (cfg->parity)
135 {
136 case PARITY_ODD:
137 lcr.par_mod = LCR_PARITY_ODD;
138 lcr.par_en = 1;
139 break;
140 case PARITY_EVEN:
141 lcr.par_mod = LCR_PARITY_EVEN;
142 lcr.par_en = 1;
143 break;
144 case PARITY_NONE:
145 default:
146 lcr.par_en = 0;
147 break;
148 }
149 uxreg->LCR.reg = lcr.reg;
150
151 fcr.reg = RB_FCR_FIFO_EN | RB_FCR_RX_FIFO_CLR | RB_FCR_TX_FIFO_CLR;
152 fcr.fifo_trig = UART_1BYTE_TRIG;
153 uxreg->FCR.reg = fcr.reg;
154
155 /* TXD pin output enable */
156 uxreg->IER.txd_en = 1;
157
158 return RT_EOK;
159 }
160
uart_control(struct rt_serial_device * serial,int cmd,void * args)161 static rt_err_t uart_control(struct rt_serial_device *serial, int cmd, void *args)
162 {
163 struct serial_device *serial_device = (struct serial_device *)serial;
164 volatile struct uart_registers *uxreg = serial_device->reg_base;
165
166 switch (cmd)
167 {
168 case RT_DEVICE_CTRL_CLR_INT:
169 uxreg->IER.recv_rdy = 0;
170 uxreg->IER.line_stat = 0;
171 uxreg->IER.thr_empty = 0;
172 rt_hw_interrupt_mask(serial_device->irqn);
173 break;
174 case RT_DEVICE_CTRL_SET_INT:
175 uxreg->FCR.fifo_trig = UART_1BYTE_TRIG;
176 uxreg->MCR.int_oe = 1;
177 uxreg->IER.recv_rdy = 1;
178 uxreg->IER.line_stat = 1;
179 if (serial->parent.open_flag & RT_DEVICE_FLAG_INT_TX)
180 {
181 uxreg->IER.thr_empty = 1;
182 }
183 rt_hw_interrupt_umask(serial_device->irqn);
184 break;
185 default:
186 break;
187 }
188
189 return RT_EOK;
190 }
191
uart_putc(struct rt_serial_device * serial,char ch)192 static int uart_putc(struct rt_serial_device *serial, char ch)
193 {
194 struct serial_device *serial_device = (struct serial_device *)serial;
195 volatile struct uart_registers *uxreg = serial_device->reg_base;
196
197 if (serial->parent.open_flag & RT_DEVICE_FLAG_INT_TX)
198 {
199 if (uxreg->TFC >= UART_FIFO_SIZE)
200 return -1;
201 }
202 else
203 {
204 while (uxreg->TFC >= UART_FIFO_SIZE)
205 {
206 if (rt_thread_self() && rt_interrupt_get_nest() == 0)
207 rt_thread_yield();
208 }
209 }
210 uxreg->THR = ch;
211
212 return 1;
213 }
214
uart_getc(struct rt_serial_device * serial)215 static int uart_getc(struct rt_serial_device *serial)
216 {
217 struct serial_device *serial_device = (struct serial_device *)serial;
218 volatile struct uart_registers *uxreg = serial_device->reg_base;
219
220 /* UART_II_RECV_RDY is cleared by reading RBR */
221 return (uxreg->RFC > 0) ? uxreg->RBR : -1;
222 }
223
224 static const struct rt_uart_ops uart_ops =
225 {
226 .configure = uart_configure,
227 .control = uart_control,
228 .putc = uart_putc,
229 .getc = uart_getc,
230 .dma_transmit = RT_NULL,
231 };
232
rt_hw_uart_init(void)233 int rt_hw_uart_init(void)
234 {
235 struct serial_device *devices[4];
236
237 /* Note: HCLK should be at least 8MHz for default 115200 baud to work */
238 struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
239
240 int n = 0;
241
242 #ifdef BSP_USING_UART3
243 devices[n++] = &serial_device_3;
244 #endif
245 #ifdef BSP_USING_UART2
246 devices[n++] = &serial_device_2;
247 #endif
248 #ifdef BSP_USING_UART1
249 devices[n++] = &serial_device_1;
250 #endif
251 #ifdef BSP_USING_UART0
252 devices[n++] = &serial_device_0;
253 #endif
254
255 while (--n >= 0)
256 {
257 uint32_t flag;
258 struct serial_device *serial = devices[n];
259 serial->parent.ops = &uart_ops;
260 serial->parent.config = config;
261
262 rt_pin_mode(serial->txd_pin, PIN_MODE_OUTPUT);
263 rt_pin_mode(serial->rxd_pin, PIN_MODE_INPUT_PULLUP);
264
265 sys_clk_off_by_irqn(serial->irqn, SYS_SLP_CLK_ON);
266
267 flag = RT_DEVICE_FLAG_RDWR |
268 RT_DEVICE_FLAG_STREAM | // for converting '\n'
269 RT_DEVICE_FLAG_INT_TX |
270 RT_DEVICE_FLAG_INT_RX ;
271 rt_hw_serial_register(&serial->parent, serial->name, flag, RT_NULL);
272
273 /* rt_serial_open => uart_control with RT_DEVICE_CTRL_SET_INT */
274 }
275
276 return 0;
277 }
278
_uart_isr_common(struct serial_device * serial_device)279 static void _uart_isr_common(struct serial_device *serial_device)
280 {
281 struct rt_serial_device *serial = &serial_device->parent;
282 volatile struct uart_registers *uxreg = serial_device->reg_base;
283
284 switch (uxreg->IIR.int_mask)
285 {
286 case UART_II_RECV_TOUT:
287 /* FIXME: It's a bad idea to read RBR to clear UART_II_RECV_TOUT.
288 * Race condition may happen that actual rx data is dropped.
289 */
290 if (uxreg->RFC == 0)
291 {
292 uxreg->RBR;
293 //rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_TIMEOUT);
294 break;
295 }
296 /* pass through as if UART_II_RECV_RDY */
297 case UART_II_RECV_RDY:
298 rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
299 break;
300 case UART_II_THR_EMPTY:
301 rt_hw_serial_isr(serial, RT_SERIAL_EVENT_TX_DONE);
302 break;
303 case UART_II_LINE_STAT:
304 uxreg->LSR;
305 break;
306 case UART_II_MODEM_CHG:
307 uxreg->MSR;
308 break;
309 case UART_II_SLV_ADDR:
310 uxreg->IIR;
311 break;
312 default:
313 break;
314 }
315 }
316
317 #ifdef BSP_USING_UART0
318 void uart0_irq_handler(void) __attribute__((interrupt()));
uart0_irq_handler(void)319 void uart0_irq_handler(void)
320 {
321 isr_sp_enter();
322 rt_interrupt_enter();
323 _uart_isr_common(&serial_device_0);
324 rt_interrupt_leave();
325 isr_sp_leave();
326 }
327 #endif
328
329 #ifdef BSP_USING_UART1
330 void uart1_irq_handler(void) __attribute__((interrupt()));
uart1_irq_handler(void)331 void uart1_irq_handler(void)
332 {
333 isr_sp_enter();
334 rt_interrupt_enter();
335 _uart_isr_common(&serial_device_1);
336 rt_interrupt_leave();
337 isr_sp_leave();
338 }
339 #endif
340
341 #ifdef BSP_USING_UART2
342 void uart2_irq_handler(void) __attribute__((interrupt()));
uart2_irq_handler(void)343 void uart2_irq_handler(void)
344 {
345 isr_sp_enter();
346 rt_interrupt_enter();
347 _uart_isr_common(&serial_device_2);
348 rt_interrupt_leave();
349 isr_sp_leave();
350 }
351 #endif
352
353 #ifdef BSP_USING_UART3
354 void uart3_irq_handler(void) __attribute__((interrupt()));
uart3_irq_handler(void)355 void uart3_irq_handler(void)
356 {
357 isr_sp_enter();
358 rt_interrupt_enter();
359 _uart_isr_common(&serial_device_3);
360 rt_interrupt_leave();
361 isr_sp_leave();
362 }
363 #endif
364