1 /* 2 * Copyright (c) 2006-2023, RT-Thread Development Team 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 * 2022-07-15 Emuzit first version 9 */ 10 #ifndef __SOC_H__ 11 #define __SOC_H__ 12 13 #include <stdint.h> 14 #include <stddef.h> 15 #include <assert.h> 16 #include <rtdef.h> 17 18 #if !defined(SOC_CH567) && \ 19 !defined(SOC_CH568) && \ 20 !defined(SOC_SERIES_CH569) 21 #define SOC_SERIES_CH569 22 #endif 23 24 #ifndef __packed 25 #define __packed __attribute__((packed)) 26 #endif 27 28 #define CHECK_STRUCT_SIZE(s, size) \ 29 static_assert(sizeof(s) == size, #s " has wrong size") 30 31 #define BITS_SET(x, bits) do x |= bits; while(0) 32 #define BITS_CLR(x, bits) do x &= ~bits; while(0) 33 34 #define FLASH_BASE_ADDRESS 0x00000000 35 #define RAMS_BASE_ADDRESS 0x20000000 36 #define BUS8_BASE_ADDRESS 0x80000000 37 38 #ifdef SOC_SERIES_CH569 39 #define RAMX_BASE_ADDRESS 0x20020000 40 #define RAMS_SIZE 16 41 #else 42 #define RAMS_SIZE 32 43 #endif 44 #define RAMS_END (RAMS_BASE_ADDRESS + RAMS_SIZE * 1024) 45 46 #define SYS_REG_BASE 0x40001000 47 #define GPIO_REG_BASE 0x40001000 48 #define GPIO_REG_BASE_PA 0x40001040 49 #define GPIO_REG_BASE_PB 0x40001060 50 51 #define GPIO_PORTS 2 // 2 ports : PA & PB 52 #define GPIO_PA_PIN_START 0 // PA : pin number 0~31 53 #define GPIO_PB_PIN_START 32 // PB : pin number 32~63 54 55 #ifdef SOC_SERIES_CH569 56 #define GPIO_PA_PIN_MARK 0x00ffffff // PA : bits 0~23 57 #define GPIO_PB_PIN_MARK 0x01ffffff // PB : bits 0~24 58 #else 59 #define GPIO_PA_PIN_MARK 0x0000ffff // PA : bits 0~15 60 #define GPIO_PB_PIN_MARK 0x00003fff // PB : bits 0~13 61 #endif 62 63 #define TMR0_REG_BASE 0x40002000 64 #define TMR1_REG_BASE 0x40002400 65 #define TMR2_REG_BASE 0x40002800 66 67 #define UART0_REG_BASE 0x40003000 68 #define UART1_REG_BASE 0x40003400 69 #define UART2_REG_BASE 0x40003800 70 #define UART3_REG_BASE 0x40003c00 71 72 #define SPI0_REG_BASE 0x40004000 73 #define SPI1_REG_BASE 0x40004400 74 75 #define PWMX_REG_BASE 0x40005000 76 77 #define PFIC_REG_BASE 0xe000e000 78 #define SysTick_REG_BASE 0xe000f000 79 80 #ifdef SOC_SERIES_CH569 81 #define HSPI_REG_BASE 0x40006000 // CH569W 82 #define ECDC_REG_BASE 0x40007000 83 #define USBSS_REG_BASE 0x40008000 84 #define USBHS_REG_BASE 0x40009000 85 #define EMMC_REG_BASE 0x4000a000 86 #define SERDES_REG_BASE 0x4000b000 87 #define ETH_REG_BASE 0x4000c000 // CH565W/CH569W 88 #define DVP_REG_BASE 0x4000e000 // CH565W/CH565M 89 #else 90 #define LED_REG_BASE 0x40006000 91 #define USB0_REG_BASE 0x40008000 // CH567 92 #define USB1_REG_BASE 0x40009000 // CH567 93 #define USB_REG_BASE 0x40009000 // CH568 94 #define SDC_REG_BASE 0x4000a000 95 #define SATA_REG_BASE 0x4000b000 // CH568 96 #define ECDC_REG_BASE 0x4000c400 97 #endif 98 99 #if defined(SOC_SERIES_CH569) 100 typedef enum 101 { 102 PWMX_OFFn = 0, 103 NMI_IRQn = 2, 104 EXC_IRQn = 3, 105 SysTick_IRQn = 12, 106 SWI_IRQn = 14, 107 WDOG_IRQn = 16, 108 TMR0_IRQn = 17, 109 GPIO_IRQn = 18, 110 SPI0_IRQn = 19, 111 USBSS_IRQn = 20, 112 LINK_IRQn = 21, 113 TMR1_IRQn = 22, 114 TMR2_IRQn = 23, 115 UART0_IRQn = 24, 116 USBHS_IRQn = 25, 117 EMMC_IRQn = 26, 118 DVP_IRQn = 27, 119 HSPI_IRQn = 28, 120 SPI1_IRQn = 29, 121 UART1_IRQn = 30, 122 UART2_IRQn = 31, 123 UART3_IRQn = 32, 124 SerDes_IRQn = 33, 125 ETH_IRQn = 34, 126 PMT_IRQn = 35, 127 ECDC_IRQn = 36, 128 END_OF_IRQn 129 } irq_number_t; 130 131 #else 132 133 typedef enum 134 { 135 PWMX_OFFn = 0, 136 SOFT_IRQn = 0, 137 TMR0_IRQn = 1, 138 GPIO_IRQn = 2, 139 SPI0_IRQn = 3, 140 USB0_IRQn = 4, // CH567 141 SATA_IRQn = 4, // CH568 142 TMR1_IRQn = 5, 143 TMR2_IRQn = 6, 144 UART0_IRQn = 7, 145 USB1_IRQn = 8, 146 SDC_IRQn = 9, 147 ECDC_IRQn = 10, 148 LED_IRQn = 11, 149 SPI1_IRQn = 12, 150 UART1_IRQn = 13, 151 UART2_IRQn = 14, 152 UART3_IRQn = 15, 153 END_OF_IRQn 154 } irq_number_t; 155 #endif 156 157 #endif 158